1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
4*4882a593Smuzhiyun * Driver EMU10K1X chips
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Parts of this code were adapted from audigyls.c driver which is
7*4882a593Smuzhiyun * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * BUGS:
10*4882a593Smuzhiyun * --
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * TODO:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * Chips (SB0200 model):
15*4882a593Smuzhiyun * - EMU10K1X-DBQ
16*4882a593Smuzhiyun * - STAC 9708T
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <linux/pci.h>
21*4882a593Smuzhiyun #include <linux/dma-mapping.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <sound/core.h>
25*4882a593Smuzhiyun #include <sound/initval.h>
26*4882a593Smuzhiyun #include <sound/pcm.h>
27*4882a593Smuzhiyun #include <sound/ac97_codec.h>
28*4882a593Smuzhiyun #include <sound/info.h>
29*4882a593Smuzhiyun #include <sound/rawmidi.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun MODULE_AUTHOR("Francisco Moraes <fmoraes@nc.rr.com>");
32*4882a593Smuzhiyun MODULE_DESCRIPTION("EMU10K1X");
33*4882a593Smuzhiyun MODULE_LICENSE("GPL");
34*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{Dell Creative Labs,SB Live!}");
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun // module parameters (see "Module Parameters")
37*4882a593Smuzhiyun static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
38*4882a593Smuzhiyun static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
39*4882a593Smuzhiyun static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun module_param_array(index, int, NULL, 0444);
42*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for the EMU10K1X soundcard.");
43*4882a593Smuzhiyun module_param_array(id, charp, NULL, 0444);
44*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for the EMU10K1X soundcard.");
45*4882a593Smuzhiyun module_param_array(enable, bool, NULL, 0444);
46*4882a593Smuzhiyun MODULE_PARM_DESC(enable, "Enable the EMU10K1X soundcard.");
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun // some definitions were borrowed from emu10k1 driver as they seem to be the same
50*4882a593Smuzhiyun /************************************************************************************************/
51*4882a593Smuzhiyun /* PCI function 0 registers, address = <val> + PCIBASE0 */
52*4882a593Smuzhiyun /************************************************************************************************/
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define PTR 0x00 /* Indexed register set pointer register */
55*4882a593Smuzhiyun /* NOTE: The CHANNELNUM and ADDRESS words can */
56*4882a593Smuzhiyun /* be modified independently of each other. */
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define DATA 0x04 /* Indexed register set data register */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define IPR 0x08 /* Global interrupt pending register */
61*4882a593Smuzhiyun /* Clear pending interrupts by writing a 1 to */
62*4882a593Smuzhiyun /* the relevant bits and zero to the other bits */
63*4882a593Smuzhiyun #define IPR_MIDITRANSBUFEMPTY 0x00000001 /* MIDI UART transmit buffer empty */
64*4882a593Smuzhiyun #define IPR_MIDIRECVBUFEMPTY 0x00000002 /* MIDI UART receive buffer empty */
65*4882a593Smuzhiyun #define IPR_CH_0_LOOP 0x00000800 /* Channel 0 loop */
66*4882a593Smuzhiyun #define IPR_CH_0_HALF_LOOP 0x00000100 /* Channel 0 half loop */
67*4882a593Smuzhiyun #define IPR_CAP_0_LOOP 0x00080000 /* Channel capture loop */
68*4882a593Smuzhiyun #define IPR_CAP_0_HALF_LOOP 0x00010000 /* Channel capture half loop */
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define INTE 0x0c /* Interrupt enable register */
71*4882a593Smuzhiyun #define INTE_MIDITXENABLE 0x00000001 /* Enable MIDI transmit-buffer-empty interrupts */
72*4882a593Smuzhiyun #define INTE_MIDIRXENABLE 0x00000002 /* Enable MIDI receive-buffer-empty interrupts */
73*4882a593Smuzhiyun #define INTE_CH_0_LOOP 0x00000800 /* Channel 0 loop */
74*4882a593Smuzhiyun #define INTE_CH_0_HALF_LOOP 0x00000100 /* Channel 0 half loop */
75*4882a593Smuzhiyun #define INTE_CAP_0_LOOP 0x00080000 /* Channel capture loop */
76*4882a593Smuzhiyun #define INTE_CAP_0_HALF_LOOP 0x00010000 /* Channel capture half loop */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define HCFG 0x14 /* Hardware config register */
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
81*4882a593Smuzhiyun /* NOTE: This should generally never be used. */
82*4882a593Smuzhiyun #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
83*4882a593Smuzhiyun /* Should be set to 1 when the EMU10K1 is */
84*4882a593Smuzhiyun /* completely initialized. */
85*4882a593Smuzhiyun #define GPIO 0x18 /* Defaults: 00001080-Analog, 00001000-SPDIF. */
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /********************************************************************************************************/
93*4882a593Smuzhiyun /* Emu10k1x pointer-offset register set, accessed through the PTR and DATA registers */
94*4882a593Smuzhiyun /********************************************************************************************************/
95*4882a593Smuzhiyun #define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
96*4882a593Smuzhiyun /* One list entry: 4 bytes for DMA address,
97*4882a593Smuzhiyun * 4 bytes for period_size << 16.
98*4882a593Smuzhiyun * One list entry is 8 bytes long.
99*4882a593Smuzhiyun * One list entry for each period in the buffer.
100*4882a593Smuzhiyun */
101*4882a593Smuzhiyun #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
102*4882a593Smuzhiyun #define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
103*4882a593Smuzhiyun #define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA address */
104*4882a593Smuzhiyun #define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size */
105*4882a593Smuzhiyun #define PLAYBACK_POINTER 0x06 /* Playback period pointer. Sample currently in DAC */
106*4882a593Smuzhiyun #define PLAYBACK_UNKNOWN1 0x07
107*4882a593Smuzhiyun #define PLAYBACK_UNKNOWN2 0x08
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Only one capture channel supported */
110*4882a593Smuzhiyun #define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
111*4882a593Smuzhiyun #define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
112*4882a593Smuzhiyun #define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
113*4882a593Smuzhiyun #define CAPTURE_UNKNOWN 0x13
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* From 0x20 - 0x3f, last samples played on each channel */
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #define TRIGGER_CHANNEL 0x40 /* Trigger channel playback */
118*4882a593Smuzhiyun #define TRIGGER_CHANNEL_0 0x00000001 /* Trigger channel 0 */
119*4882a593Smuzhiyun #define TRIGGER_CHANNEL_1 0x00000002 /* Trigger channel 1 */
120*4882a593Smuzhiyun #define TRIGGER_CHANNEL_2 0x00000004 /* Trigger channel 2 */
121*4882a593Smuzhiyun #define TRIGGER_CAPTURE 0x00000100 /* Trigger capture channel */
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #define ROUTING 0x41 /* Setup sound routing ? */
124*4882a593Smuzhiyun #define ROUTING_FRONT_LEFT 0x00000001
125*4882a593Smuzhiyun #define ROUTING_FRONT_RIGHT 0x00000002
126*4882a593Smuzhiyun #define ROUTING_REAR_LEFT 0x00000004
127*4882a593Smuzhiyun #define ROUTING_REAR_RIGHT 0x00000008
128*4882a593Smuzhiyun #define ROUTING_CENTER_LFE 0x00010000
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun #define SPCS0 0x42 /* SPDIF output Channel Status 0 register */
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #define SPCS1 0x43 /* SPDIF output Channel Status 1 register */
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun #define SPCS2 0x44 /* SPDIF output Channel Status 2 register */
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
137*4882a593Smuzhiyun #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
138*4882a593Smuzhiyun #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
139*4882a593Smuzhiyun #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
140*4882a593Smuzhiyun #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
141*4882a593Smuzhiyun #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
142*4882a593Smuzhiyun #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
143*4882a593Smuzhiyun #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
144*4882a593Smuzhiyun #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
145*4882a593Smuzhiyun #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
146*4882a593Smuzhiyun #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
147*4882a593Smuzhiyun #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
148*4882a593Smuzhiyun #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
149*4882a593Smuzhiyun #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
150*4882a593Smuzhiyun #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
151*4882a593Smuzhiyun #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
152*4882a593Smuzhiyun #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
153*4882a593Smuzhiyun #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
154*4882a593Smuzhiyun #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
155*4882a593Smuzhiyun #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
156*4882a593Smuzhiyun #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
157*4882a593Smuzhiyun #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
158*4882a593Smuzhiyun #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #define SPDIF_SELECT 0x45 /* Enables SPDIF or Analogue outputs 0-Analogue, 0x700-SPDIF */
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* This is the MPU port on the card */
163*4882a593Smuzhiyun #define MUDATA 0x47
164*4882a593Smuzhiyun #define MUCMD 0x48
165*4882a593Smuzhiyun #define MUSTAT MUCMD
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* From 0x50 - 0x5f, last samples captured */
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /*
170*4882a593Smuzhiyun * The hardware has 3 channels for playback and 1 for capture.
171*4882a593Smuzhiyun * - channel 0 is the front channel
172*4882a593Smuzhiyun * - channel 1 is the rear channel
173*4882a593Smuzhiyun * - channel 2 is the center/lfe channel
174*4882a593Smuzhiyun * Volume is controlled by the AC97 for the front and rear channels by
175*4882a593Smuzhiyun * the PCM Playback Volume, Sigmatel Surround Playback Volume and
176*4882a593Smuzhiyun * Surround Playback Volume. The Sigmatel 4-Speaker Stereo switch affects
177*4882a593Smuzhiyun * the front/rear channel mixing in the REAR OUT jack. When using the
178*4882a593Smuzhiyun * 4-Speaker Stereo, both front and rear channels will be mixed in the
179*4882a593Smuzhiyun * REAR OUT.
180*4882a593Smuzhiyun * The center/lfe channel has no volume control and cannot be muted during
181*4882a593Smuzhiyun * playback.
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun struct emu10k1x_voice {
185*4882a593Smuzhiyun struct emu10k1x *emu;
186*4882a593Smuzhiyun int number;
187*4882a593Smuzhiyun int use;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun struct emu10k1x_pcm *epcm;
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun struct emu10k1x_pcm {
193*4882a593Smuzhiyun struct emu10k1x *emu;
194*4882a593Smuzhiyun struct snd_pcm_substream *substream;
195*4882a593Smuzhiyun struct emu10k1x_voice *voice;
196*4882a593Smuzhiyun unsigned short running;
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun struct emu10k1x_midi {
200*4882a593Smuzhiyun struct emu10k1x *emu;
201*4882a593Smuzhiyun struct snd_rawmidi *rmidi;
202*4882a593Smuzhiyun struct snd_rawmidi_substream *substream_input;
203*4882a593Smuzhiyun struct snd_rawmidi_substream *substream_output;
204*4882a593Smuzhiyun unsigned int midi_mode;
205*4882a593Smuzhiyun spinlock_t input_lock;
206*4882a593Smuzhiyun spinlock_t output_lock;
207*4882a593Smuzhiyun spinlock_t open_lock;
208*4882a593Smuzhiyun int tx_enable, rx_enable;
209*4882a593Smuzhiyun int port;
210*4882a593Smuzhiyun int ipr_tx, ipr_rx;
211*4882a593Smuzhiyun void (*interrupt)(struct emu10k1x *emu, unsigned int status);
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun // definition of the chip-specific record
215*4882a593Smuzhiyun struct emu10k1x {
216*4882a593Smuzhiyun struct snd_card *card;
217*4882a593Smuzhiyun struct pci_dev *pci;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun unsigned long port;
220*4882a593Smuzhiyun struct resource *res_port;
221*4882a593Smuzhiyun int irq;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun unsigned char revision; /* chip revision */
224*4882a593Smuzhiyun unsigned int serial; /* serial number */
225*4882a593Smuzhiyun unsigned short model; /* subsystem id */
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun spinlock_t emu_lock;
228*4882a593Smuzhiyun spinlock_t voice_lock;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun struct snd_ac97 *ac97;
231*4882a593Smuzhiyun struct snd_pcm *pcm;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun struct emu10k1x_voice voices[3];
234*4882a593Smuzhiyun struct emu10k1x_voice capture_voice;
235*4882a593Smuzhiyun u32 spdif_bits[3]; // SPDIF out setup
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun struct snd_dma_buffer dma_buffer;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun struct emu10k1x_midi midi;
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /* hardware definition */
243*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_emu10k1x_playback_hw = {
244*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP |
245*4882a593Smuzhiyun SNDRV_PCM_INFO_INTERLEAVED |
246*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
247*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
248*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S16_LE,
249*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_48000,
250*4882a593Smuzhiyun .rate_min = 48000,
251*4882a593Smuzhiyun .rate_max = 48000,
252*4882a593Smuzhiyun .channels_min = 2,
253*4882a593Smuzhiyun .channels_max = 2,
254*4882a593Smuzhiyun .buffer_bytes_max = (32*1024),
255*4882a593Smuzhiyun .period_bytes_min = 64,
256*4882a593Smuzhiyun .period_bytes_max = (16*1024),
257*4882a593Smuzhiyun .periods_min = 2,
258*4882a593Smuzhiyun .periods_max = 8,
259*4882a593Smuzhiyun .fifo_size = 0,
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_emu10k1x_capture_hw = {
263*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP |
264*4882a593Smuzhiyun SNDRV_PCM_INFO_INTERLEAVED |
265*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
266*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
267*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S16_LE,
268*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_48000,
269*4882a593Smuzhiyun .rate_min = 48000,
270*4882a593Smuzhiyun .rate_max = 48000,
271*4882a593Smuzhiyun .channels_min = 2,
272*4882a593Smuzhiyun .channels_max = 2,
273*4882a593Smuzhiyun .buffer_bytes_max = (32*1024),
274*4882a593Smuzhiyun .period_bytes_min = 64,
275*4882a593Smuzhiyun .period_bytes_max = (16*1024),
276*4882a593Smuzhiyun .periods_min = 2,
277*4882a593Smuzhiyun .periods_max = 2,
278*4882a593Smuzhiyun .fifo_size = 0,
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
snd_emu10k1x_ptr_read(struct emu10k1x * emu,unsigned int reg,unsigned int chn)281*4882a593Smuzhiyun static unsigned int snd_emu10k1x_ptr_read(struct emu10k1x * emu,
282*4882a593Smuzhiyun unsigned int reg,
283*4882a593Smuzhiyun unsigned int chn)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun unsigned long flags;
286*4882a593Smuzhiyun unsigned int regptr, val;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun regptr = (reg << 16) | chn;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun spin_lock_irqsave(&emu->emu_lock, flags);
291*4882a593Smuzhiyun outl(regptr, emu->port + PTR);
292*4882a593Smuzhiyun val = inl(emu->port + DATA);
293*4882a593Smuzhiyun spin_unlock_irqrestore(&emu->emu_lock, flags);
294*4882a593Smuzhiyun return val;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
snd_emu10k1x_ptr_write(struct emu10k1x * emu,unsigned int reg,unsigned int chn,unsigned int data)297*4882a593Smuzhiyun static void snd_emu10k1x_ptr_write(struct emu10k1x *emu,
298*4882a593Smuzhiyun unsigned int reg,
299*4882a593Smuzhiyun unsigned int chn,
300*4882a593Smuzhiyun unsigned int data)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun unsigned int regptr;
303*4882a593Smuzhiyun unsigned long flags;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun regptr = (reg << 16) | chn;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun spin_lock_irqsave(&emu->emu_lock, flags);
308*4882a593Smuzhiyun outl(regptr, emu->port + PTR);
309*4882a593Smuzhiyun outl(data, emu->port + DATA);
310*4882a593Smuzhiyun spin_unlock_irqrestore(&emu->emu_lock, flags);
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
snd_emu10k1x_intr_enable(struct emu10k1x * emu,unsigned int intrenb)313*4882a593Smuzhiyun static void snd_emu10k1x_intr_enable(struct emu10k1x *emu, unsigned int intrenb)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun unsigned long flags;
316*4882a593Smuzhiyun unsigned int intr_enable;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun spin_lock_irqsave(&emu->emu_lock, flags);
319*4882a593Smuzhiyun intr_enable = inl(emu->port + INTE) | intrenb;
320*4882a593Smuzhiyun outl(intr_enable, emu->port + INTE);
321*4882a593Smuzhiyun spin_unlock_irqrestore(&emu->emu_lock, flags);
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
snd_emu10k1x_intr_disable(struct emu10k1x * emu,unsigned int intrenb)324*4882a593Smuzhiyun static void snd_emu10k1x_intr_disable(struct emu10k1x *emu, unsigned int intrenb)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun unsigned long flags;
327*4882a593Smuzhiyun unsigned int intr_enable;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun spin_lock_irqsave(&emu->emu_lock, flags);
330*4882a593Smuzhiyun intr_enable = inl(emu->port + INTE) & ~intrenb;
331*4882a593Smuzhiyun outl(intr_enable, emu->port + INTE);
332*4882a593Smuzhiyun spin_unlock_irqrestore(&emu->emu_lock, flags);
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
snd_emu10k1x_gpio_write(struct emu10k1x * emu,unsigned int value)335*4882a593Smuzhiyun static void snd_emu10k1x_gpio_write(struct emu10k1x *emu, unsigned int value)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun unsigned long flags;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun spin_lock_irqsave(&emu->emu_lock, flags);
340*4882a593Smuzhiyun outl(value, emu->port + GPIO);
341*4882a593Smuzhiyun spin_unlock_irqrestore(&emu->emu_lock, flags);
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
snd_emu10k1x_pcm_free_substream(struct snd_pcm_runtime * runtime)344*4882a593Smuzhiyun static void snd_emu10k1x_pcm_free_substream(struct snd_pcm_runtime *runtime)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun kfree(runtime->private_data);
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
snd_emu10k1x_pcm_interrupt(struct emu10k1x * emu,struct emu10k1x_voice * voice)349*4882a593Smuzhiyun static void snd_emu10k1x_pcm_interrupt(struct emu10k1x *emu, struct emu10k1x_voice *voice)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct emu10k1x_pcm *epcm;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun if ((epcm = voice->epcm) == NULL)
354*4882a593Smuzhiyun return;
355*4882a593Smuzhiyun if (epcm->substream == NULL)
356*4882a593Smuzhiyun return;
357*4882a593Smuzhiyun #if 0
358*4882a593Smuzhiyun dev_info(emu->card->dev,
359*4882a593Smuzhiyun "IRQ: position = 0x%x, period = 0x%x, size = 0x%x\n",
360*4882a593Smuzhiyun epcm->substream->ops->pointer(epcm->substream),
361*4882a593Smuzhiyun snd_pcm_lib_period_bytes(epcm->substream),
362*4882a593Smuzhiyun snd_pcm_lib_buffer_bytes(epcm->substream));
363*4882a593Smuzhiyun #endif
364*4882a593Smuzhiyun snd_pcm_period_elapsed(epcm->substream);
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /* open callback */
snd_emu10k1x_playback_open(struct snd_pcm_substream * substream)368*4882a593Smuzhiyun static int snd_emu10k1x_playback_open(struct snd_pcm_substream *substream)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun struct emu10k1x *chip = snd_pcm_substream_chip(substream);
371*4882a593Smuzhiyun struct emu10k1x_pcm *epcm;
372*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
373*4882a593Smuzhiyun int err;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) {
376*4882a593Smuzhiyun return err;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
379*4882a593Smuzhiyun return err;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
382*4882a593Smuzhiyun if (epcm == NULL)
383*4882a593Smuzhiyun return -ENOMEM;
384*4882a593Smuzhiyun epcm->emu = chip;
385*4882a593Smuzhiyun epcm->substream = substream;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun runtime->private_data = epcm;
388*4882a593Smuzhiyun runtime->private_free = snd_emu10k1x_pcm_free_substream;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun runtime->hw = snd_emu10k1x_playback_hw;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun return 0;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun /* close callback */
snd_emu10k1x_playback_close(struct snd_pcm_substream * substream)396*4882a593Smuzhiyun static int snd_emu10k1x_playback_close(struct snd_pcm_substream *substream)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun return 0;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun /* hw_params callback */
snd_emu10k1x_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)402*4882a593Smuzhiyun static int snd_emu10k1x_pcm_hw_params(struct snd_pcm_substream *substream,
403*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
406*4882a593Smuzhiyun struct emu10k1x_pcm *epcm = runtime->private_data;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun if (! epcm->voice) {
409*4882a593Smuzhiyun epcm->voice = &epcm->emu->voices[substream->pcm->device];
410*4882a593Smuzhiyun epcm->voice->use = 1;
411*4882a593Smuzhiyun epcm->voice->epcm = epcm;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun return 0;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* hw_free callback */
snd_emu10k1x_pcm_hw_free(struct snd_pcm_substream * substream)418*4882a593Smuzhiyun static int snd_emu10k1x_pcm_hw_free(struct snd_pcm_substream *substream)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
421*4882a593Smuzhiyun struct emu10k1x_pcm *epcm;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun if (runtime->private_data == NULL)
424*4882a593Smuzhiyun return 0;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun epcm = runtime->private_data;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (epcm->voice) {
429*4882a593Smuzhiyun epcm->voice->use = 0;
430*4882a593Smuzhiyun epcm->voice->epcm = NULL;
431*4882a593Smuzhiyun epcm->voice = NULL;
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun return 0;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun /* prepare callback */
snd_emu10k1x_pcm_prepare(struct snd_pcm_substream * substream)438*4882a593Smuzhiyun static int snd_emu10k1x_pcm_prepare(struct snd_pcm_substream *substream)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun struct emu10k1x *emu = snd_pcm_substream_chip(substream);
441*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
442*4882a593Smuzhiyun struct emu10k1x_pcm *epcm = runtime->private_data;
443*4882a593Smuzhiyun int voice = epcm->voice->number;
444*4882a593Smuzhiyun u32 *table_base = (u32 *)(emu->dma_buffer.area+1024*voice);
445*4882a593Smuzhiyun u32 period_size_bytes = frames_to_bytes(runtime, runtime->period_size);
446*4882a593Smuzhiyun int i;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun for(i = 0; i < runtime->periods; i++) {
449*4882a593Smuzhiyun *table_base++=runtime->dma_addr+(i*period_size_bytes);
450*4882a593Smuzhiyun *table_base++=period_size_bytes<<16;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_ADDR, voice, emu->dma_buffer.addr+1024*voice);
454*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_SIZE, voice, (runtime->periods - 1) << 19);
455*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_PTR, voice, 0);
456*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, PLAYBACK_POINTER, voice, 0);
457*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, PLAYBACK_UNKNOWN1, voice, 0);
458*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, PLAYBACK_UNKNOWN2, voice, 0);
459*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, PLAYBACK_DMA_ADDR, voice, runtime->dma_addr);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, PLAYBACK_PERIOD_SIZE, voice, frames_to_bytes(runtime, runtime->period_size)<<16);
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun return 0;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun /* trigger callback */
snd_emu10k1x_pcm_trigger(struct snd_pcm_substream * substream,int cmd)467*4882a593Smuzhiyun static int snd_emu10k1x_pcm_trigger(struct snd_pcm_substream *substream,
468*4882a593Smuzhiyun int cmd)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun struct emu10k1x *emu = snd_pcm_substream_chip(substream);
471*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
472*4882a593Smuzhiyun struct emu10k1x_pcm *epcm = runtime->private_data;
473*4882a593Smuzhiyun int channel = epcm->voice->number;
474*4882a593Smuzhiyun int result = 0;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun /*
477*4882a593Smuzhiyun dev_dbg(emu->card->dev,
478*4882a593Smuzhiyun "trigger - emu10k1x = 0x%x, cmd = %i, pointer = %d\n",
479*4882a593Smuzhiyun (int)emu, cmd, (int)substream->ops->pointer(substream));
480*4882a593Smuzhiyun */
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun switch (cmd) {
483*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
484*4882a593Smuzhiyun if(runtime->periods == 2)
485*4882a593Smuzhiyun snd_emu10k1x_intr_enable(emu, (INTE_CH_0_LOOP | INTE_CH_0_HALF_LOOP) << channel);
486*4882a593Smuzhiyun else
487*4882a593Smuzhiyun snd_emu10k1x_intr_enable(emu, INTE_CH_0_LOOP << channel);
488*4882a593Smuzhiyun epcm->running = 1;
489*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0)|(TRIGGER_CHANNEL_0<<channel));
490*4882a593Smuzhiyun break;
491*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
492*4882a593Smuzhiyun epcm->running = 0;
493*4882a593Smuzhiyun snd_emu10k1x_intr_disable(emu, (INTE_CH_0_LOOP | INTE_CH_0_HALF_LOOP) << channel);
494*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0) & ~(TRIGGER_CHANNEL_0<<channel));
495*4882a593Smuzhiyun break;
496*4882a593Smuzhiyun default:
497*4882a593Smuzhiyun result = -EINVAL;
498*4882a593Smuzhiyun break;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun return result;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun /* pointer callback */
504*4882a593Smuzhiyun static snd_pcm_uframes_t
snd_emu10k1x_pcm_pointer(struct snd_pcm_substream * substream)505*4882a593Smuzhiyun snd_emu10k1x_pcm_pointer(struct snd_pcm_substream *substream)
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun struct emu10k1x *emu = snd_pcm_substream_chip(substream);
508*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
509*4882a593Smuzhiyun struct emu10k1x_pcm *epcm = runtime->private_data;
510*4882a593Smuzhiyun int channel = epcm->voice->number;
511*4882a593Smuzhiyun snd_pcm_uframes_t ptr = 0, ptr1 = 0, ptr2= 0,ptr3 = 0,ptr4 = 0;
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun if (!epcm->running)
514*4882a593Smuzhiyun return 0;
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun ptr3 = snd_emu10k1x_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
517*4882a593Smuzhiyun ptr1 = snd_emu10k1x_ptr_read(emu, PLAYBACK_POINTER, channel);
518*4882a593Smuzhiyun ptr4 = snd_emu10k1x_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun if(ptr4 == 0 && ptr1 == frames_to_bytes(runtime, runtime->buffer_size))
521*4882a593Smuzhiyun return 0;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun if (ptr3 != ptr4)
524*4882a593Smuzhiyun ptr1 = snd_emu10k1x_ptr_read(emu, PLAYBACK_POINTER, channel);
525*4882a593Smuzhiyun ptr2 = bytes_to_frames(runtime, ptr1);
526*4882a593Smuzhiyun ptr2 += (ptr4 >> 3) * runtime->period_size;
527*4882a593Smuzhiyun ptr = ptr2;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun if (ptr >= runtime->buffer_size)
530*4882a593Smuzhiyun ptr -= runtime->buffer_size;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun return ptr;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /* operators */
536*4882a593Smuzhiyun static const struct snd_pcm_ops snd_emu10k1x_playback_ops = {
537*4882a593Smuzhiyun .open = snd_emu10k1x_playback_open,
538*4882a593Smuzhiyun .close = snd_emu10k1x_playback_close,
539*4882a593Smuzhiyun .hw_params = snd_emu10k1x_pcm_hw_params,
540*4882a593Smuzhiyun .hw_free = snd_emu10k1x_pcm_hw_free,
541*4882a593Smuzhiyun .prepare = snd_emu10k1x_pcm_prepare,
542*4882a593Smuzhiyun .trigger = snd_emu10k1x_pcm_trigger,
543*4882a593Smuzhiyun .pointer = snd_emu10k1x_pcm_pointer,
544*4882a593Smuzhiyun };
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun /* open_capture callback */
snd_emu10k1x_pcm_open_capture(struct snd_pcm_substream * substream)547*4882a593Smuzhiyun static int snd_emu10k1x_pcm_open_capture(struct snd_pcm_substream *substream)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun struct emu10k1x *chip = snd_pcm_substream_chip(substream);
550*4882a593Smuzhiyun struct emu10k1x_pcm *epcm;
551*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
552*4882a593Smuzhiyun int err;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
555*4882a593Smuzhiyun return err;
556*4882a593Smuzhiyun if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
557*4882a593Smuzhiyun return err;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
560*4882a593Smuzhiyun if (epcm == NULL)
561*4882a593Smuzhiyun return -ENOMEM;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun epcm->emu = chip;
564*4882a593Smuzhiyun epcm->substream = substream;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun runtime->private_data = epcm;
567*4882a593Smuzhiyun runtime->private_free = snd_emu10k1x_pcm_free_substream;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun runtime->hw = snd_emu10k1x_capture_hw;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun return 0;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun /* close callback */
snd_emu10k1x_pcm_close_capture(struct snd_pcm_substream * substream)575*4882a593Smuzhiyun static int snd_emu10k1x_pcm_close_capture(struct snd_pcm_substream *substream)
576*4882a593Smuzhiyun {
577*4882a593Smuzhiyun return 0;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun /* hw_params callback */
snd_emu10k1x_pcm_hw_params_capture(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)581*4882a593Smuzhiyun static int snd_emu10k1x_pcm_hw_params_capture(struct snd_pcm_substream *substream,
582*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
585*4882a593Smuzhiyun struct emu10k1x_pcm *epcm = runtime->private_data;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun if (! epcm->voice) {
588*4882a593Smuzhiyun if (epcm->emu->capture_voice.use)
589*4882a593Smuzhiyun return -EBUSY;
590*4882a593Smuzhiyun epcm->voice = &epcm->emu->capture_voice;
591*4882a593Smuzhiyun epcm->voice->epcm = epcm;
592*4882a593Smuzhiyun epcm->voice->use = 1;
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun return 0;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun /* hw_free callback */
snd_emu10k1x_pcm_hw_free_capture(struct snd_pcm_substream * substream)599*4882a593Smuzhiyun static int snd_emu10k1x_pcm_hw_free_capture(struct snd_pcm_substream *substream)
600*4882a593Smuzhiyun {
601*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun struct emu10k1x_pcm *epcm;
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun if (runtime->private_data == NULL)
606*4882a593Smuzhiyun return 0;
607*4882a593Smuzhiyun epcm = runtime->private_data;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun if (epcm->voice) {
610*4882a593Smuzhiyun epcm->voice->use = 0;
611*4882a593Smuzhiyun epcm->voice->epcm = NULL;
612*4882a593Smuzhiyun epcm->voice = NULL;
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun return 0;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun /* prepare capture callback */
snd_emu10k1x_pcm_prepare_capture(struct snd_pcm_substream * substream)619*4882a593Smuzhiyun static int snd_emu10k1x_pcm_prepare_capture(struct snd_pcm_substream *substream)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun struct emu10k1x *emu = snd_pcm_substream_chip(substream);
622*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, CAPTURE_DMA_ADDR, 0, runtime->dma_addr);
625*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, CAPTURE_BUFFER_SIZE, 0, frames_to_bytes(runtime, runtime->buffer_size)<<16); // buffer size in bytes
626*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, CAPTURE_POINTER, 0, 0);
627*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, CAPTURE_UNKNOWN, 0, 0);
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun return 0;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun /* trigger_capture callback */
snd_emu10k1x_pcm_trigger_capture(struct snd_pcm_substream * substream,int cmd)633*4882a593Smuzhiyun static int snd_emu10k1x_pcm_trigger_capture(struct snd_pcm_substream *substream,
634*4882a593Smuzhiyun int cmd)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun struct emu10k1x *emu = snd_pcm_substream_chip(substream);
637*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
638*4882a593Smuzhiyun struct emu10k1x_pcm *epcm = runtime->private_data;
639*4882a593Smuzhiyun int result = 0;
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun switch (cmd) {
642*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
643*4882a593Smuzhiyun snd_emu10k1x_intr_enable(emu, INTE_CAP_0_LOOP |
644*4882a593Smuzhiyun INTE_CAP_0_HALF_LOOP);
645*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0)|TRIGGER_CAPTURE);
646*4882a593Smuzhiyun epcm->running = 1;
647*4882a593Smuzhiyun break;
648*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
649*4882a593Smuzhiyun epcm->running = 0;
650*4882a593Smuzhiyun snd_emu10k1x_intr_disable(emu, INTE_CAP_0_LOOP |
651*4882a593Smuzhiyun INTE_CAP_0_HALF_LOOP);
652*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0) & ~(TRIGGER_CAPTURE));
653*4882a593Smuzhiyun break;
654*4882a593Smuzhiyun default:
655*4882a593Smuzhiyun result = -EINVAL;
656*4882a593Smuzhiyun break;
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun return result;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun /* pointer_capture callback */
662*4882a593Smuzhiyun static snd_pcm_uframes_t
snd_emu10k1x_pcm_pointer_capture(struct snd_pcm_substream * substream)663*4882a593Smuzhiyun snd_emu10k1x_pcm_pointer_capture(struct snd_pcm_substream *substream)
664*4882a593Smuzhiyun {
665*4882a593Smuzhiyun struct emu10k1x *emu = snd_pcm_substream_chip(substream);
666*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
667*4882a593Smuzhiyun struct emu10k1x_pcm *epcm = runtime->private_data;
668*4882a593Smuzhiyun snd_pcm_uframes_t ptr;
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun if (!epcm->running)
671*4882a593Smuzhiyun return 0;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun ptr = bytes_to_frames(runtime, snd_emu10k1x_ptr_read(emu, CAPTURE_POINTER, 0));
674*4882a593Smuzhiyun if (ptr >= runtime->buffer_size)
675*4882a593Smuzhiyun ptr -= runtime->buffer_size;
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun return ptr;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun static const struct snd_pcm_ops snd_emu10k1x_capture_ops = {
681*4882a593Smuzhiyun .open = snd_emu10k1x_pcm_open_capture,
682*4882a593Smuzhiyun .close = snd_emu10k1x_pcm_close_capture,
683*4882a593Smuzhiyun .hw_params = snd_emu10k1x_pcm_hw_params_capture,
684*4882a593Smuzhiyun .hw_free = snd_emu10k1x_pcm_hw_free_capture,
685*4882a593Smuzhiyun .prepare = snd_emu10k1x_pcm_prepare_capture,
686*4882a593Smuzhiyun .trigger = snd_emu10k1x_pcm_trigger_capture,
687*4882a593Smuzhiyun .pointer = snd_emu10k1x_pcm_pointer_capture,
688*4882a593Smuzhiyun };
689*4882a593Smuzhiyun
snd_emu10k1x_ac97_read(struct snd_ac97 * ac97,unsigned short reg)690*4882a593Smuzhiyun static unsigned short snd_emu10k1x_ac97_read(struct snd_ac97 *ac97,
691*4882a593Smuzhiyun unsigned short reg)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun struct emu10k1x *emu = ac97->private_data;
694*4882a593Smuzhiyun unsigned long flags;
695*4882a593Smuzhiyun unsigned short val;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun spin_lock_irqsave(&emu->emu_lock, flags);
698*4882a593Smuzhiyun outb(reg, emu->port + AC97ADDRESS);
699*4882a593Smuzhiyun val = inw(emu->port + AC97DATA);
700*4882a593Smuzhiyun spin_unlock_irqrestore(&emu->emu_lock, flags);
701*4882a593Smuzhiyun return val;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun
snd_emu10k1x_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)704*4882a593Smuzhiyun static void snd_emu10k1x_ac97_write(struct snd_ac97 *ac97,
705*4882a593Smuzhiyun unsigned short reg, unsigned short val)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun struct emu10k1x *emu = ac97->private_data;
708*4882a593Smuzhiyun unsigned long flags;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun spin_lock_irqsave(&emu->emu_lock, flags);
711*4882a593Smuzhiyun outb(reg, emu->port + AC97ADDRESS);
712*4882a593Smuzhiyun outw(val, emu->port + AC97DATA);
713*4882a593Smuzhiyun spin_unlock_irqrestore(&emu->emu_lock, flags);
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
snd_emu10k1x_ac97(struct emu10k1x * chip)716*4882a593Smuzhiyun static int snd_emu10k1x_ac97(struct emu10k1x *chip)
717*4882a593Smuzhiyun {
718*4882a593Smuzhiyun struct snd_ac97_bus *pbus;
719*4882a593Smuzhiyun struct snd_ac97_template ac97;
720*4882a593Smuzhiyun int err;
721*4882a593Smuzhiyun static const struct snd_ac97_bus_ops ops = {
722*4882a593Smuzhiyun .write = snd_emu10k1x_ac97_write,
723*4882a593Smuzhiyun .read = snd_emu10k1x_ac97_read,
724*4882a593Smuzhiyun };
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
727*4882a593Smuzhiyun return err;
728*4882a593Smuzhiyun pbus->no_vra = 1; /* we don't need VRA */
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun memset(&ac97, 0, sizeof(ac97));
731*4882a593Smuzhiyun ac97.private_data = chip;
732*4882a593Smuzhiyun ac97.scaps = AC97_SCAP_NO_SPDIF;
733*4882a593Smuzhiyun return snd_ac97_mixer(pbus, &ac97, &chip->ac97);
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
snd_emu10k1x_free(struct emu10k1x * chip)736*4882a593Smuzhiyun static int snd_emu10k1x_free(struct emu10k1x *chip)
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun snd_emu10k1x_ptr_write(chip, TRIGGER_CHANNEL, 0, 0);
739*4882a593Smuzhiyun // disable interrupts
740*4882a593Smuzhiyun outl(0, chip->port + INTE);
741*4882a593Smuzhiyun // disable audio
742*4882a593Smuzhiyun outl(HCFG_LOCKSOUNDCACHE, chip->port + HCFG);
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun /* release the irq */
745*4882a593Smuzhiyun if (chip->irq >= 0)
746*4882a593Smuzhiyun free_irq(chip->irq, chip);
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun // release the i/o port
749*4882a593Smuzhiyun release_and_free_resource(chip->res_port);
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun // release the DMA
752*4882a593Smuzhiyun if (chip->dma_buffer.area) {
753*4882a593Smuzhiyun snd_dma_free_pages(&chip->dma_buffer);
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun pci_disable_device(chip->pci);
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun // release the data
759*4882a593Smuzhiyun kfree(chip);
760*4882a593Smuzhiyun return 0;
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun
snd_emu10k1x_dev_free(struct snd_device * device)763*4882a593Smuzhiyun static int snd_emu10k1x_dev_free(struct snd_device *device)
764*4882a593Smuzhiyun {
765*4882a593Smuzhiyun struct emu10k1x *chip = device->device_data;
766*4882a593Smuzhiyun return snd_emu10k1x_free(chip);
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun
snd_emu10k1x_interrupt(int irq,void * dev_id)769*4882a593Smuzhiyun static irqreturn_t snd_emu10k1x_interrupt(int irq, void *dev_id)
770*4882a593Smuzhiyun {
771*4882a593Smuzhiyun unsigned int status;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun struct emu10k1x *chip = dev_id;
774*4882a593Smuzhiyun struct emu10k1x_voice *pvoice = chip->voices;
775*4882a593Smuzhiyun int i;
776*4882a593Smuzhiyun int mask;
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun status = inl(chip->port + IPR);
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun if (! status)
781*4882a593Smuzhiyun return IRQ_NONE;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun // capture interrupt
784*4882a593Smuzhiyun if (status & (IPR_CAP_0_LOOP | IPR_CAP_0_HALF_LOOP)) {
785*4882a593Smuzhiyun struct emu10k1x_voice *cap_voice = &chip->capture_voice;
786*4882a593Smuzhiyun if (cap_voice->use)
787*4882a593Smuzhiyun snd_emu10k1x_pcm_interrupt(chip, cap_voice);
788*4882a593Smuzhiyun else
789*4882a593Smuzhiyun snd_emu10k1x_intr_disable(chip,
790*4882a593Smuzhiyun INTE_CAP_0_LOOP |
791*4882a593Smuzhiyun INTE_CAP_0_HALF_LOOP);
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun mask = IPR_CH_0_LOOP|IPR_CH_0_HALF_LOOP;
795*4882a593Smuzhiyun for (i = 0; i < 3; i++) {
796*4882a593Smuzhiyun if (status & mask) {
797*4882a593Smuzhiyun if (pvoice->use)
798*4882a593Smuzhiyun snd_emu10k1x_pcm_interrupt(chip, pvoice);
799*4882a593Smuzhiyun else
800*4882a593Smuzhiyun snd_emu10k1x_intr_disable(chip, mask);
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun pvoice++;
803*4882a593Smuzhiyun mask <<= 1;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun if (status & (IPR_MIDITRANSBUFEMPTY|IPR_MIDIRECVBUFEMPTY)) {
807*4882a593Smuzhiyun if (chip->midi.interrupt)
808*4882a593Smuzhiyun chip->midi.interrupt(chip, status);
809*4882a593Smuzhiyun else
810*4882a593Smuzhiyun snd_emu10k1x_intr_disable(chip, INTE_MIDITXENABLE|INTE_MIDIRXENABLE);
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun // acknowledge the interrupt if necessary
814*4882a593Smuzhiyun outl(status, chip->port + IPR);
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun /* dev_dbg(chip->card->dev, "interrupt %08x\n", status); */
817*4882a593Smuzhiyun return IRQ_HANDLED;
818*4882a593Smuzhiyun }
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun static const struct snd_pcm_chmap_elem surround_map[] = {
821*4882a593Smuzhiyun { .channels = 2,
822*4882a593Smuzhiyun .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
823*4882a593Smuzhiyun { }
824*4882a593Smuzhiyun };
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun static const struct snd_pcm_chmap_elem clfe_map[] = {
827*4882a593Smuzhiyun { .channels = 2,
828*4882a593Smuzhiyun .map = { SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE } },
829*4882a593Smuzhiyun { }
830*4882a593Smuzhiyun };
831*4882a593Smuzhiyun
snd_emu10k1x_pcm(struct emu10k1x * emu,int device)832*4882a593Smuzhiyun static int snd_emu10k1x_pcm(struct emu10k1x *emu, int device)
833*4882a593Smuzhiyun {
834*4882a593Smuzhiyun struct snd_pcm *pcm;
835*4882a593Smuzhiyun const struct snd_pcm_chmap_elem *map = NULL;
836*4882a593Smuzhiyun int err;
837*4882a593Smuzhiyun int capture = 0;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun if (device == 0)
840*4882a593Smuzhiyun capture = 1;
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun if ((err = snd_pcm_new(emu->card, "emu10k1x", device, 1, capture, &pcm)) < 0)
843*4882a593Smuzhiyun return err;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun pcm->private_data = emu;
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun switch(device) {
848*4882a593Smuzhiyun case 0:
849*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1x_playback_ops);
850*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_emu10k1x_capture_ops);
851*4882a593Smuzhiyun break;
852*4882a593Smuzhiyun case 1:
853*4882a593Smuzhiyun case 2:
854*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1x_playback_ops);
855*4882a593Smuzhiyun break;
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun pcm->info_flags = 0;
859*4882a593Smuzhiyun switch(device) {
860*4882a593Smuzhiyun case 0:
861*4882a593Smuzhiyun strcpy(pcm->name, "EMU10K1X Front");
862*4882a593Smuzhiyun map = snd_pcm_std_chmaps;
863*4882a593Smuzhiyun break;
864*4882a593Smuzhiyun case 1:
865*4882a593Smuzhiyun strcpy(pcm->name, "EMU10K1X Rear");
866*4882a593Smuzhiyun map = surround_map;
867*4882a593Smuzhiyun break;
868*4882a593Smuzhiyun case 2:
869*4882a593Smuzhiyun strcpy(pcm->name, "EMU10K1X Center/LFE");
870*4882a593Smuzhiyun map = clfe_map;
871*4882a593Smuzhiyun break;
872*4882a593Smuzhiyun }
873*4882a593Smuzhiyun emu->pcm = pcm;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
876*4882a593Smuzhiyun &emu->pci->dev, 32*1024, 32*1024);
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, map, 2,
879*4882a593Smuzhiyun 1 << 2, NULL);
880*4882a593Smuzhiyun }
881*4882a593Smuzhiyun
snd_emu10k1x_create(struct snd_card * card,struct pci_dev * pci,struct emu10k1x ** rchip)882*4882a593Smuzhiyun static int snd_emu10k1x_create(struct snd_card *card,
883*4882a593Smuzhiyun struct pci_dev *pci,
884*4882a593Smuzhiyun struct emu10k1x **rchip)
885*4882a593Smuzhiyun {
886*4882a593Smuzhiyun struct emu10k1x *chip;
887*4882a593Smuzhiyun int err;
888*4882a593Smuzhiyun int ch;
889*4882a593Smuzhiyun static const struct snd_device_ops ops = {
890*4882a593Smuzhiyun .dev_free = snd_emu10k1x_dev_free,
891*4882a593Smuzhiyun };
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun *rchip = NULL;
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun if ((err = pci_enable_device(pci)) < 0)
896*4882a593Smuzhiyun return err;
897*4882a593Smuzhiyun if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
898*4882a593Smuzhiyun pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
899*4882a593Smuzhiyun dev_err(card->dev, "error to set 28bit mask DMA\n");
900*4882a593Smuzhiyun pci_disable_device(pci);
901*4882a593Smuzhiyun return -ENXIO;
902*4882a593Smuzhiyun }
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun chip = kzalloc(sizeof(*chip), GFP_KERNEL);
905*4882a593Smuzhiyun if (chip == NULL) {
906*4882a593Smuzhiyun pci_disable_device(pci);
907*4882a593Smuzhiyun return -ENOMEM;
908*4882a593Smuzhiyun }
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun chip->card = card;
911*4882a593Smuzhiyun chip->pci = pci;
912*4882a593Smuzhiyun chip->irq = -1;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun spin_lock_init(&chip->emu_lock);
915*4882a593Smuzhiyun spin_lock_init(&chip->voice_lock);
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun chip->port = pci_resource_start(pci, 0);
918*4882a593Smuzhiyun if ((chip->res_port = request_region(chip->port, 8,
919*4882a593Smuzhiyun "EMU10K1X")) == NULL) {
920*4882a593Smuzhiyun dev_err(card->dev, "cannot allocate the port 0x%lx\n",
921*4882a593Smuzhiyun chip->port);
922*4882a593Smuzhiyun snd_emu10k1x_free(chip);
923*4882a593Smuzhiyun return -EBUSY;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun if (request_irq(pci->irq, snd_emu10k1x_interrupt,
927*4882a593Smuzhiyun IRQF_SHARED, KBUILD_MODNAME, chip)) {
928*4882a593Smuzhiyun dev_err(card->dev, "cannot grab irq %d\n", pci->irq);
929*4882a593Smuzhiyun snd_emu10k1x_free(chip);
930*4882a593Smuzhiyun return -EBUSY;
931*4882a593Smuzhiyun }
932*4882a593Smuzhiyun chip->irq = pci->irq;
933*4882a593Smuzhiyun card->sync_irq = chip->irq;
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
936*4882a593Smuzhiyun 4 * 1024, &chip->dma_buffer) < 0) {
937*4882a593Smuzhiyun snd_emu10k1x_free(chip);
938*4882a593Smuzhiyun return -ENOMEM;
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun pci_set_master(pci);
942*4882a593Smuzhiyun /* read revision & serial */
943*4882a593Smuzhiyun chip->revision = pci->revision;
944*4882a593Smuzhiyun pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &chip->serial);
945*4882a593Smuzhiyun pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &chip->model);
946*4882a593Smuzhiyun dev_info(card->dev, "Model %04x Rev %08x Serial %08x\n", chip->model,
947*4882a593Smuzhiyun chip->revision, chip->serial);
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun outl(0, chip->port + INTE);
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun for(ch = 0; ch < 3; ch++) {
952*4882a593Smuzhiyun chip->voices[ch].emu = chip;
953*4882a593Smuzhiyun chip->voices[ch].number = ch;
954*4882a593Smuzhiyun }
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun /*
957*4882a593Smuzhiyun * Init to 0x02109204 :
958*4882a593Smuzhiyun * Clock accuracy = 0 (1000ppm)
959*4882a593Smuzhiyun * Sample Rate = 2 (48kHz)
960*4882a593Smuzhiyun * Audio Channel = 1 (Left of 2)
961*4882a593Smuzhiyun * Source Number = 0 (Unspecified)
962*4882a593Smuzhiyun * Generation Status = 1 (Original for Cat Code 12)
963*4882a593Smuzhiyun * Cat Code = 12 (Digital Signal Mixer)
964*4882a593Smuzhiyun * Mode = 0 (Mode 0)
965*4882a593Smuzhiyun * Emphasis = 0 (None)
966*4882a593Smuzhiyun * CP = 1 (Copyright unasserted)
967*4882a593Smuzhiyun * AN = 0 (Audio data)
968*4882a593Smuzhiyun * P = 0 (Consumer)
969*4882a593Smuzhiyun */
970*4882a593Smuzhiyun snd_emu10k1x_ptr_write(chip, SPCS0, 0,
971*4882a593Smuzhiyun chip->spdif_bits[0] =
972*4882a593Smuzhiyun SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
973*4882a593Smuzhiyun SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
974*4882a593Smuzhiyun SPCS_GENERATIONSTATUS | 0x00001200 |
975*4882a593Smuzhiyun 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
976*4882a593Smuzhiyun snd_emu10k1x_ptr_write(chip, SPCS1, 0,
977*4882a593Smuzhiyun chip->spdif_bits[1] =
978*4882a593Smuzhiyun SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
979*4882a593Smuzhiyun SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
980*4882a593Smuzhiyun SPCS_GENERATIONSTATUS | 0x00001200 |
981*4882a593Smuzhiyun 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
982*4882a593Smuzhiyun snd_emu10k1x_ptr_write(chip, SPCS2, 0,
983*4882a593Smuzhiyun chip->spdif_bits[2] =
984*4882a593Smuzhiyun SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
985*4882a593Smuzhiyun SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
986*4882a593Smuzhiyun SPCS_GENERATIONSTATUS | 0x00001200 |
987*4882a593Smuzhiyun 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun snd_emu10k1x_ptr_write(chip, SPDIF_SELECT, 0, 0x700); // disable SPDIF
990*4882a593Smuzhiyun snd_emu10k1x_ptr_write(chip, ROUTING, 0, 0x1003F); // routing
991*4882a593Smuzhiyun snd_emu10k1x_gpio_write(chip, 0x1080); // analog mode
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun outl(HCFG_LOCKSOUNDCACHE|HCFG_AUDIOENABLE, chip->port+HCFG);
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
996*4882a593Smuzhiyun chip, &ops)) < 0) {
997*4882a593Smuzhiyun snd_emu10k1x_free(chip);
998*4882a593Smuzhiyun return err;
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun *rchip = chip;
1001*4882a593Smuzhiyun return 0;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun
snd_emu10k1x_proc_reg_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1004*4882a593Smuzhiyun static void snd_emu10k1x_proc_reg_read(struct snd_info_entry *entry,
1005*4882a593Smuzhiyun struct snd_info_buffer *buffer)
1006*4882a593Smuzhiyun {
1007*4882a593Smuzhiyun struct emu10k1x *emu = entry->private_data;
1008*4882a593Smuzhiyun unsigned long value,value1,value2;
1009*4882a593Smuzhiyun unsigned long flags;
1010*4882a593Smuzhiyun int i;
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun snd_iprintf(buffer, "Registers:\n\n");
1013*4882a593Smuzhiyun for(i = 0; i < 0x20; i+=4) {
1014*4882a593Smuzhiyun spin_lock_irqsave(&emu->emu_lock, flags);
1015*4882a593Smuzhiyun value = inl(emu->port + i);
1016*4882a593Smuzhiyun spin_unlock_irqrestore(&emu->emu_lock, flags);
1017*4882a593Smuzhiyun snd_iprintf(buffer, "Register %02X: %08lX\n", i, value);
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun snd_iprintf(buffer, "\nRegisters\n\n");
1020*4882a593Smuzhiyun for(i = 0; i <= 0x48; i++) {
1021*4882a593Smuzhiyun value = snd_emu10k1x_ptr_read(emu, i, 0);
1022*4882a593Smuzhiyun if(i < 0x10 || (i >= 0x20 && i < 0x40)) {
1023*4882a593Smuzhiyun value1 = snd_emu10k1x_ptr_read(emu, i, 1);
1024*4882a593Smuzhiyun value2 = snd_emu10k1x_ptr_read(emu, i, 2);
1025*4882a593Smuzhiyun snd_iprintf(buffer, "%02X: %08lX %08lX %08lX\n", i, value, value1, value2);
1026*4882a593Smuzhiyun } else {
1027*4882a593Smuzhiyun snd_iprintf(buffer, "%02X: %08lX\n", i, value);
1028*4882a593Smuzhiyun }
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun
snd_emu10k1x_proc_reg_write(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1032*4882a593Smuzhiyun static void snd_emu10k1x_proc_reg_write(struct snd_info_entry *entry,
1033*4882a593Smuzhiyun struct snd_info_buffer *buffer)
1034*4882a593Smuzhiyun {
1035*4882a593Smuzhiyun struct emu10k1x *emu = entry->private_data;
1036*4882a593Smuzhiyun char line[64];
1037*4882a593Smuzhiyun unsigned int reg, channel_id , val;
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun while (!snd_info_get_line(buffer, line, sizeof(line))) {
1040*4882a593Smuzhiyun if (sscanf(line, "%x %x %x", ®, &channel_id, &val) != 3)
1041*4882a593Smuzhiyun continue;
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun if (reg < 0x49 && channel_id <= 2)
1044*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, reg, channel_id, val);
1045*4882a593Smuzhiyun }
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun
snd_emu10k1x_proc_init(struct emu10k1x * emu)1048*4882a593Smuzhiyun static int snd_emu10k1x_proc_init(struct emu10k1x *emu)
1049*4882a593Smuzhiyun {
1050*4882a593Smuzhiyun snd_card_rw_proc_new(emu->card, "emu10k1x_regs", emu,
1051*4882a593Smuzhiyun snd_emu10k1x_proc_reg_read,
1052*4882a593Smuzhiyun snd_emu10k1x_proc_reg_write);
1053*4882a593Smuzhiyun return 0;
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun #define snd_emu10k1x_shared_spdif_info snd_ctl_boolean_mono_info
1057*4882a593Smuzhiyun
snd_emu10k1x_shared_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1058*4882a593Smuzhiyun static int snd_emu10k1x_shared_spdif_get(struct snd_kcontrol *kcontrol,
1059*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1060*4882a593Smuzhiyun {
1061*4882a593Smuzhiyun struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (snd_emu10k1x_ptr_read(emu, SPDIF_SELECT, 0) == 0x700) ? 0 : 1;
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun return 0;
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun
snd_emu10k1x_shared_spdif_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1068*4882a593Smuzhiyun static int snd_emu10k1x_shared_spdif_put(struct snd_kcontrol *kcontrol,
1069*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1070*4882a593Smuzhiyun {
1071*4882a593Smuzhiyun struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
1072*4882a593Smuzhiyun unsigned int val;
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun val = ucontrol->value.integer.value[0] ;
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun if (val) {
1077*4882a593Smuzhiyun // enable spdif output
1078*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, SPDIF_SELECT, 0, 0x000);
1079*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, ROUTING, 0, 0x700);
1080*4882a593Smuzhiyun snd_emu10k1x_gpio_write(emu, 0x1000);
1081*4882a593Smuzhiyun } else {
1082*4882a593Smuzhiyun // disable spdif output
1083*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, SPDIF_SELECT, 0, 0x700);
1084*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, ROUTING, 0, 0x1003F);
1085*4882a593Smuzhiyun snd_emu10k1x_gpio_write(emu, 0x1080);
1086*4882a593Smuzhiyun }
1087*4882a593Smuzhiyun return 0;
1088*4882a593Smuzhiyun }
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_emu10k1x_shared_spdif =
1091*4882a593Smuzhiyun {
1092*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1093*4882a593Smuzhiyun .name = "Analog/Digital Output Jack",
1094*4882a593Smuzhiyun .info = snd_emu10k1x_shared_spdif_info,
1095*4882a593Smuzhiyun .get = snd_emu10k1x_shared_spdif_get,
1096*4882a593Smuzhiyun .put = snd_emu10k1x_shared_spdif_put
1097*4882a593Smuzhiyun };
1098*4882a593Smuzhiyun
snd_emu10k1x_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1099*4882a593Smuzhiyun static int snd_emu10k1x_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1100*4882a593Smuzhiyun {
1101*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1102*4882a593Smuzhiyun uinfo->count = 1;
1103*4882a593Smuzhiyun return 0;
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun
snd_emu10k1x_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1106*4882a593Smuzhiyun static int snd_emu10k1x_spdif_get(struct snd_kcontrol *kcontrol,
1107*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
1110*4882a593Smuzhiyun unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = (emu->spdif_bits[idx] >> 0) & 0xff;
1113*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = (emu->spdif_bits[idx] >> 8) & 0xff;
1114*4882a593Smuzhiyun ucontrol->value.iec958.status[2] = (emu->spdif_bits[idx] >> 16) & 0xff;
1115*4882a593Smuzhiyun ucontrol->value.iec958.status[3] = (emu->spdif_bits[idx] >> 24) & 0xff;
1116*4882a593Smuzhiyun return 0;
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun
snd_emu10k1x_spdif_get_mask(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1119*4882a593Smuzhiyun static int snd_emu10k1x_spdif_get_mask(struct snd_kcontrol *kcontrol,
1120*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1121*4882a593Smuzhiyun {
1122*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = 0xff;
1123*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = 0xff;
1124*4882a593Smuzhiyun ucontrol->value.iec958.status[2] = 0xff;
1125*4882a593Smuzhiyun ucontrol->value.iec958.status[3] = 0xff;
1126*4882a593Smuzhiyun return 0;
1127*4882a593Smuzhiyun }
1128*4882a593Smuzhiyun
snd_emu10k1x_spdif_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1129*4882a593Smuzhiyun static int snd_emu10k1x_spdif_put(struct snd_kcontrol *kcontrol,
1130*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1131*4882a593Smuzhiyun {
1132*4882a593Smuzhiyun struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
1133*4882a593Smuzhiyun unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1134*4882a593Smuzhiyun int change;
1135*4882a593Smuzhiyun unsigned int val;
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun val = (ucontrol->value.iec958.status[0] << 0) |
1138*4882a593Smuzhiyun (ucontrol->value.iec958.status[1] << 8) |
1139*4882a593Smuzhiyun (ucontrol->value.iec958.status[2] << 16) |
1140*4882a593Smuzhiyun (ucontrol->value.iec958.status[3] << 24);
1141*4882a593Smuzhiyun change = val != emu->spdif_bits[idx];
1142*4882a593Smuzhiyun if (change) {
1143*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, SPCS0 + idx, 0, val);
1144*4882a593Smuzhiyun emu->spdif_bits[idx] = val;
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun return change;
1147*4882a593Smuzhiyun }
1148*4882a593Smuzhiyun
1149*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_emu10k1x_spdif_mask_control =
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
1152*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1153*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1154*4882a593Smuzhiyun .count = 3,
1155*4882a593Smuzhiyun .info = snd_emu10k1x_spdif_info,
1156*4882a593Smuzhiyun .get = snd_emu10k1x_spdif_get_mask
1157*4882a593Smuzhiyun };
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_emu10k1x_spdif_control =
1160*4882a593Smuzhiyun {
1161*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1162*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1163*4882a593Smuzhiyun .count = 3,
1164*4882a593Smuzhiyun .info = snd_emu10k1x_spdif_info,
1165*4882a593Smuzhiyun .get = snd_emu10k1x_spdif_get,
1166*4882a593Smuzhiyun .put = snd_emu10k1x_spdif_put
1167*4882a593Smuzhiyun };
1168*4882a593Smuzhiyun
snd_emu10k1x_mixer(struct emu10k1x * emu)1169*4882a593Smuzhiyun static int snd_emu10k1x_mixer(struct emu10k1x *emu)
1170*4882a593Smuzhiyun {
1171*4882a593Smuzhiyun int err;
1172*4882a593Smuzhiyun struct snd_kcontrol *kctl;
1173*4882a593Smuzhiyun struct snd_card *card = emu->card;
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun if ((kctl = snd_ctl_new1(&snd_emu10k1x_spdif_mask_control, emu)) == NULL)
1176*4882a593Smuzhiyun return -ENOMEM;
1177*4882a593Smuzhiyun if ((err = snd_ctl_add(card, kctl)))
1178*4882a593Smuzhiyun return err;
1179*4882a593Smuzhiyun if ((kctl = snd_ctl_new1(&snd_emu10k1x_shared_spdif, emu)) == NULL)
1180*4882a593Smuzhiyun return -ENOMEM;
1181*4882a593Smuzhiyun if ((err = snd_ctl_add(card, kctl)))
1182*4882a593Smuzhiyun return err;
1183*4882a593Smuzhiyun if ((kctl = snd_ctl_new1(&snd_emu10k1x_spdif_control, emu)) == NULL)
1184*4882a593Smuzhiyun return -ENOMEM;
1185*4882a593Smuzhiyun if ((err = snd_ctl_add(card, kctl)))
1186*4882a593Smuzhiyun return err;
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun return 0;
1189*4882a593Smuzhiyun }
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun #define EMU10K1X_MIDI_MODE_INPUT (1<<0)
1192*4882a593Smuzhiyun #define EMU10K1X_MIDI_MODE_OUTPUT (1<<1)
1193*4882a593Smuzhiyun
mpu401_read(struct emu10k1x * emu,struct emu10k1x_midi * mpu,int idx)1194*4882a593Smuzhiyun static inline unsigned char mpu401_read(struct emu10k1x *emu, struct emu10k1x_midi *mpu, int idx)
1195*4882a593Smuzhiyun {
1196*4882a593Smuzhiyun return (unsigned char)snd_emu10k1x_ptr_read(emu, mpu->port + idx, 0);
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun
mpu401_write(struct emu10k1x * emu,struct emu10k1x_midi * mpu,int data,int idx)1199*4882a593Smuzhiyun static inline void mpu401_write(struct emu10k1x *emu, struct emu10k1x_midi *mpu, int data, int idx)
1200*4882a593Smuzhiyun {
1201*4882a593Smuzhiyun snd_emu10k1x_ptr_write(emu, mpu->port + idx, 0, data);
1202*4882a593Smuzhiyun }
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun #define mpu401_write_data(emu, mpu, data) mpu401_write(emu, mpu, data, 0)
1205*4882a593Smuzhiyun #define mpu401_write_cmd(emu, mpu, data) mpu401_write(emu, mpu, data, 1)
1206*4882a593Smuzhiyun #define mpu401_read_data(emu, mpu) mpu401_read(emu, mpu, 0)
1207*4882a593Smuzhiyun #define mpu401_read_stat(emu, mpu) mpu401_read(emu, mpu, 1)
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun #define mpu401_input_avail(emu,mpu) (!(mpu401_read_stat(emu,mpu) & 0x80))
1210*4882a593Smuzhiyun #define mpu401_output_ready(emu,mpu) (!(mpu401_read_stat(emu,mpu) & 0x40))
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun #define MPU401_RESET 0xff
1213*4882a593Smuzhiyun #define MPU401_ENTER_UART 0x3f
1214*4882a593Smuzhiyun #define MPU401_ACK 0xfe
1215*4882a593Smuzhiyun
mpu401_clear_rx(struct emu10k1x * emu,struct emu10k1x_midi * mpu)1216*4882a593Smuzhiyun static void mpu401_clear_rx(struct emu10k1x *emu, struct emu10k1x_midi *mpu)
1217*4882a593Smuzhiyun {
1218*4882a593Smuzhiyun int timeout = 100000;
1219*4882a593Smuzhiyun for (; timeout > 0 && mpu401_input_avail(emu, mpu); timeout--)
1220*4882a593Smuzhiyun mpu401_read_data(emu, mpu);
1221*4882a593Smuzhiyun #ifdef CONFIG_SND_DEBUG
1222*4882a593Smuzhiyun if (timeout <= 0)
1223*4882a593Smuzhiyun dev_err(emu->card->dev,
1224*4882a593Smuzhiyun "cmd: clear rx timeout (status = 0x%x)\n",
1225*4882a593Smuzhiyun mpu401_read_stat(emu, mpu));
1226*4882a593Smuzhiyun #endif
1227*4882a593Smuzhiyun }
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun /*
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun */
1232*4882a593Smuzhiyun
do_emu10k1x_midi_interrupt(struct emu10k1x * emu,struct emu10k1x_midi * midi,unsigned int status)1233*4882a593Smuzhiyun static void do_emu10k1x_midi_interrupt(struct emu10k1x *emu,
1234*4882a593Smuzhiyun struct emu10k1x_midi *midi, unsigned int status)
1235*4882a593Smuzhiyun {
1236*4882a593Smuzhiyun unsigned char byte;
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun if (midi->rmidi == NULL) {
1239*4882a593Smuzhiyun snd_emu10k1x_intr_disable(emu, midi->tx_enable | midi->rx_enable);
1240*4882a593Smuzhiyun return;
1241*4882a593Smuzhiyun }
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun spin_lock(&midi->input_lock);
1244*4882a593Smuzhiyun if ((status & midi->ipr_rx) && mpu401_input_avail(emu, midi)) {
1245*4882a593Smuzhiyun if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
1246*4882a593Smuzhiyun mpu401_clear_rx(emu, midi);
1247*4882a593Smuzhiyun } else {
1248*4882a593Smuzhiyun byte = mpu401_read_data(emu, midi);
1249*4882a593Smuzhiyun if (midi->substream_input)
1250*4882a593Smuzhiyun snd_rawmidi_receive(midi->substream_input, &byte, 1);
1251*4882a593Smuzhiyun }
1252*4882a593Smuzhiyun }
1253*4882a593Smuzhiyun spin_unlock(&midi->input_lock);
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun spin_lock(&midi->output_lock);
1256*4882a593Smuzhiyun if ((status & midi->ipr_tx) && mpu401_output_ready(emu, midi)) {
1257*4882a593Smuzhiyun if (midi->substream_output &&
1258*4882a593Smuzhiyun snd_rawmidi_transmit(midi->substream_output, &byte, 1) == 1) {
1259*4882a593Smuzhiyun mpu401_write_data(emu, midi, byte);
1260*4882a593Smuzhiyun } else {
1261*4882a593Smuzhiyun snd_emu10k1x_intr_disable(emu, midi->tx_enable);
1262*4882a593Smuzhiyun }
1263*4882a593Smuzhiyun }
1264*4882a593Smuzhiyun spin_unlock(&midi->output_lock);
1265*4882a593Smuzhiyun }
1266*4882a593Smuzhiyun
snd_emu10k1x_midi_interrupt(struct emu10k1x * emu,unsigned int status)1267*4882a593Smuzhiyun static void snd_emu10k1x_midi_interrupt(struct emu10k1x *emu, unsigned int status)
1268*4882a593Smuzhiyun {
1269*4882a593Smuzhiyun do_emu10k1x_midi_interrupt(emu, &emu->midi, status);
1270*4882a593Smuzhiyun }
1271*4882a593Smuzhiyun
snd_emu10k1x_midi_cmd(struct emu10k1x * emu,struct emu10k1x_midi * midi,unsigned char cmd,int ack)1272*4882a593Smuzhiyun static int snd_emu10k1x_midi_cmd(struct emu10k1x * emu,
1273*4882a593Smuzhiyun struct emu10k1x_midi *midi, unsigned char cmd, int ack)
1274*4882a593Smuzhiyun {
1275*4882a593Smuzhiyun unsigned long flags;
1276*4882a593Smuzhiyun int timeout, ok;
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun spin_lock_irqsave(&midi->input_lock, flags);
1279*4882a593Smuzhiyun mpu401_write_data(emu, midi, 0x00);
1280*4882a593Smuzhiyun /* mpu401_clear_rx(emu, midi); */
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun mpu401_write_cmd(emu, midi, cmd);
1283*4882a593Smuzhiyun if (ack) {
1284*4882a593Smuzhiyun ok = 0;
1285*4882a593Smuzhiyun timeout = 10000;
1286*4882a593Smuzhiyun while (!ok && timeout-- > 0) {
1287*4882a593Smuzhiyun if (mpu401_input_avail(emu, midi)) {
1288*4882a593Smuzhiyun if (mpu401_read_data(emu, midi) == MPU401_ACK)
1289*4882a593Smuzhiyun ok = 1;
1290*4882a593Smuzhiyun }
1291*4882a593Smuzhiyun }
1292*4882a593Smuzhiyun if (!ok && mpu401_read_data(emu, midi) == MPU401_ACK)
1293*4882a593Smuzhiyun ok = 1;
1294*4882a593Smuzhiyun } else {
1295*4882a593Smuzhiyun ok = 1;
1296*4882a593Smuzhiyun }
1297*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->input_lock, flags);
1298*4882a593Smuzhiyun if (!ok) {
1299*4882a593Smuzhiyun dev_err(emu->card->dev,
1300*4882a593Smuzhiyun "midi_cmd: 0x%x failed at 0x%lx (status = 0x%x, data = 0x%x)!!!\n",
1301*4882a593Smuzhiyun cmd, emu->port,
1302*4882a593Smuzhiyun mpu401_read_stat(emu, midi),
1303*4882a593Smuzhiyun mpu401_read_data(emu, midi));
1304*4882a593Smuzhiyun return 1;
1305*4882a593Smuzhiyun }
1306*4882a593Smuzhiyun return 0;
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun
snd_emu10k1x_midi_input_open(struct snd_rawmidi_substream * substream)1309*4882a593Smuzhiyun static int snd_emu10k1x_midi_input_open(struct snd_rawmidi_substream *substream)
1310*4882a593Smuzhiyun {
1311*4882a593Smuzhiyun struct emu10k1x *emu;
1312*4882a593Smuzhiyun struct emu10k1x_midi *midi = substream->rmidi->private_data;
1313*4882a593Smuzhiyun unsigned long flags;
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun emu = midi->emu;
1316*4882a593Smuzhiyun if (snd_BUG_ON(!emu))
1317*4882a593Smuzhiyun return -ENXIO;
1318*4882a593Smuzhiyun spin_lock_irqsave(&midi->open_lock, flags);
1319*4882a593Smuzhiyun midi->midi_mode |= EMU10K1X_MIDI_MODE_INPUT;
1320*4882a593Smuzhiyun midi->substream_input = substream;
1321*4882a593Smuzhiyun if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT)) {
1322*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->open_lock, flags);
1323*4882a593Smuzhiyun if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 1))
1324*4882a593Smuzhiyun goto error_out;
1325*4882a593Smuzhiyun if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_ENTER_UART, 1))
1326*4882a593Smuzhiyun goto error_out;
1327*4882a593Smuzhiyun } else {
1328*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->open_lock, flags);
1329*4882a593Smuzhiyun }
1330*4882a593Smuzhiyun return 0;
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun error_out:
1333*4882a593Smuzhiyun return -EIO;
1334*4882a593Smuzhiyun }
1335*4882a593Smuzhiyun
snd_emu10k1x_midi_output_open(struct snd_rawmidi_substream * substream)1336*4882a593Smuzhiyun static int snd_emu10k1x_midi_output_open(struct snd_rawmidi_substream *substream)
1337*4882a593Smuzhiyun {
1338*4882a593Smuzhiyun struct emu10k1x *emu;
1339*4882a593Smuzhiyun struct emu10k1x_midi *midi = substream->rmidi->private_data;
1340*4882a593Smuzhiyun unsigned long flags;
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun emu = midi->emu;
1343*4882a593Smuzhiyun if (snd_BUG_ON(!emu))
1344*4882a593Smuzhiyun return -ENXIO;
1345*4882a593Smuzhiyun spin_lock_irqsave(&midi->open_lock, flags);
1346*4882a593Smuzhiyun midi->midi_mode |= EMU10K1X_MIDI_MODE_OUTPUT;
1347*4882a593Smuzhiyun midi->substream_output = substream;
1348*4882a593Smuzhiyun if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
1349*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->open_lock, flags);
1350*4882a593Smuzhiyun if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 1))
1351*4882a593Smuzhiyun goto error_out;
1352*4882a593Smuzhiyun if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_ENTER_UART, 1))
1353*4882a593Smuzhiyun goto error_out;
1354*4882a593Smuzhiyun } else {
1355*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->open_lock, flags);
1356*4882a593Smuzhiyun }
1357*4882a593Smuzhiyun return 0;
1358*4882a593Smuzhiyun
1359*4882a593Smuzhiyun error_out:
1360*4882a593Smuzhiyun return -EIO;
1361*4882a593Smuzhiyun }
1362*4882a593Smuzhiyun
snd_emu10k1x_midi_input_close(struct snd_rawmidi_substream * substream)1363*4882a593Smuzhiyun static int snd_emu10k1x_midi_input_close(struct snd_rawmidi_substream *substream)
1364*4882a593Smuzhiyun {
1365*4882a593Smuzhiyun struct emu10k1x *emu;
1366*4882a593Smuzhiyun struct emu10k1x_midi *midi = substream->rmidi->private_data;
1367*4882a593Smuzhiyun unsigned long flags;
1368*4882a593Smuzhiyun int err = 0;
1369*4882a593Smuzhiyun
1370*4882a593Smuzhiyun emu = midi->emu;
1371*4882a593Smuzhiyun if (snd_BUG_ON(!emu))
1372*4882a593Smuzhiyun return -ENXIO;
1373*4882a593Smuzhiyun spin_lock_irqsave(&midi->open_lock, flags);
1374*4882a593Smuzhiyun snd_emu10k1x_intr_disable(emu, midi->rx_enable);
1375*4882a593Smuzhiyun midi->midi_mode &= ~EMU10K1X_MIDI_MODE_INPUT;
1376*4882a593Smuzhiyun midi->substream_input = NULL;
1377*4882a593Smuzhiyun if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT)) {
1378*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->open_lock, flags);
1379*4882a593Smuzhiyun err = snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 0);
1380*4882a593Smuzhiyun } else {
1381*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->open_lock, flags);
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun return err;
1384*4882a593Smuzhiyun }
1385*4882a593Smuzhiyun
snd_emu10k1x_midi_output_close(struct snd_rawmidi_substream * substream)1386*4882a593Smuzhiyun static int snd_emu10k1x_midi_output_close(struct snd_rawmidi_substream *substream)
1387*4882a593Smuzhiyun {
1388*4882a593Smuzhiyun struct emu10k1x *emu;
1389*4882a593Smuzhiyun struct emu10k1x_midi *midi = substream->rmidi->private_data;
1390*4882a593Smuzhiyun unsigned long flags;
1391*4882a593Smuzhiyun int err = 0;
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun emu = midi->emu;
1394*4882a593Smuzhiyun if (snd_BUG_ON(!emu))
1395*4882a593Smuzhiyun return -ENXIO;
1396*4882a593Smuzhiyun spin_lock_irqsave(&midi->open_lock, flags);
1397*4882a593Smuzhiyun snd_emu10k1x_intr_disable(emu, midi->tx_enable);
1398*4882a593Smuzhiyun midi->midi_mode &= ~EMU10K1X_MIDI_MODE_OUTPUT;
1399*4882a593Smuzhiyun midi->substream_output = NULL;
1400*4882a593Smuzhiyun if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
1401*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->open_lock, flags);
1402*4882a593Smuzhiyun err = snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 0);
1403*4882a593Smuzhiyun } else {
1404*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->open_lock, flags);
1405*4882a593Smuzhiyun }
1406*4882a593Smuzhiyun return err;
1407*4882a593Smuzhiyun }
1408*4882a593Smuzhiyun
snd_emu10k1x_midi_input_trigger(struct snd_rawmidi_substream * substream,int up)1409*4882a593Smuzhiyun static void snd_emu10k1x_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1410*4882a593Smuzhiyun {
1411*4882a593Smuzhiyun struct emu10k1x *emu;
1412*4882a593Smuzhiyun struct emu10k1x_midi *midi = substream->rmidi->private_data;
1413*4882a593Smuzhiyun emu = midi->emu;
1414*4882a593Smuzhiyun if (snd_BUG_ON(!emu))
1415*4882a593Smuzhiyun return;
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun if (up)
1418*4882a593Smuzhiyun snd_emu10k1x_intr_enable(emu, midi->rx_enable);
1419*4882a593Smuzhiyun else
1420*4882a593Smuzhiyun snd_emu10k1x_intr_disable(emu, midi->rx_enable);
1421*4882a593Smuzhiyun }
1422*4882a593Smuzhiyun
snd_emu10k1x_midi_output_trigger(struct snd_rawmidi_substream * substream,int up)1423*4882a593Smuzhiyun static void snd_emu10k1x_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1424*4882a593Smuzhiyun {
1425*4882a593Smuzhiyun struct emu10k1x *emu;
1426*4882a593Smuzhiyun struct emu10k1x_midi *midi = substream->rmidi->private_data;
1427*4882a593Smuzhiyun unsigned long flags;
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun emu = midi->emu;
1430*4882a593Smuzhiyun if (snd_BUG_ON(!emu))
1431*4882a593Smuzhiyun return;
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun if (up) {
1434*4882a593Smuzhiyun int max = 4;
1435*4882a593Smuzhiyun unsigned char byte;
1436*4882a593Smuzhiyun
1437*4882a593Smuzhiyun /* try to send some amount of bytes here before interrupts */
1438*4882a593Smuzhiyun spin_lock_irqsave(&midi->output_lock, flags);
1439*4882a593Smuzhiyun while (max > 0) {
1440*4882a593Smuzhiyun if (mpu401_output_ready(emu, midi)) {
1441*4882a593Smuzhiyun if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT) ||
1442*4882a593Smuzhiyun snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1443*4882a593Smuzhiyun /* no more data */
1444*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->output_lock, flags);
1445*4882a593Smuzhiyun return;
1446*4882a593Smuzhiyun }
1447*4882a593Smuzhiyun mpu401_write_data(emu, midi, byte);
1448*4882a593Smuzhiyun max--;
1449*4882a593Smuzhiyun } else {
1450*4882a593Smuzhiyun break;
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun }
1453*4882a593Smuzhiyun spin_unlock_irqrestore(&midi->output_lock, flags);
1454*4882a593Smuzhiyun snd_emu10k1x_intr_enable(emu, midi->tx_enable);
1455*4882a593Smuzhiyun } else {
1456*4882a593Smuzhiyun snd_emu10k1x_intr_disable(emu, midi->tx_enable);
1457*4882a593Smuzhiyun }
1458*4882a593Smuzhiyun }
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun /*
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun */
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun static const struct snd_rawmidi_ops snd_emu10k1x_midi_output =
1465*4882a593Smuzhiyun {
1466*4882a593Smuzhiyun .open = snd_emu10k1x_midi_output_open,
1467*4882a593Smuzhiyun .close = snd_emu10k1x_midi_output_close,
1468*4882a593Smuzhiyun .trigger = snd_emu10k1x_midi_output_trigger,
1469*4882a593Smuzhiyun };
1470*4882a593Smuzhiyun
1471*4882a593Smuzhiyun static const struct snd_rawmidi_ops snd_emu10k1x_midi_input =
1472*4882a593Smuzhiyun {
1473*4882a593Smuzhiyun .open = snd_emu10k1x_midi_input_open,
1474*4882a593Smuzhiyun .close = snd_emu10k1x_midi_input_close,
1475*4882a593Smuzhiyun .trigger = snd_emu10k1x_midi_input_trigger,
1476*4882a593Smuzhiyun };
1477*4882a593Smuzhiyun
snd_emu10k1x_midi_free(struct snd_rawmidi * rmidi)1478*4882a593Smuzhiyun static void snd_emu10k1x_midi_free(struct snd_rawmidi *rmidi)
1479*4882a593Smuzhiyun {
1480*4882a593Smuzhiyun struct emu10k1x_midi *midi = rmidi->private_data;
1481*4882a593Smuzhiyun midi->interrupt = NULL;
1482*4882a593Smuzhiyun midi->rmidi = NULL;
1483*4882a593Smuzhiyun }
1484*4882a593Smuzhiyun
emu10k1x_midi_init(struct emu10k1x * emu,struct emu10k1x_midi * midi,int device,char * name)1485*4882a593Smuzhiyun static int emu10k1x_midi_init(struct emu10k1x *emu,
1486*4882a593Smuzhiyun struct emu10k1x_midi *midi, int device,
1487*4882a593Smuzhiyun char *name)
1488*4882a593Smuzhiyun {
1489*4882a593Smuzhiyun struct snd_rawmidi *rmidi;
1490*4882a593Smuzhiyun int err;
1491*4882a593Smuzhiyun
1492*4882a593Smuzhiyun if ((err = snd_rawmidi_new(emu->card, name, device, 1, 1, &rmidi)) < 0)
1493*4882a593Smuzhiyun return err;
1494*4882a593Smuzhiyun midi->emu = emu;
1495*4882a593Smuzhiyun spin_lock_init(&midi->open_lock);
1496*4882a593Smuzhiyun spin_lock_init(&midi->input_lock);
1497*4882a593Smuzhiyun spin_lock_init(&midi->output_lock);
1498*4882a593Smuzhiyun strcpy(rmidi->name, name);
1499*4882a593Smuzhiyun snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_emu10k1x_midi_output);
1500*4882a593Smuzhiyun snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_emu10k1x_midi_input);
1501*4882a593Smuzhiyun rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1502*4882a593Smuzhiyun SNDRV_RAWMIDI_INFO_INPUT |
1503*4882a593Smuzhiyun SNDRV_RAWMIDI_INFO_DUPLEX;
1504*4882a593Smuzhiyun rmidi->private_data = midi;
1505*4882a593Smuzhiyun rmidi->private_free = snd_emu10k1x_midi_free;
1506*4882a593Smuzhiyun midi->rmidi = rmidi;
1507*4882a593Smuzhiyun return 0;
1508*4882a593Smuzhiyun }
1509*4882a593Smuzhiyun
snd_emu10k1x_midi(struct emu10k1x * emu)1510*4882a593Smuzhiyun static int snd_emu10k1x_midi(struct emu10k1x *emu)
1511*4882a593Smuzhiyun {
1512*4882a593Smuzhiyun struct emu10k1x_midi *midi = &emu->midi;
1513*4882a593Smuzhiyun int err;
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun if ((err = emu10k1x_midi_init(emu, midi, 0, "EMU10K1X MPU-401 (UART)")) < 0)
1516*4882a593Smuzhiyun return err;
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun midi->tx_enable = INTE_MIDITXENABLE;
1519*4882a593Smuzhiyun midi->rx_enable = INTE_MIDIRXENABLE;
1520*4882a593Smuzhiyun midi->port = MUDATA;
1521*4882a593Smuzhiyun midi->ipr_tx = IPR_MIDITRANSBUFEMPTY;
1522*4882a593Smuzhiyun midi->ipr_rx = IPR_MIDIRECVBUFEMPTY;
1523*4882a593Smuzhiyun midi->interrupt = snd_emu10k1x_midi_interrupt;
1524*4882a593Smuzhiyun return 0;
1525*4882a593Smuzhiyun }
1526*4882a593Smuzhiyun
snd_emu10k1x_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1527*4882a593Smuzhiyun static int snd_emu10k1x_probe(struct pci_dev *pci,
1528*4882a593Smuzhiyun const struct pci_device_id *pci_id)
1529*4882a593Smuzhiyun {
1530*4882a593Smuzhiyun static int dev;
1531*4882a593Smuzhiyun struct snd_card *card;
1532*4882a593Smuzhiyun struct emu10k1x *chip;
1533*4882a593Smuzhiyun int err;
1534*4882a593Smuzhiyun
1535*4882a593Smuzhiyun if (dev >= SNDRV_CARDS)
1536*4882a593Smuzhiyun return -ENODEV;
1537*4882a593Smuzhiyun if (!enable[dev]) {
1538*4882a593Smuzhiyun dev++;
1539*4882a593Smuzhiyun return -ENOENT;
1540*4882a593Smuzhiyun }
1541*4882a593Smuzhiyun
1542*4882a593Smuzhiyun err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1543*4882a593Smuzhiyun 0, &card);
1544*4882a593Smuzhiyun if (err < 0)
1545*4882a593Smuzhiyun return err;
1546*4882a593Smuzhiyun
1547*4882a593Smuzhiyun if ((err = snd_emu10k1x_create(card, pci, &chip)) < 0) {
1548*4882a593Smuzhiyun snd_card_free(card);
1549*4882a593Smuzhiyun return err;
1550*4882a593Smuzhiyun }
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun if ((err = snd_emu10k1x_pcm(chip, 0)) < 0) {
1553*4882a593Smuzhiyun snd_card_free(card);
1554*4882a593Smuzhiyun return err;
1555*4882a593Smuzhiyun }
1556*4882a593Smuzhiyun if ((err = snd_emu10k1x_pcm(chip, 1)) < 0) {
1557*4882a593Smuzhiyun snd_card_free(card);
1558*4882a593Smuzhiyun return err;
1559*4882a593Smuzhiyun }
1560*4882a593Smuzhiyun if ((err = snd_emu10k1x_pcm(chip, 2)) < 0) {
1561*4882a593Smuzhiyun snd_card_free(card);
1562*4882a593Smuzhiyun return err;
1563*4882a593Smuzhiyun }
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun if ((err = snd_emu10k1x_ac97(chip)) < 0) {
1566*4882a593Smuzhiyun snd_card_free(card);
1567*4882a593Smuzhiyun return err;
1568*4882a593Smuzhiyun }
1569*4882a593Smuzhiyun
1570*4882a593Smuzhiyun if ((err = snd_emu10k1x_mixer(chip)) < 0) {
1571*4882a593Smuzhiyun snd_card_free(card);
1572*4882a593Smuzhiyun return err;
1573*4882a593Smuzhiyun }
1574*4882a593Smuzhiyun
1575*4882a593Smuzhiyun if ((err = snd_emu10k1x_midi(chip)) < 0) {
1576*4882a593Smuzhiyun snd_card_free(card);
1577*4882a593Smuzhiyun return err;
1578*4882a593Smuzhiyun }
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun snd_emu10k1x_proc_init(chip);
1581*4882a593Smuzhiyun
1582*4882a593Smuzhiyun strcpy(card->driver, "EMU10K1X");
1583*4882a593Smuzhiyun strcpy(card->shortname, "Dell Sound Blaster Live!");
1584*4882a593Smuzhiyun sprintf(card->longname, "%s at 0x%lx irq %i",
1585*4882a593Smuzhiyun card->shortname, chip->port, chip->irq);
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun if ((err = snd_card_register(card)) < 0) {
1588*4882a593Smuzhiyun snd_card_free(card);
1589*4882a593Smuzhiyun return err;
1590*4882a593Smuzhiyun }
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun pci_set_drvdata(pci, card);
1593*4882a593Smuzhiyun dev++;
1594*4882a593Smuzhiyun return 0;
1595*4882a593Smuzhiyun }
1596*4882a593Smuzhiyun
snd_emu10k1x_remove(struct pci_dev * pci)1597*4882a593Smuzhiyun static void snd_emu10k1x_remove(struct pci_dev *pci)
1598*4882a593Smuzhiyun {
1599*4882a593Smuzhiyun snd_card_free(pci_get_drvdata(pci));
1600*4882a593Smuzhiyun }
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun // PCI IDs
1603*4882a593Smuzhiyun static const struct pci_device_id snd_emu10k1x_ids[] = {
1604*4882a593Smuzhiyun { PCI_VDEVICE(CREATIVE, 0x0006), 0 }, /* Dell OEM version (EMU10K1) */
1605*4882a593Smuzhiyun { 0, }
1606*4882a593Smuzhiyun };
1607*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_emu10k1x_ids);
1608*4882a593Smuzhiyun
1609*4882a593Smuzhiyun // pci_driver definition
1610*4882a593Smuzhiyun static struct pci_driver emu10k1x_driver = {
1611*4882a593Smuzhiyun .name = KBUILD_MODNAME,
1612*4882a593Smuzhiyun .id_table = snd_emu10k1x_ids,
1613*4882a593Smuzhiyun .probe = snd_emu10k1x_probe,
1614*4882a593Smuzhiyun .remove = snd_emu10k1x_remove,
1615*4882a593Smuzhiyun };
1616*4882a593Smuzhiyun
1617*4882a593Smuzhiyun module_pci_driver(emu10k1x_driver);
1618