1*4882a593Smuzhiyun /***************************************************************************
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun Copyright Echo Digital Audio Corporation (c) 1998 - 2004
4*4882a593Smuzhiyun All rights reserved
5*4882a593Smuzhiyun www.echoaudio.com
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun This file is part of Echo Digital Audio's generic driver library.
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun Echo Digital Audio's generic driver library is free software;
10*4882a593Smuzhiyun you can redistribute it and/or modify it under the terms of
11*4882a593Smuzhiyun the GNU General Public License as published by the Free Software
12*4882a593Smuzhiyun Foundation.
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun This program is distributed in the hope that it will be useful,
15*4882a593Smuzhiyun but WITHOUT ANY WARRANTY; without even the implied warranty of
16*4882a593Smuzhiyun MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17*4882a593Smuzhiyun GNU General Public License for more details.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun You should have received a copy of the GNU General Public License
20*4882a593Smuzhiyun along with this program; if not, write to the Free Software
21*4882a593Smuzhiyun Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22*4882a593Smuzhiyun MA 02111-1307, USA.
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun *************************************************************************
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun Translation from C++ and adaptation for use in ALSA-Driver
27*4882a593Smuzhiyun were made by Giuliano Pochini <pochini@shiny.it>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun ****************************************************************************/
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun
init_hw(struct echoaudio * chip,u16 device_id,u16 subdevice_id)32*4882a593Smuzhiyun static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun int err;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (snd_BUG_ON((subdevice_id & 0xfff0) != DARLA24))
37*4882a593Smuzhiyun return -ENODEV;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if ((err = init_dsp_comm_page(chip))) {
40*4882a593Smuzhiyun dev_err(chip->card->dev,
41*4882a593Smuzhiyun "init_hw: could not initialize DSP comm page\n");
42*4882a593Smuzhiyun return err;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun chip->device_id = device_id;
46*4882a593Smuzhiyun chip->subdevice_id = subdevice_id;
47*4882a593Smuzhiyun chip->bad_board = true;
48*4882a593Smuzhiyun chip->dsp_code_to_load = FW_DARLA24_DSP;
49*4882a593Smuzhiyun /* Since this card has no ASIC, mark it as loaded so everything
50*4882a593Smuzhiyun works OK */
51*4882a593Smuzhiyun chip->asic_loaded = true;
52*4882a593Smuzhiyun chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL |
53*4882a593Smuzhiyun ECHO_CLOCK_BIT_ESYNC;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if ((err = load_firmware(chip)) < 0)
56*4882a593Smuzhiyun return err;
57*4882a593Smuzhiyun chip->bad_board = false;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return err;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun
set_mixer_defaults(struct echoaudio * chip)64*4882a593Smuzhiyun static int set_mixer_defaults(struct echoaudio *chip)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun return init_line_levels(chip);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun
detect_input_clocks(const struct echoaudio * chip)71*4882a593Smuzhiyun static u32 detect_input_clocks(const struct echoaudio *chip)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun u32 clocks_from_dsp, clock_bits;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Map the DSP clock detect bits to the generic driver clock
76*4882a593Smuzhiyun detect bits */
77*4882a593Smuzhiyun clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun clock_bits = ECHO_CLOCK_BIT_INTERNAL;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_ESYNC)
82*4882a593Smuzhiyun clock_bits |= ECHO_CLOCK_BIT_ESYNC;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return clock_bits;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* The Darla24 has no ASIC. Just do nothing */
load_asic(struct echoaudio * chip)90*4882a593Smuzhiyun static int load_asic(struct echoaudio *chip)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun
set_sample_rate(struct echoaudio * chip,u32 rate)97*4882a593Smuzhiyun static int set_sample_rate(struct echoaudio *chip, u32 rate)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun u8 clock;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun switch (rate) {
102*4882a593Smuzhiyun case 96000:
103*4882a593Smuzhiyun clock = GD24_96000;
104*4882a593Smuzhiyun break;
105*4882a593Smuzhiyun case 88200:
106*4882a593Smuzhiyun clock = GD24_88200;
107*4882a593Smuzhiyun break;
108*4882a593Smuzhiyun case 48000:
109*4882a593Smuzhiyun clock = GD24_48000;
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun case 44100:
112*4882a593Smuzhiyun clock = GD24_44100;
113*4882a593Smuzhiyun break;
114*4882a593Smuzhiyun case 32000:
115*4882a593Smuzhiyun clock = GD24_32000;
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun case 22050:
118*4882a593Smuzhiyun clock = GD24_22050;
119*4882a593Smuzhiyun break;
120*4882a593Smuzhiyun case 16000:
121*4882a593Smuzhiyun clock = GD24_16000;
122*4882a593Smuzhiyun break;
123*4882a593Smuzhiyun case 11025:
124*4882a593Smuzhiyun clock = GD24_11025;
125*4882a593Smuzhiyun break;
126*4882a593Smuzhiyun case 8000:
127*4882a593Smuzhiyun clock = GD24_8000;
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun default:
130*4882a593Smuzhiyun dev_err(chip->card->dev,
131*4882a593Smuzhiyun "set_sample_rate: Error, invalid sample rate %d\n",
132*4882a593Smuzhiyun rate);
133*4882a593Smuzhiyun return -EINVAL;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if (wait_handshake(chip))
137*4882a593Smuzhiyun return -EIO;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun dev_dbg(chip->card->dev,
140*4882a593Smuzhiyun "set_sample_rate: %d clock %d\n", rate, clock);
141*4882a593Smuzhiyun chip->sample_rate = rate;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Override the sample rate if this card is set to Echo sync. */
144*4882a593Smuzhiyun if (chip->input_clock == ECHO_CLOCK_ESYNC)
145*4882a593Smuzhiyun clock = GD24_EXT_SYNC;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */
148*4882a593Smuzhiyun chip->comm_page->gd_clock_state = clock;
149*4882a593Smuzhiyun clear_handshake(chip);
150*4882a593Smuzhiyun return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun
set_input_clock(struct echoaudio * chip,u16 clock)155*4882a593Smuzhiyun static int set_input_clock(struct echoaudio *chip, u16 clock)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun if (snd_BUG_ON(clock != ECHO_CLOCK_INTERNAL &&
158*4882a593Smuzhiyun clock != ECHO_CLOCK_ESYNC))
159*4882a593Smuzhiyun return -EINVAL;
160*4882a593Smuzhiyun chip->input_clock = clock;
161*4882a593Smuzhiyun return set_sample_rate(chip, chip->sample_rate);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
164