xref: /OK3568_Linux_fs/kernel/sound/pci/ctxfi/cthardware.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun  * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * @File	cthardware.h
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * @Brief
8*4882a593Smuzhiyun  * This file contains the definition of hardware access methord.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * @Author	Liu Chun
11*4882a593Smuzhiyun  * @Date 	May 13 2008
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #ifndef CTHARDWARE_H
15*4882a593Smuzhiyun #define CTHARDWARE_H
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/types.h>
18*4882a593Smuzhiyun #include <linux/pci.h>
19*4882a593Smuzhiyun #include <sound/core.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun enum CHIPTYP {
22*4882a593Smuzhiyun 	ATC20K1,
23*4882a593Smuzhiyun 	ATC20K2,
24*4882a593Smuzhiyun 	ATCNONE
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun enum CTCARDS {
28*4882a593Smuzhiyun 	/* 20k1 models */
29*4882a593Smuzhiyun 	CTSB046X,
30*4882a593Smuzhiyun 	CT20K1_MODEL_FIRST = CTSB046X,
31*4882a593Smuzhiyun 	CTSB055X,
32*4882a593Smuzhiyun 	CTSB073X,
33*4882a593Smuzhiyun 	CTUAA,
34*4882a593Smuzhiyun 	CT20K1_UNKNOWN,
35*4882a593Smuzhiyun 	/* 20k2 models */
36*4882a593Smuzhiyun 	CTSB0760,
37*4882a593Smuzhiyun 	CT20K2_MODEL_FIRST = CTSB0760,
38*4882a593Smuzhiyun 	CTHENDRIX,
39*4882a593Smuzhiyun 	CTSB0880,
40*4882a593Smuzhiyun 	CTSB1270,
41*4882a593Smuzhiyun 	CT20K2_UNKNOWN,
42*4882a593Smuzhiyun 	NUM_CTCARDS		/* This should always be the last */
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* Type of input source for ADC */
46*4882a593Smuzhiyun enum ADCSRC{
47*4882a593Smuzhiyun 	ADC_MICIN,
48*4882a593Smuzhiyun 	ADC_LINEIN,
49*4882a593Smuzhiyun 	ADC_VIDEO,
50*4882a593Smuzhiyun 	ADC_AUX,
51*4882a593Smuzhiyun 	ADC_NONE	/* Switch to digital input */
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun struct card_conf {
55*4882a593Smuzhiyun 	/* device virtual mem page table page physical addr
56*4882a593Smuzhiyun 	 * (supporting one page table page now) */
57*4882a593Smuzhiyun 	unsigned long vm_pgt_phys;
58*4882a593Smuzhiyun 	unsigned int rsr;	/* reference sample rate in Hzs*/
59*4882a593Smuzhiyun 	unsigned int msr;	/* master sample rate in rsrs */
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun struct capabilities {
63*4882a593Smuzhiyun 	unsigned int digit_io_switch:1;
64*4882a593Smuzhiyun 	unsigned int dedicated_mic:1;
65*4882a593Smuzhiyun 	unsigned int output_switch:1;
66*4882a593Smuzhiyun 	unsigned int mic_source_switch:1;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun struct hw {
70*4882a593Smuzhiyun 	int (*card_init)(struct hw *hw, struct card_conf *info);
71*4882a593Smuzhiyun 	int (*card_stop)(struct hw *hw);
72*4882a593Smuzhiyun 	int (*pll_init)(struct hw *hw, unsigned int rsr);
73*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
74*4882a593Smuzhiyun 	int (*suspend)(struct hw *hw);
75*4882a593Smuzhiyun 	int (*resume)(struct hw *hw, struct card_conf *info);
76*4882a593Smuzhiyun #endif
77*4882a593Smuzhiyun 	int (*is_adc_source_selected)(struct hw *hw, enum ADCSRC source);
78*4882a593Smuzhiyun 	int (*select_adc_source)(struct hw *hw, enum ADCSRC source);
79*4882a593Smuzhiyun 	struct capabilities (*capabilities)(struct hw *hw);
80*4882a593Smuzhiyun 	int (*output_switch_get)(struct hw *hw);
81*4882a593Smuzhiyun 	int (*output_switch_put)(struct hw *hw, int position);
82*4882a593Smuzhiyun 	int (*mic_source_switch_get)(struct hw *hw);
83*4882a593Smuzhiyun 	int (*mic_source_switch_put)(struct hw *hw, int position);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* SRC operations */
86*4882a593Smuzhiyun 	int (*src_rsc_get_ctrl_blk)(void **rblk);
87*4882a593Smuzhiyun 	int (*src_rsc_put_ctrl_blk)(void *blk);
88*4882a593Smuzhiyun 	int (*src_set_state)(void *blk, unsigned int state);
89*4882a593Smuzhiyun 	int (*src_set_bm)(void *blk, unsigned int bm);
90*4882a593Smuzhiyun 	int (*src_set_rsr)(void *blk, unsigned int rsr);
91*4882a593Smuzhiyun 	int (*src_set_sf)(void *blk, unsigned int sf);
92*4882a593Smuzhiyun 	int (*src_set_wr)(void *blk, unsigned int wr);
93*4882a593Smuzhiyun 	int (*src_set_pm)(void *blk, unsigned int pm);
94*4882a593Smuzhiyun 	int (*src_set_rom)(void *blk, unsigned int rom);
95*4882a593Smuzhiyun 	int (*src_set_vo)(void *blk, unsigned int vo);
96*4882a593Smuzhiyun 	int (*src_set_st)(void *blk, unsigned int st);
97*4882a593Smuzhiyun 	int (*src_set_ie)(void *blk, unsigned int ie);
98*4882a593Smuzhiyun 	int (*src_set_ilsz)(void *blk, unsigned int ilsz);
99*4882a593Smuzhiyun 	int (*src_set_bp)(void *blk, unsigned int bp);
100*4882a593Smuzhiyun 	int (*src_set_cisz)(void *blk, unsigned int cisz);
101*4882a593Smuzhiyun 	int (*src_set_ca)(void *blk, unsigned int ca);
102*4882a593Smuzhiyun 	int (*src_set_sa)(void *blk, unsigned int sa);
103*4882a593Smuzhiyun 	int (*src_set_la)(void *blk, unsigned int la);
104*4882a593Smuzhiyun 	int (*src_set_pitch)(void *blk, unsigned int pitch);
105*4882a593Smuzhiyun 	int (*src_set_clear_zbufs)(void *blk, unsigned int clear);
106*4882a593Smuzhiyun 	int (*src_set_dirty)(void *blk, unsigned int flags);
107*4882a593Smuzhiyun 	int (*src_set_dirty_all)(void *blk);
108*4882a593Smuzhiyun 	int (*src_commit_write)(struct hw *hw, unsigned int idx, void *blk);
109*4882a593Smuzhiyun 	int (*src_get_ca)(struct hw *hw, unsigned int idx, void *blk);
110*4882a593Smuzhiyun 	unsigned int (*src_get_dirty)(void *blk);
111*4882a593Smuzhiyun 	unsigned int (*src_dirty_conj_mask)(void);
112*4882a593Smuzhiyun 	int (*src_mgr_get_ctrl_blk)(void **rblk);
113*4882a593Smuzhiyun 	int (*src_mgr_put_ctrl_blk)(void *blk);
114*4882a593Smuzhiyun 	/* syncly enable src @idx */
115*4882a593Smuzhiyun 	int (*src_mgr_enbs_src)(void *blk, unsigned int idx);
116*4882a593Smuzhiyun 	/* enable src @idx */
117*4882a593Smuzhiyun 	int (*src_mgr_enb_src)(void *blk, unsigned int idx);
118*4882a593Smuzhiyun 	/* disable src @idx */
119*4882a593Smuzhiyun 	int (*src_mgr_dsb_src)(void *blk, unsigned int idx);
120*4882a593Smuzhiyun 	int (*src_mgr_commit_write)(struct hw *hw, void *blk);
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	/* SRC Input Mapper operations */
123*4882a593Smuzhiyun 	int (*srcimp_mgr_get_ctrl_blk)(void **rblk);
124*4882a593Smuzhiyun 	int (*srcimp_mgr_put_ctrl_blk)(void *blk);
125*4882a593Smuzhiyun 	int (*srcimp_mgr_set_imaparc)(void *blk, unsigned int slot);
126*4882a593Smuzhiyun 	int (*srcimp_mgr_set_imapuser)(void *blk, unsigned int user);
127*4882a593Smuzhiyun 	int (*srcimp_mgr_set_imapnxt)(void *blk, unsigned int next);
128*4882a593Smuzhiyun 	int (*srcimp_mgr_set_imapaddr)(void *blk, unsigned int addr);
129*4882a593Smuzhiyun 	int (*srcimp_mgr_commit_write)(struct hw *hw, void *blk);
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	/* AMIXER operations */
132*4882a593Smuzhiyun 	int (*amixer_rsc_get_ctrl_blk)(void **rblk);
133*4882a593Smuzhiyun 	int (*amixer_rsc_put_ctrl_blk)(void *blk);
134*4882a593Smuzhiyun 	int (*amixer_mgr_get_ctrl_blk)(void **rblk);
135*4882a593Smuzhiyun 	int (*amixer_mgr_put_ctrl_blk)(void *blk);
136*4882a593Smuzhiyun 	int (*amixer_set_mode)(void *blk, unsigned int mode);
137*4882a593Smuzhiyun 	int (*amixer_set_iv)(void *blk, unsigned int iv);
138*4882a593Smuzhiyun 	int (*amixer_set_x)(void *blk, unsigned int x);
139*4882a593Smuzhiyun 	int (*amixer_set_y)(void *blk, unsigned int y);
140*4882a593Smuzhiyun 	int (*amixer_set_sadr)(void *blk, unsigned int sadr);
141*4882a593Smuzhiyun 	int (*amixer_set_se)(void *blk, unsigned int se);
142*4882a593Smuzhiyun 	int (*amixer_set_dirty)(void *blk, unsigned int flags);
143*4882a593Smuzhiyun 	int (*amixer_set_dirty_all)(void *blk);
144*4882a593Smuzhiyun 	int (*amixer_commit_write)(struct hw *hw, unsigned int idx, void *blk);
145*4882a593Smuzhiyun 	int (*amixer_get_y)(void *blk);
146*4882a593Smuzhiyun 	unsigned int (*amixer_get_dirty)(void *blk);
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	/* DAIO operations */
149*4882a593Smuzhiyun 	int (*dai_get_ctrl_blk)(void **rblk);
150*4882a593Smuzhiyun 	int (*dai_put_ctrl_blk)(void *blk);
151*4882a593Smuzhiyun 	int (*dai_srt_set_srco)(void *blk, unsigned int src);
152*4882a593Smuzhiyun 	int (*dai_srt_set_srcm)(void *blk, unsigned int src);
153*4882a593Smuzhiyun 	int (*dai_srt_set_rsr)(void *blk, unsigned int rsr);
154*4882a593Smuzhiyun 	int (*dai_srt_set_drat)(void *blk, unsigned int drat);
155*4882a593Smuzhiyun 	int (*dai_srt_set_ec)(void *blk, unsigned int ec);
156*4882a593Smuzhiyun 	int (*dai_srt_set_et)(void *blk, unsigned int et);
157*4882a593Smuzhiyun 	int (*dai_commit_write)(struct hw *hw, unsigned int idx, void *blk);
158*4882a593Smuzhiyun 	int (*dao_get_ctrl_blk)(void **rblk);
159*4882a593Smuzhiyun 	int (*dao_put_ctrl_blk)(void *blk);
160*4882a593Smuzhiyun 	int (*dao_set_spos)(void *blk, unsigned int spos);
161*4882a593Smuzhiyun 	int (*dao_commit_write)(struct hw *hw, unsigned int idx, void *blk);
162*4882a593Smuzhiyun 	int (*dao_get_spos)(void *blk, unsigned int *spos);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	int (*daio_mgr_get_ctrl_blk)(struct hw *hw, void **rblk);
165*4882a593Smuzhiyun 	int (*daio_mgr_put_ctrl_blk)(void *blk);
166*4882a593Smuzhiyun 	int (*daio_mgr_enb_dai)(void *blk, unsigned int idx);
167*4882a593Smuzhiyun 	int (*daio_mgr_dsb_dai)(void *blk, unsigned int idx);
168*4882a593Smuzhiyun 	int (*daio_mgr_enb_dao)(void *blk, unsigned int idx);
169*4882a593Smuzhiyun 	int (*daio_mgr_dsb_dao)(void *blk, unsigned int idx);
170*4882a593Smuzhiyun 	int (*daio_mgr_dao_init)(void *blk, unsigned int idx,
171*4882a593Smuzhiyun 						unsigned int conf);
172*4882a593Smuzhiyun 	int (*daio_mgr_set_imaparc)(void *blk, unsigned int slot);
173*4882a593Smuzhiyun 	int (*daio_mgr_set_imapnxt)(void *blk, unsigned int next);
174*4882a593Smuzhiyun 	int (*daio_mgr_set_imapaddr)(void *blk, unsigned int addr);
175*4882a593Smuzhiyun 	int (*daio_mgr_commit_write)(struct hw *hw, void *blk);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	int (*set_timer_irq)(struct hw *hw, int enable);
178*4882a593Smuzhiyun 	int (*set_timer_tick)(struct hw *hw, unsigned int tick);
179*4882a593Smuzhiyun 	unsigned int (*get_wc)(struct hw *hw);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	void (*irq_callback)(void *data, unsigned int bit);
182*4882a593Smuzhiyun 	void *irq_callback_data;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	struct pci_dev *pci;	/* the pci kernel structure of this card */
185*4882a593Smuzhiyun 	struct snd_card *card;	/* pointer to this card */
186*4882a593Smuzhiyun 	int irq;
187*4882a593Smuzhiyun 	unsigned long io_base;
188*4882a593Smuzhiyun 	void __iomem *mem_base;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	enum CHIPTYP chip_type;
191*4882a593Smuzhiyun 	enum CTCARDS model;
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun int create_hw_obj(struct pci_dev *pci, enum CHIPTYP chip_type,
195*4882a593Smuzhiyun 		  enum CTCARDS model, struct hw **rhw);
196*4882a593Smuzhiyun int destroy_hw_obj(struct hw *hw);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun unsigned int get_field(unsigned int data, unsigned int field);
199*4882a593Smuzhiyun void set_field(unsigned int *data, unsigned int field, unsigned int value);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun /* IRQ bits */
202*4882a593Smuzhiyun #define	PLL_INT		(1 << 10) /* PLL input-clock out-of-range */
203*4882a593Smuzhiyun #define FI_INT		(1 << 9)  /* forced interrupt */
204*4882a593Smuzhiyun #define IT_INT		(1 << 8)  /* timer interrupt */
205*4882a593Smuzhiyun #define PCI_INT		(1 << 7)  /* PCI bus error pending */
206*4882a593Smuzhiyun #define URT_INT		(1 << 6)  /* UART Tx/Rx */
207*4882a593Smuzhiyun #define GPI_INT		(1 << 5)  /* GPI pin */
208*4882a593Smuzhiyun #define MIX_INT		(1 << 4)  /* mixer parameter segment FIFO channels */
209*4882a593Smuzhiyun #define DAI_INT		(1 << 3)  /* DAI (SR-tracker or SPDIF-receiver) */
210*4882a593Smuzhiyun #define TP_INT		(1 << 2)  /* transport priority queue */
211*4882a593Smuzhiyun #define DSP_INT		(1 << 1)  /* DSP */
212*4882a593Smuzhiyun #define SRC_INT		(1 << 0)  /* SRC channels */
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun #endif /* CTHARDWARE_H */
215