1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /** 3*4882a593Smuzhiyun * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _20K2REGISTERS_H_ 7*4882a593Smuzhiyun #define _20K2REGISTERS_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Timer Registers */ 11*4882a593Smuzhiyun #define WC 0x1b7000 12*4882a593Smuzhiyun #define TIMR 0x1b7004 13*4882a593Smuzhiyun # define TIMR_IE (1<<15) 14*4882a593Smuzhiyun # define TIMR_IP (1<<14) 15*4882a593Smuzhiyun #define GIP 0x1b7010 16*4882a593Smuzhiyun #define GIE 0x1b7014 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* I2C Registers */ 19*4882a593Smuzhiyun #define I2C_IF_ADDRESS 0x1B9000 20*4882a593Smuzhiyun #define I2C_IF_WDATA 0x1B9004 21*4882a593Smuzhiyun #define I2C_IF_RDATA 0x1B9008 22*4882a593Smuzhiyun #define I2C_IF_STATUS 0x1B900C 23*4882a593Smuzhiyun #define I2C_IF_WLOCK 0x1B9010 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Global Control Registers */ 26*4882a593Smuzhiyun #define GLOBAL_CNTL_GCTL 0x1B7090 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* PLL Registers */ 29*4882a593Smuzhiyun #define PLL_CTL 0x1B7080 30*4882a593Smuzhiyun #define PLL_STAT 0x1B7084 31*4882a593Smuzhiyun #define PLL_ENB 0x1B7088 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* SRC Registers */ 34*4882a593Smuzhiyun #define SRC_CTL 0x1A0000 /* 0x1A0000 + (256 * Chn) */ 35*4882a593Smuzhiyun #define SRC_CCR 0x1A0004 /* 0x1A0004 + (256 * Chn) */ 36*4882a593Smuzhiyun #define SRC_IMAP 0x1A0008 /* 0x1A0008 + (256 * Chn) */ 37*4882a593Smuzhiyun #define SRC_CA 0x1A0010 /* 0x1A0010 + (256 * Chn) */ 38*4882a593Smuzhiyun #define SRC_CF 0x1A0014 /* 0x1A0014 + (256 * Chn) */ 39*4882a593Smuzhiyun #define SRC_SA 0x1A0018 /* 0x1A0018 + (256 * Chn) */ 40*4882a593Smuzhiyun #define SRC_LA 0x1A001C /* 0x1A001C + (256 * Chn) */ 41*4882a593Smuzhiyun #define SRC_CTLSWR 0x1A0020 /* 0x1A0020 + (256 * Chn) */ 42*4882a593Smuzhiyun #define SRC_CD 0x1A0080 /* 0x1A0080 + (256 * Chn) + (4 * Regn) */ 43*4882a593Smuzhiyun #define SRC_MCTL 0x1A012C 44*4882a593Smuzhiyun #define SRC_IP 0x1A102C /* 0x1A102C + (256 * Regn) */ 45*4882a593Smuzhiyun #define SRC_ENB 0x1A282C /* 0x1A282C + (256 * Regn) */ 46*4882a593Smuzhiyun #define SRC_ENBSTAT 0x1A202C 47*4882a593Smuzhiyun #define SRC_ENBSA 0x1A232C 48*4882a593Smuzhiyun #define SRC_DN0Z 0x1A0030 49*4882a593Smuzhiyun #define SRC_DN1Z 0x1A0040 50*4882a593Smuzhiyun #define SRC_UPZ 0x1A0060 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* GPIO Registers */ 53*4882a593Smuzhiyun #define GPIO_DATA 0x1B7020 54*4882a593Smuzhiyun #define GPIO_CTRL 0x1B7024 55*4882a593Smuzhiyun #define GPIO_EXT_DATA 0x1B70A0 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Virtual memory registers */ 58*4882a593Smuzhiyun #define VMEM_PTPAL 0x1C6300 /* 0x1C6300 + (16 * Chn) */ 59*4882a593Smuzhiyun #define VMEM_PTPAH 0x1C6304 /* 0x1C6304 + (16 * Chn) */ 60*4882a593Smuzhiyun #define VMEM_CTL 0x1C7000 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Transport Registers */ 63*4882a593Smuzhiyun #define TRANSPORT_ENB 0x1B6000 64*4882a593Smuzhiyun #define TRANSPORT_CTL 0x1B6004 65*4882a593Smuzhiyun #define TRANSPORT_INT 0x1B6008 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Audio IO */ 68*4882a593Smuzhiyun #define AUDIO_IO_AIM 0x1B5000 /* 0x1B5000 + (0x04 * Chn) */ 69*4882a593Smuzhiyun #define AUDIO_IO_TX_CTL 0x1B5400 /* 0x1B5400 + (0x40 * Chn) */ 70*4882a593Smuzhiyun #define AUDIO_IO_TX_CSTAT_L 0x1B5408 /* 0x1B5408 + (0x40 * Chn) */ 71*4882a593Smuzhiyun #define AUDIO_IO_TX_CSTAT_H 0x1B540C /* 0x1B540C + (0x40 * Chn) */ 72*4882a593Smuzhiyun #define AUDIO_IO_RX_CTL 0x1B5410 /* 0x1B5410 + (0x40 * Chn) */ 73*4882a593Smuzhiyun #define AUDIO_IO_RX_SRT_CTL 0x1B5420 /* 0x1B5420 + (0x40 * Chn) */ 74*4882a593Smuzhiyun #define AUDIO_IO_MCLK 0x1B5600 75*4882a593Smuzhiyun #define AUDIO_IO_TX_BLRCLK 0x1B5604 76*4882a593Smuzhiyun #define AUDIO_IO_RX_BLRCLK 0x1B5608 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Mixer */ 79*4882a593Smuzhiyun #define MIXER_AMOPLO 0x130000 /* 0x130000 + (8 * Chn) [4095 : 0] */ 80*4882a593Smuzhiyun #define MIXER_AMOPHI 0x130004 /* 0x130004 + (8 * Chn) [4095 : 0] */ 81*4882a593Smuzhiyun #define MIXER_PRING_LO_HI 0x188000 /* 0x188000 + (4 * Chn) [4095 : 0] */ 82*4882a593Smuzhiyun #define MIXER_PMOPLO 0x138000 /* 0x138000 + (8 * Chn) [4095 : 0] */ 83*4882a593Smuzhiyun #define MIXER_PMOPHI 0x138004 /* 0x138004 + (8 * Chn) [4095 : 0] */ 84*4882a593Smuzhiyun #define MIXER_AR_ENABLE 0x19000C 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif 87