xref: /OK3568_Linux_fs/kernel/sound/pci/ca0106/ca0106_main.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
4*4882a593Smuzhiyun  *  Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
5*4882a593Smuzhiyun  *  Version: 0.0.25
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *  FEATURES currently supported:
8*4882a593Smuzhiyun  *    Front, Rear and Center/LFE.
9*4882a593Smuzhiyun  *    Surround40 and Surround51.
10*4882a593Smuzhiyun  *    Capture from MIC an LINE IN input.
11*4882a593Smuzhiyun  *    SPDIF digital playback of PCM stereo and AC3/DTS works.
12*4882a593Smuzhiyun  *    (One can use a standard mono mini-jack to one RCA plugs cable.
13*4882a593Smuzhiyun  *     or one can use a standard stereo mini-jack to two RCA plugs cable.
14*4882a593Smuzhiyun  *     Plug one of the RCA plugs into the Coax input of the external decoder/receiver.)
15*4882a593Smuzhiyun  *    ( In theory one could output 3 different AC3 streams at once, to 3 different SPDIF outputs. )
16*4882a593Smuzhiyun  *    Notes on how to capture sound:
17*4882a593Smuzhiyun  *      The AC97 is used in the PLAYBACK direction.
18*4882a593Smuzhiyun  *      The output from the AC97 chip, instead of reaching the speakers, is fed into the Philips 1361T ADC.
19*4882a593Smuzhiyun  *      So, to record from the MIC, set the MIC Playback volume to max,
20*4882a593Smuzhiyun  *      unmute the MIC and turn up the MASTER Playback volume.
21*4882a593Smuzhiyun  *      So, to prevent feedback when capturing, minimise the "Capture feedback into Playback" volume.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  *    The only playback controls that currently do anything are: -
24*4882a593Smuzhiyun  *    Analog Front
25*4882a593Smuzhiyun  *    Analog Rear
26*4882a593Smuzhiyun  *    Analog Center/LFE
27*4882a593Smuzhiyun  *    SPDIF Front
28*4882a593Smuzhiyun  *    SPDIF Rear
29*4882a593Smuzhiyun  *    SPDIF Center/LFE
30*4882a593Smuzhiyun  *
31*4882a593Smuzhiyun  *    For capture from Mic in or Line in.
32*4882a593Smuzhiyun  *    Digital/Analog ( switch must be in Analog mode for CAPTURE. )
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  *    CAPTURE feedback into PLAYBACK
35*4882a593Smuzhiyun  *
36*4882a593Smuzhiyun  *  Changelog:
37*4882a593Smuzhiyun  *    Support interrupts per period.
38*4882a593Smuzhiyun  *    Removed noise from Center/LFE channel when in Analog mode.
39*4882a593Smuzhiyun  *    Rename and remove mixer controls.
40*4882a593Smuzhiyun  *  0.0.6
41*4882a593Smuzhiyun  *    Use separate card based DMA buffer for periods table list.
42*4882a593Smuzhiyun  *  0.0.7
43*4882a593Smuzhiyun  *    Change remove and rename ctrls into lists.
44*4882a593Smuzhiyun  *  0.0.8
45*4882a593Smuzhiyun  *    Try to fix capture sources.
46*4882a593Smuzhiyun  *  0.0.9
47*4882a593Smuzhiyun  *    Fix AC3 output.
48*4882a593Smuzhiyun  *    Enable S32_LE format support.
49*4882a593Smuzhiyun  *  0.0.10
50*4882a593Smuzhiyun  *    Enable playback 48000 and 96000 rates. (Rates other that these do not work, even with "plug:front".)
51*4882a593Smuzhiyun  *  0.0.11
52*4882a593Smuzhiyun  *    Add Model name recognition.
53*4882a593Smuzhiyun  *  0.0.12
54*4882a593Smuzhiyun  *    Correct interrupt timing. interrupt at end of period, instead of in the middle of a playback period.
55*4882a593Smuzhiyun  *    Remove redundent "voice" handling.
56*4882a593Smuzhiyun  *  0.0.13
57*4882a593Smuzhiyun  *    Single trigger call for multi channels.
58*4882a593Smuzhiyun  *  0.0.14
59*4882a593Smuzhiyun  *    Set limits based on what the sound card hardware can do.
60*4882a593Smuzhiyun  *    playback periods_min=2, periods_max=8
61*4882a593Smuzhiyun  *    capture hw constraints require period_size = n * 64 bytes.
62*4882a593Smuzhiyun  *    playback hw constraints require period_size = n * 64 bytes.
63*4882a593Smuzhiyun  *  0.0.15
64*4882a593Smuzhiyun  *    Minor updates.
65*4882a593Smuzhiyun  *  0.0.16
66*4882a593Smuzhiyun  *    Implement 192000 sample rate.
67*4882a593Smuzhiyun  *  0.0.17
68*4882a593Smuzhiyun  *    Add support for SB0410 and SB0413.
69*4882a593Smuzhiyun  *  0.0.18
70*4882a593Smuzhiyun  *    Modified Copyright message.
71*4882a593Smuzhiyun  *  0.0.19
72*4882a593Smuzhiyun  *    Finally fix support for SB Live 24 bit. SB0410 and SB0413.
73*4882a593Smuzhiyun  *    The output codec needs resetting, otherwise all output is muted.
74*4882a593Smuzhiyun  *  0.0.20
75*4882a593Smuzhiyun  *    Merge "pci_disable_device(pci);" fixes.
76*4882a593Smuzhiyun  *  0.0.21
77*4882a593Smuzhiyun  *    Add 4 capture channels. (SPDIF only comes in on channel 0. )
78*4882a593Smuzhiyun  *    Add SPDIF capture using optional digital I/O module for SB Live 24bit. (Analog capture does not yet work.)
79*4882a593Smuzhiyun  *  0.0.22
80*4882a593Smuzhiyun  *    Add support for MSI K8N Diamond Motherboard with onboard SB Live 24bit without AC97. From kiksen, bug #901
81*4882a593Smuzhiyun  *  0.0.23
82*4882a593Smuzhiyun  *    Implement support for Line-in capture on SB Live 24bit.
83*4882a593Smuzhiyun  *  0.0.24
84*4882a593Smuzhiyun  *    Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
85*4882a593Smuzhiyun  *  0.0.25
86*4882a593Smuzhiyun  *    Powerdown SPI DAC channels when not in use
87*4882a593Smuzhiyun  *
88*4882a593Smuzhiyun  *  BUGS:
89*4882a593Smuzhiyun  *    Some stability problems when unloading the snd-ca0106 kernel module.
90*4882a593Smuzhiyun  *    --
91*4882a593Smuzhiyun  *
92*4882a593Smuzhiyun  *  TODO:
93*4882a593Smuzhiyun  *    4 Capture channels, only one implemented so far.
94*4882a593Smuzhiyun  *    Other capture rates apart from 48khz not implemented.
95*4882a593Smuzhiyun  *    MIDI
96*4882a593Smuzhiyun  *    --
97*4882a593Smuzhiyun  *  GENERAL INFO:
98*4882a593Smuzhiyun  *    Model: SB0310
99*4882a593Smuzhiyun  *    P17 Chip: CA0106-DAT
100*4882a593Smuzhiyun  *    AC97 Codec: STAC 9721
101*4882a593Smuzhiyun  *    ADC: Philips 1361T (Stereo 24bit)
102*4882a593Smuzhiyun  *    DAC: WM8746EDS (6-channel, 24bit, 192Khz)
103*4882a593Smuzhiyun  *
104*4882a593Smuzhiyun  *  GENERAL INFO:
105*4882a593Smuzhiyun  *    Model: SB0410
106*4882a593Smuzhiyun  *    P17 Chip: CA0106-DAT
107*4882a593Smuzhiyun  *    AC97 Codec: None
108*4882a593Smuzhiyun  *    ADC: WM8775EDS (4 Channel)
109*4882a593Smuzhiyun  *    DAC: CS4382 (114 dB, 24-Bit, 192 kHz, 8-Channel D/A Converter with DSD Support)
110*4882a593Smuzhiyun  *    SPDIF Out control switches between Mic in and SPDIF out.
111*4882a593Smuzhiyun  *    No sound out or mic input working yet.
112*4882a593Smuzhiyun  *
113*4882a593Smuzhiyun  *  GENERAL INFO:
114*4882a593Smuzhiyun  *    Model: SB0413
115*4882a593Smuzhiyun  *    P17 Chip: CA0106-DAT
116*4882a593Smuzhiyun  *    AC97 Codec: None.
117*4882a593Smuzhiyun  *    ADC: Unknown
118*4882a593Smuzhiyun  *    DAC: Unknown
119*4882a593Smuzhiyun  *    Trying to handle it like the SB0410.
120*4882a593Smuzhiyun  *
121*4882a593Smuzhiyun  *  This code was initially based on code from ALSA's emu10k1x.c which is:
122*4882a593Smuzhiyun  *  Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
123*4882a593Smuzhiyun  */
124*4882a593Smuzhiyun #include <linux/delay.h>
125*4882a593Smuzhiyun #include <linux/init.h>
126*4882a593Smuzhiyun #include <linux/interrupt.h>
127*4882a593Smuzhiyun #include <linux/pci.h>
128*4882a593Smuzhiyun #include <linux/slab.h>
129*4882a593Smuzhiyun #include <linux/module.h>
130*4882a593Smuzhiyun #include <linux/dma-mapping.h>
131*4882a593Smuzhiyun #include <sound/core.h>
132*4882a593Smuzhiyun #include <sound/initval.h>
133*4882a593Smuzhiyun #include <sound/pcm.h>
134*4882a593Smuzhiyun #include <sound/ac97_codec.h>
135*4882a593Smuzhiyun #include <sound/info.h>
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun MODULE_AUTHOR("James Courtier-Dutton <James@superbug.demon.co.uk>");
138*4882a593Smuzhiyun MODULE_DESCRIPTION("CA0106");
139*4882a593Smuzhiyun MODULE_LICENSE("GPL");
140*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{Creative,SB CA0106 chip}}");
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun // module parameters (see "Module Parameters")
143*4882a593Smuzhiyun static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
144*4882a593Smuzhiyun static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
145*4882a593Smuzhiyun static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
146*4882a593Smuzhiyun static uint subsystem[SNDRV_CARDS]; /* Force card subsystem model */
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun module_param_array(index, int, NULL, 0444);
149*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for the CA0106 soundcard.");
150*4882a593Smuzhiyun module_param_array(id, charp, NULL, 0444);
151*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for the CA0106 soundcard.");
152*4882a593Smuzhiyun module_param_array(enable, bool, NULL, 0444);
153*4882a593Smuzhiyun MODULE_PARM_DESC(enable, "Enable the CA0106 soundcard.");
154*4882a593Smuzhiyun module_param_array(subsystem, uint, NULL, 0444);
155*4882a593Smuzhiyun MODULE_PARM_DESC(subsystem, "Force card subsystem model.");
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun #include "ca0106.h"
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static const struct snd_ca0106_details ca0106_chip_details[] = {
160*4882a593Smuzhiyun 	 /* Sound Blaster X-Fi Extreme Audio. This does not have an AC97. 53SB079000000 */
161*4882a593Smuzhiyun 	 /* It is really just a normal SB Live 24bit. */
162*4882a593Smuzhiyun 	 /* Tested:
163*4882a593Smuzhiyun 	  * See ALSA bug#3251
164*4882a593Smuzhiyun 	  */
165*4882a593Smuzhiyun 	 { .serial = 0x10131102,
166*4882a593Smuzhiyun 	   .name   = "X-Fi Extreme Audio [SBxxxx]",
167*4882a593Smuzhiyun 	   .gpio_type = 1,
168*4882a593Smuzhiyun 	   .i2c_adc = 1 } ,
169*4882a593Smuzhiyun 	 /* Sound Blaster X-Fi Extreme Audio. This does not have an AC97. 53SB079000000 */
170*4882a593Smuzhiyun 	 /* It is really just a normal SB Live 24bit. */
171*4882a593Smuzhiyun 	 /*
172*4882a593Smuzhiyun  	  * CTRL:CA0111-WTLF
173*4882a593Smuzhiyun 	  * ADC: WM8775SEDS
174*4882a593Smuzhiyun 	  * DAC: CS4382-KQZ
175*4882a593Smuzhiyun 	  */
176*4882a593Smuzhiyun 	 /* Tested:
177*4882a593Smuzhiyun 	  * Playback on front, rear, center/lfe speakers
178*4882a593Smuzhiyun 	  * Capture from Mic in.
179*4882a593Smuzhiyun 	  * Not-Tested:
180*4882a593Smuzhiyun 	  * Capture from Line in.
181*4882a593Smuzhiyun 	  * Playback to digital out.
182*4882a593Smuzhiyun 	  */
183*4882a593Smuzhiyun 	 { .serial = 0x10121102,
184*4882a593Smuzhiyun 	   .name   = "X-Fi Extreme Audio [SB0790]",
185*4882a593Smuzhiyun 	   .gpio_type = 1,
186*4882a593Smuzhiyun 	   .i2c_adc = 1 } ,
187*4882a593Smuzhiyun 	 /* New Dell Sound Blaster Live! 7.1 24bit. This does not have an AC97.  */
188*4882a593Smuzhiyun 	 /* AudigyLS[SB0310] */
189*4882a593Smuzhiyun 	 { .serial = 0x10021102,
190*4882a593Smuzhiyun 	   .name   = "AudigyLS [SB0310]",
191*4882a593Smuzhiyun 	   .ac97   = 1 } ,
192*4882a593Smuzhiyun 	 /* Unknown AudigyLS that also says SB0310 on it */
193*4882a593Smuzhiyun 	 { .serial = 0x10051102,
194*4882a593Smuzhiyun 	   .name   = "AudigyLS [SB0310b]",
195*4882a593Smuzhiyun 	   .ac97   = 1 } ,
196*4882a593Smuzhiyun 	 /* New Sound Blaster Live! 7.1 24bit. This does not have an AC97. 53SB041000001 */
197*4882a593Smuzhiyun 	 { .serial = 0x10061102,
198*4882a593Smuzhiyun 	   .name   = "Live! 7.1 24bit [SB0410]",
199*4882a593Smuzhiyun 	   .gpio_type = 1,
200*4882a593Smuzhiyun 	   .i2c_adc = 1 } ,
201*4882a593Smuzhiyun 	 /* New Dell Sound Blaster Live! 7.1 24bit. This does not have an AC97.  */
202*4882a593Smuzhiyun 	 { .serial = 0x10071102,
203*4882a593Smuzhiyun 	   .name   = "Live! 7.1 24bit [SB0413]",
204*4882a593Smuzhiyun 	   .gpio_type = 1,
205*4882a593Smuzhiyun 	   .i2c_adc = 1 } ,
206*4882a593Smuzhiyun 	 /* New Audigy SE. Has a different DAC. */
207*4882a593Smuzhiyun 	 /* SB0570:
208*4882a593Smuzhiyun 	  * CTRL:CA0106-DAT
209*4882a593Smuzhiyun 	  * ADC: WM8775EDS
210*4882a593Smuzhiyun 	  * DAC: WM8768GEDS
211*4882a593Smuzhiyun 	  */
212*4882a593Smuzhiyun 	 { .serial = 0x100a1102,
213*4882a593Smuzhiyun 	   .name   = "Audigy SE [SB0570]",
214*4882a593Smuzhiyun 	   .gpio_type = 1,
215*4882a593Smuzhiyun 	   .i2c_adc = 1,
216*4882a593Smuzhiyun 	   .spi_dac = 0x4021 } ,
217*4882a593Smuzhiyun 	 /* New Audigy LS. Has a different DAC. */
218*4882a593Smuzhiyun 	 /* SB0570:
219*4882a593Smuzhiyun 	  * CTRL:CA0106-DAT
220*4882a593Smuzhiyun 	  * ADC: WM8775EDS
221*4882a593Smuzhiyun 	  * DAC: WM8768GEDS
222*4882a593Smuzhiyun 	  */
223*4882a593Smuzhiyun 	 { .serial = 0x10111102,
224*4882a593Smuzhiyun 	   .name   = "Audigy SE OEM [SB0570a]",
225*4882a593Smuzhiyun 	   .gpio_type = 1,
226*4882a593Smuzhiyun 	   .i2c_adc = 1,
227*4882a593Smuzhiyun 	   .spi_dac = 0x4021 } ,
228*4882a593Smuzhiyun 	/* Sound Blaster 5.1vx
229*4882a593Smuzhiyun 	 * Tested: Playback on front, rear, center/lfe speakers
230*4882a593Smuzhiyun 	 * Not-Tested: Capture
231*4882a593Smuzhiyun 	 */
232*4882a593Smuzhiyun 	{ .serial = 0x10041102,
233*4882a593Smuzhiyun 	  .name   = "Sound Blaster 5.1vx [SB1070]",
234*4882a593Smuzhiyun 	  .gpio_type = 1,
235*4882a593Smuzhiyun 	  .i2c_adc = 0,
236*4882a593Smuzhiyun 	  .spi_dac = 0x0124
237*4882a593Smuzhiyun 	 } ,
238*4882a593Smuzhiyun 	 /* MSI K8N Diamond Motherboard with onboard SB Live 24bit without AC97 */
239*4882a593Smuzhiyun 	 /* SB0438
240*4882a593Smuzhiyun 	  * CTRL:CA0106-DAT
241*4882a593Smuzhiyun 	  * ADC: WM8775SEDS
242*4882a593Smuzhiyun 	  * DAC: CS4382-KQZ
243*4882a593Smuzhiyun 	  */
244*4882a593Smuzhiyun 	 { .serial = 0x10091462,
245*4882a593Smuzhiyun 	   .name   = "MSI K8N Diamond MB [SB0438]",
246*4882a593Smuzhiyun 	   .gpio_type = 2,
247*4882a593Smuzhiyun 	   .i2c_adc = 1 } ,
248*4882a593Smuzhiyun 	 /* MSI K8N Diamond PLUS MB */
249*4882a593Smuzhiyun 	 { .serial = 0x10091102,
250*4882a593Smuzhiyun 	   .name   = "MSI K8N Diamond MB",
251*4882a593Smuzhiyun 	   .gpio_type = 2,
252*4882a593Smuzhiyun 	   .i2c_adc = 1,
253*4882a593Smuzhiyun 	   .spi_dac = 0x4021 } ,
254*4882a593Smuzhiyun 	/* Giga-byte GA-G1975X mobo
255*4882a593Smuzhiyun 	 * Novell bnc#395807
256*4882a593Smuzhiyun 	 */
257*4882a593Smuzhiyun 	/* FIXME: the GPIO and I2C setting aren't tested well */
258*4882a593Smuzhiyun 	{ .serial = 0x1458a006,
259*4882a593Smuzhiyun 	  .name = "Giga-byte GA-G1975X",
260*4882a593Smuzhiyun 	  .gpio_type = 1,
261*4882a593Smuzhiyun 	  .i2c_adc = 1 },
262*4882a593Smuzhiyun 	 /* Shuttle XPC SD31P which has an onboard Creative Labs
263*4882a593Smuzhiyun 	  * Sound Blaster Live! 24-bit EAX
264*4882a593Smuzhiyun 	  * high-definition 7.1 audio processor".
265*4882a593Smuzhiyun 	  * Added using info from andrewvegan in alsa bug #1298
266*4882a593Smuzhiyun 	  */
267*4882a593Smuzhiyun 	 { .serial = 0x30381297,
268*4882a593Smuzhiyun 	   .name   = "Shuttle XPC SD31P [SD31P]",
269*4882a593Smuzhiyun 	   .gpio_type = 1,
270*4882a593Smuzhiyun 	   .i2c_adc = 1 } ,
271*4882a593Smuzhiyun 	/* Shuttle XPC SD11G5 which has an onboard Creative Labs
272*4882a593Smuzhiyun 	 * Sound Blaster Live! 24-bit EAX
273*4882a593Smuzhiyun 	 * high-definition 7.1 audio processor".
274*4882a593Smuzhiyun 	 * Fixes ALSA bug#1600
275*4882a593Smuzhiyun          */
276*4882a593Smuzhiyun 	{ .serial = 0x30411297,
277*4882a593Smuzhiyun 	  .name = "Shuttle XPC SD11G5 [SD11G5]",
278*4882a593Smuzhiyun 	  .gpio_type = 1,
279*4882a593Smuzhiyun 	  .i2c_adc = 1 } ,
280*4882a593Smuzhiyun 	 { .serial = 0,
281*4882a593Smuzhiyun 	   .name   = "AudigyLS [Unknown]" }
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun /* hardware definition */
285*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ca0106_playback_hw = {
286*4882a593Smuzhiyun 	.info =			SNDRV_PCM_INFO_MMAP |
287*4882a593Smuzhiyun 				SNDRV_PCM_INFO_INTERLEAVED |
288*4882a593Smuzhiyun 				SNDRV_PCM_INFO_BLOCK_TRANSFER |
289*4882a593Smuzhiyun 				SNDRV_PCM_INFO_MMAP_VALID |
290*4882a593Smuzhiyun 				SNDRV_PCM_INFO_SYNC_START,
291*4882a593Smuzhiyun 	.formats =		SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
292*4882a593Smuzhiyun 	.rates =		(SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
293*4882a593Smuzhiyun 				 SNDRV_PCM_RATE_192000),
294*4882a593Smuzhiyun 	.rate_min =		48000,
295*4882a593Smuzhiyun 	.rate_max =		192000,
296*4882a593Smuzhiyun 	.channels_min =		2,  //1,
297*4882a593Smuzhiyun 	.channels_max =		2,  //6,
298*4882a593Smuzhiyun 	.buffer_bytes_max =	((65536 - 64) * 8),
299*4882a593Smuzhiyun 	.period_bytes_min =	64,
300*4882a593Smuzhiyun 	.period_bytes_max =	(65536 - 64),
301*4882a593Smuzhiyun 	.periods_min =		2,
302*4882a593Smuzhiyun 	.periods_max =		8,
303*4882a593Smuzhiyun 	.fifo_size =		0,
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ca0106_capture_hw = {
307*4882a593Smuzhiyun 	.info =			(SNDRV_PCM_INFO_MMAP |
308*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_INTERLEAVED |
309*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
310*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_MMAP_VALID),
311*4882a593Smuzhiyun 	.formats =		SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
312*4882a593Smuzhiyun #if 0 /* FIXME: looks like 44.1kHz capture causes noisy output on 48kHz */
313*4882a593Smuzhiyun 	.rates =		(SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
314*4882a593Smuzhiyun 				 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000),
315*4882a593Smuzhiyun 	.rate_min =		44100,
316*4882a593Smuzhiyun #else
317*4882a593Smuzhiyun 	.rates =		(SNDRV_PCM_RATE_48000 |
318*4882a593Smuzhiyun 				 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000),
319*4882a593Smuzhiyun 	.rate_min =		48000,
320*4882a593Smuzhiyun #endif /* FIXME */
321*4882a593Smuzhiyun 	.rate_max =		192000,
322*4882a593Smuzhiyun 	.channels_min =		2,
323*4882a593Smuzhiyun 	.channels_max =		2,
324*4882a593Smuzhiyun 	.buffer_bytes_max =	65536 - 128,
325*4882a593Smuzhiyun 	.period_bytes_min =	64,
326*4882a593Smuzhiyun 	.period_bytes_max =	32768 - 64,
327*4882a593Smuzhiyun 	.periods_min =		2,
328*4882a593Smuzhiyun 	.periods_max =		2,
329*4882a593Smuzhiyun 	.fifo_size =		0,
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun 
snd_ca0106_ptr_read(struct snd_ca0106 * emu,unsigned int reg,unsigned int chn)332*4882a593Smuzhiyun unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu,
333*4882a593Smuzhiyun 					  unsigned int reg,
334*4882a593Smuzhiyun 					  unsigned int chn)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun 	unsigned long flags;
337*4882a593Smuzhiyun 	unsigned int regptr, val;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	regptr = (reg << 16) | chn;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	spin_lock_irqsave(&emu->emu_lock, flags);
342*4882a593Smuzhiyun 	outl(regptr, emu->port + PTR);
343*4882a593Smuzhiyun 	val = inl(emu->port + DATA);
344*4882a593Smuzhiyun 	spin_unlock_irqrestore(&emu->emu_lock, flags);
345*4882a593Smuzhiyun 	return val;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
snd_ca0106_ptr_write(struct snd_ca0106 * emu,unsigned int reg,unsigned int chn,unsigned int data)348*4882a593Smuzhiyun void snd_ca0106_ptr_write(struct snd_ca0106 *emu,
349*4882a593Smuzhiyun 				   unsigned int reg,
350*4882a593Smuzhiyun 				   unsigned int chn,
351*4882a593Smuzhiyun 				   unsigned int data)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	unsigned int regptr;
354*4882a593Smuzhiyun 	unsigned long flags;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	regptr = (reg << 16) | chn;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	spin_lock_irqsave(&emu->emu_lock, flags);
359*4882a593Smuzhiyun 	outl(regptr, emu->port + PTR);
360*4882a593Smuzhiyun 	outl(data, emu->port + DATA);
361*4882a593Smuzhiyun 	spin_unlock_irqrestore(&emu->emu_lock, flags);
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun 
snd_ca0106_spi_write(struct snd_ca0106 * emu,unsigned int data)364*4882a593Smuzhiyun int snd_ca0106_spi_write(struct snd_ca0106 * emu,
365*4882a593Smuzhiyun 				   unsigned int data)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	unsigned int reset, set;
368*4882a593Smuzhiyun 	unsigned int reg, tmp;
369*4882a593Smuzhiyun 	int n, result;
370*4882a593Smuzhiyun 	reg = SPI;
371*4882a593Smuzhiyun 	if (data > 0xffff) /* Only 16bit values allowed */
372*4882a593Smuzhiyun 		return 1;
373*4882a593Smuzhiyun 	tmp = snd_ca0106_ptr_read(emu, reg, 0);
374*4882a593Smuzhiyun 	reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */
375*4882a593Smuzhiyun 	set = reset | 0x10000; /* Set xxx1xxxx */
376*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, reg, 0, reset | data);
377*4882a593Smuzhiyun 	tmp = snd_ca0106_ptr_read(emu, reg, 0); /* write post */
378*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, reg, 0, set | data);
379*4882a593Smuzhiyun 	result = 1;
380*4882a593Smuzhiyun 	/* Wait for status bit to return to 0 */
381*4882a593Smuzhiyun 	for (n = 0; n < 100; n++) {
382*4882a593Smuzhiyun 		udelay(10);
383*4882a593Smuzhiyun 		tmp = snd_ca0106_ptr_read(emu, reg, 0);
384*4882a593Smuzhiyun 		if (!(tmp & 0x10000)) {
385*4882a593Smuzhiyun 			result = 0;
386*4882a593Smuzhiyun 			break;
387*4882a593Smuzhiyun 		}
388*4882a593Smuzhiyun 	}
389*4882a593Smuzhiyun 	if (result) /* Timed out */
390*4882a593Smuzhiyun 		return 1;
391*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, reg, 0, reset | data);
392*4882a593Smuzhiyun 	tmp = snd_ca0106_ptr_read(emu, reg, 0); /* Write post */
393*4882a593Smuzhiyun 	return 0;
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun /* The ADC does not support i2c read, so only write is implemented */
snd_ca0106_i2c_write(struct snd_ca0106 * emu,u32 reg,u32 value)397*4882a593Smuzhiyun int snd_ca0106_i2c_write(struct snd_ca0106 *emu,
398*4882a593Smuzhiyun 				u32 reg,
399*4882a593Smuzhiyun 				u32 value)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun 	u32 tmp;
402*4882a593Smuzhiyun 	int timeout = 0;
403*4882a593Smuzhiyun 	int status;
404*4882a593Smuzhiyun 	int retry;
405*4882a593Smuzhiyun 	if ((reg > 0x7f) || (value > 0x1ff)) {
406*4882a593Smuzhiyun 		dev_err(emu->card->dev, "i2c_write: invalid values.\n");
407*4882a593Smuzhiyun 		return -EINVAL;
408*4882a593Smuzhiyun 	}
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	tmp = reg << 25 | value << 16;
411*4882a593Smuzhiyun 	/*
412*4882a593Smuzhiyun 	dev_dbg(emu->card->dev, "I2C-write:reg=0x%x, value=0x%x\n", reg, value);
413*4882a593Smuzhiyun 	*/
414*4882a593Smuzhiyun 	/* Not sure what this I2C channel controls. */
415*4882a593Smuzhiyun 	/* snd_ca0106_ptr_write(emu, I2C_D0, 0, tmp); */
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	/* This controls the I2C connected to the WM8775 ADC Codec */
418*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, I2C_D1, 0, tmp);
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	for (retry = 0; retry < 10; retry++) {
421*4882a593Smuzhiyun 		/* Send the data to i2c */
422*4882a593Smuzhiyun 		//tmp = snd_ca0106_ptr_read(emu, I2C_A, 0);
423*4882a593Smuzhiyun 		//tmp = tmp & ~(I2C_A_ADC_READ|I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD_MASK);
424*4882a593Smuzhiyun 		tmp = 0;
425*4882a593Smuzhiyun 		tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD);
426*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, I2C_A, 0, tmp);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 		/* Wait till the transaction ends */
429*4882a593Smuzhiyun 		while (1) {
430*4882a593Smuzhiyun 			status = snd_ca0106_ptr_read(emu, I2C_A, 0);
431*4882a593Smuzhiyun 			/*dev_dbg(emu->card->dev, "I2C:status=0x%x\n", status);*/
432*4882a593Smuzhiyun 			timeout++;
433*4882a593Smuzhiyun 			if ((status & I2C_A_ADC_START) == 0)
434*4882a593Smuzhiyun 				break;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 			if (timeout > 1000)
437*4882a593Smuzhiyun 				break;
438*4882a593Smuzhiyun 		}
439*4882a593Smuzhiyun 		//Read back and see if the transaction is successful
440*4882a593Smuzhiyun 		if ((status & I2C_A_ADC_ABORT) == 0)
441*4882a593Smuzhiyun 			break;
442*4882a593Smuzhiyun 	}
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	if (retry == 10) {
445*4882a593Smuzhiyun 		dev_err(emu->card->dev, "Writing to ADC failed!\n");
446*4882a593Smuzhiyun 		return -EINVAL;
447*4882a593Smuzhiyun 	}
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun     	return 0;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 
snd_ca0106_intr_enable(struct snd_ca0106 * emu,unsigned int intrenb)453*4882a593Smuzhiyun static void snd_ca0106_intr_enable(struct snd_ca0106 *emu, unsigned int intrenb)
454*4882a593Smuzhiyun {
455*4882a593Smuzhiyun 	unsigned long flags;
456*4882a593Smuzhiyun 	unsigned int intr_enable;
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	spin_lock_irqsave(&emu->emu_lock, flags);
459*4882a593Smuzhiyun 	intr_enable = inl(emu->port + INTE) | intrenb;
460*4882a593Smuzhiyun 	outl(intr_enable, emu->port + INTE);
461*4882a593Smuzhiyun 	spin_unlock_irqrestore(&emu->emu_lock, flags);
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun 
snd_ca0106_intr_disable(struct snd_ca0106 * emu,unsigned int intrenb)464*4882a593Smuzhiyun static void snd_ca0106_intr_disable(struct snd_ca0106 *emu, unsigned int intrenb)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun 	unsigned long flags;
467*4882a593Smuzhiyun 	unsigned int intr_enable;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	spin_lock_irqsave(&emu->emu_lock, flags);
470*4882a593Smuzhiyun 	intr_enable = inl(emu->port + INTE) & ~intrenb;
471*4882a593Smuzhiyun 	outl(intr_enable, emu->port + INTE);
472*4882a593Smuzhiyun 	spin_unlock_irqrestore(&emu->emu_lock, flags);
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 
snd_ca0106_pcm_free_substream(struct snd_pcm_runtime * runtime)476*4882a593Smuzhiyun static void snd_ca0106_pcm_free_substream(struct snd_pcm_runtime *runtime)
477*4882a593Smuzhiyun {
478*4882a593Smuzhiyun 	kfree(runtime->private_data);
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun static const int spi_dacd_reg[] = {
482*4882a593Smuzhiyun 	SPI_DACD0_REG,
483*4882a593Smuzhiyun 	SPI_DACD1_REG,
484*4882a593Smuzhiyun 	SPI_DACD2_REG,
485*4882a593Smuzhiyun 	0,
486*4882a593Smuzhiyun 	SPI_DACD4_REG,
487*4882a593Smuzhiyun };
488*4882a593Smuzhiyun static const int spi_dacd_bit[] = {
489*4882a593Smuzhiyun 	SPI_DACD0_BIT,
490*4882a593Smuzhiyun 	SPI_DACD1_BIT,
491*4882a593Smuzhiyun 	SPI_DACD2_BIT,
492*4882a593Smuzhiyun 	0,
493*4882a593Smuzhiyun 	SPI_DACD4_BIT,
494*4882a593Smuzhiyun };
495*4882a593Smuzhiyun 
restore_spdif_bits(struct snd_ca0106 * chip,int idx)496*4882a593Smuzhiyun static void restore_spdif_bits(struct snd_ca0106 *chip, int idx)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun 	if (chip->spdif_str_bits[idx] != chip->spdif_bits[idx]) {
499*4882a593Smuzhiyun 		chip->spdif_str_bits[idx] = chip->spdif_bits[idx];
500*4882a593Smuzhiyun 		snd_ca0106_ptr_write(chip, SPCS0 + idx, 0,
501*4882a593Smuzhiyun 				     chip->spdif_str_bits[idx]);
502*4882a593Smuzhiyun 	}
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun 
snd_ca0106_channel_dac(struct snd_ca0106 * chip,const struct snd_ca0106_details * details,int channel_id)505*4882a593Smuzhiyun static int snd_ca0106_channel_dac(struct snd_ca0106 *chip,
506*4882a593Smuzhiyun 				  const struct snd_ca0106_details *details,
507*4882a593Smuzhiyun 				  int channel_id)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun 	switch (channel_id) {
510*4882a593Smuzhiyun 	case PCM_FRONT_CHANNEL:
511*4882a593Smuzhiyun 		return (details->spi_dac & 0xf000) >> (4 * 3);
512*4882a593Smuzhiyun 	case PCM_REAR_CHANNEL:
513*4882a593Smuzhiyun 		return (details->spi_dac & 0x0f00) >> (4 * 2);
514*4882a593Smuzhiyun 	case PCM_CENTER_LFE_CHANNEL:
515*4882a593Smuzhiyun 		return (details->spi_dac & 0x00f0) >> (4 * 1);
516*4882a593Smuzhiyun 	case PCM_UNKNOWN_CHANNEL:
517*4882a593Smuzhiyun 		return (details->spi_dac & 0x000f) >> (4 * 0);
518*4882a593Smuzhiyun 	default:
519*4882a593Smuzhiyun 		dev_dbg(chip->card->dev, "ca0106: unknown channel_id %d\n",
520*4882a593Smuzhiyun 			   channel_id);
521*4882a593Smuzhiyun 	}
522*4882a593Smuzhiyun 	return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun 
snd_ca0106_pcm_power_dac(struct snd_ca0106 * chip,int channel_id,int power)525*4882a593Smuzhiyun static int snd_ca0106_pcm_power_dac(struct snd_ca0106 *chip, int channel_id,
526*4882a593Smuzhiyun 				    int power)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun 	if (chip->details->spi_dac) {
529*4882a593Smuzhiyun 		const int dac = snd_ca0106_channel_dac(chip, chip->details,
530*4882a593Smuzhiyun 						       channel_id);
531*4882a593Smuzhiyun 		const int reg = spi_dacd_reg[dac];
532*4882a593Smuzhiyun 		const int bit = spi_dacd_bit[dac];
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 		if (power)
535*4882a593Smuzhiyun 			/* Power up */
536*4882a593Smuzhiyun 			chip->spi_dac_reg[reg] &= ~bit;
537*4882a593Smuzhiyun 		else
538*4882a593Smuzhiyun 			/* Power down */
539*4882a593Smuzhiyun 			chip->spi_dac_reg[reg] |= bit;
540*4882a593Smuzhiyun 		if (snd_ca0106_spi_write(chip, chip->spi_dac_reg[reg]) != 0)
541*4882a593Smuzhiyun 			return -ENXIO;
542*4882a593Smuzhiyun 	}
543*4882a593Smuzhiyun 	return 0;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun /* open_playback callback */
snd_ca0106_pcm_open_playback_channel(struct snd_pcm_substream * substream,int channel_id)547*4882a593Smuzhiyun static int snd_ca0106_pcm_open_playback_channel(struct snd_pcm_substream *substream,
548*4882a593Smuzhiyun 						int channel_id)
549*4882a593Smuzhiyun {
550*4882a593Smuzhiyun 	struct snd_ca0106 *chip = snd_pcm_substream_chip(substream);
551*4882a593Smuzhiyun         struct snd_ca0106_channel *channel = &(chip->playback_channels[channel_id]);
552*4882a593Smuzhiyun 	struct snd_ca0106_pcm *epcm;
553*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
554*4882a593Smuzhiyun 	int err;
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	if (epcm == NULL)
559*4882a593Smuzhiyun 		return -ENOMEM;
560*4882a593Smuzhiyun 	epcm->emu = chip;
561*4882a593Smuzhiyun 	epcm->substream = substream;
562*4882a593Smuzhiyun         epcm->channel_id=channel_id;
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	runtime->private_data = epcm;
565*4882a593Smuzhiyun 	runtime->private_free = snd_ca0106_pcm_free_substream;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	runtime->hw = snd_ca0106_playback_hw;
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun         channel->emu = chip;
570*4882a593Smuzhiyun         channel->number = channel_id;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	channel->use = 1;
573*4882a593Smuzhiyun 	/*
574*4882a593Smuzhiyun 	dev_dbg(chip->card->dev, "open:channel_id=%d, chip=%p, channel=%p\n",
575*4882a593Smuzhiyun 	       channel_id, chip, channel);
576*4882a593Smuzhiyun 	*/
577*4882a593Smuzhiyun         //channel->interrupt = snd_ca0106_pcm_channel_interrupt;
578*4882a593Smuzhiyun 	channel->epcm = epcm;
579*4882a593Smuzhiyun 	if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
580*4882a593Smuzhiyun                 return err;
581*4882a593Smuzhiyun 	if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
582*4882a593Smuzhiyun                 return err;
583*4882a593Smuzhiyun 	snd_pcm_set_sync(substream);
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	/* Front channel dac should already be on */
586*4882a593Smuzhiyun 	if (channel_id != PCM_FRONT_CHANNEL) {
587*4882a593Smuzhiyun 		err = snd_ca0106_pcm_power_dac(chip, channel_id, 1);
588*4882a593Smuzhiyun 		if (err < 0)
589*4882a593Smuzhiyun 			return err;
590*4882a593Smuzhiyun 	}
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	restore_spdif_bits(chip, channel_id);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	return 0;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun /* close callback */
snd_ca0106_pcm_close_playback(struct snd_pcm_substream * substream)598*4882a593Smuzhiyun static int snd_ca0106_pcm_close_playback(struct snd_pcm_substream *substream)
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun 	struct snd_ca0106 *chip = snd_pcm_substream_chip(substream);
601*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
602*4882a593Smuzhiyun         struct snd_ca0106_pcm *epcm = runtime->private_data;
603*4882a593Smuzhiyun 	chip->playback_channels[epcm->channel_id].use = 0;
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 	restore_spdif_bits(chip, epcm->channel_id);
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	/* Front channel dac should stay on */
608*4882a593Smuzhiyun 	if (epcm->channel_id != PCM_FRONT_CHANNEL) {
609*4882a593Smuzhiyun 		int err;
610*4882a593Smuzhiyun 		err = snd_ca0106_pcm_power_dac(chip, epcm->channel_id, 0);
611*4882a593Smuzhiyun 		if (err < 0)
612*4882a593Smuzhiyun 			return err;
613*4882a593Smuzhiyun 	}
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	/* FIXME: maybe zero others */
616*4882a593Smuzhiyun 	return 0;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun 
snd_ca0106_pcm_open_playback_front(struct snd_pcm_substream * substream)619*4882a593Smuzhiyun static int snd_ca0106_pcm_open_playback_front(struct snd_pcm_substream *substream)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun 	return snd_ca0106_pcm_open_playback_channel(substream, PCM_FRONT_CHANNEL);
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun 
snd_ca0106_pcm_open_playback_center_lfe(struct snd_pcm_substream * substream)624*4882a593Smuzhiyun static int snd_ca0106_pcm_open_playback_center_lfe(struct snd_pcm_substream *substream)
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun 	return snd_ca0106_pcm_open_playback_channel(substream, PCM_CENTER_LFE_CHANNEL);
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun 
snd_ca0106_pcm_open_playback_unknown(struct snd_pcm_substream * substream)629*4882a593Smuzhiyun static int snd_ca0106_pcm_open_playback_unknown(struct snd_pcm_substream *substream)
630*4882a593Smuzhiyun {
631*4882a593Smuzhiyun 	return snd_ca0106_pcm_open_playback_channel(substream, PCM_UNKNOWN_CHANNEL);
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun 
snd_ca0106_pcm_open_playback_rear(struct snd_pcm_substream * substream)634*4882a593Smuzhiyun static int snd_ca0106_pcm_open_playback_rear(struct snd_pcm_substream *substream)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun 	return snd_ca0106_pcm_open_playback_channel(substream, PCM_REAR_CHANNEL);
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun /* open_capture callback */
snd_ca0106_pcm_open_capture_channel(struct snd_pcm_substream * substream,int channel_id)640*4882a593Smuzhiyun static int snd_ca0106_pcm_open_capture_channel(struct snd_pcm_substream *substream,
641*4882a593Smuzhiyun 					       int channel_id)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	struct snd_ca0106 *chip = snd_pcm_substream_chip(substream);
644*4882a593Smuzhiyun         struct snd_ca0106_channel *channel = &(chip->capture_channels[channel_id]);
645*4882a593Smuzhiyun 	struct snd_ca0106_pcm *epcm;
646*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
647*4882a593Smuzhiyun 	int err;
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
650*4882a593Smuzhiyun 	if (!epcm)
651*4882a593Smuzhiyun 		return -ENOMEM;
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	epcm->emu = chip;
654*4882a593Smuzhiyun 	epcm->substream = substream;
655*4882a593Smuzhiyun         epcm->channel_id=channel_id;
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun 	runtime->private_data = epcm;
658*4882a593Smuzhiyun 	runtime->private_free = snd_ca0106_pcm_free_substream;
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	runtime->hw = snd_ca0106_capture_hw;
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun         channel->emu = chip;
663*4882a593Smuzhiyun         channel->number = channel_id;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	channel->use = 1;
666*4882a593Smuzhiyun 	/*
667*4882a593Smuzhiyun 	dev_dbg(chip->card->dev, "open:channel_id=%d, chip=%p, channel=%p\n",
668*4882a593Smuzhiyun 	       channel_id, chip, channel);
669*4882a593Smuzhiyun 	*/
670*4882a593Smuzhiyun         //channel->interrupt = snd_ca0106_pcm_channel_interrupt;
671*4882a593Smuzhiyun         channel->epcm = epcm;
672*4882a593Smuzhiyun 	if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
673*4882a593Smuzhiyun                 return err;
674*4882a593Smuzhiyun 	//snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_capture_period_sizes);
675*4882a593Smuzhiyun 	if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
676*4882a593Smuzhiyun                 return err;
677*4882a593Smuzhiyun 	return 0;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun /* close callback */
snd_ca0106_pcm_close_capture(struct snd_pcm_substream * substream)681*4882a593Smuzhiyun static int snd_ca0106_pcm_close_capture(struct snd_pcm_substream *substream)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun 	struct snd_ca0106 *chip = snd_pcm_substream_chip(substream);
684*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
685*4882a593Smuzhiyun         struct snd_ca0106_pcm *epcm = runtime->private_data;
686*4882a593Smuzhiyun 	chip->capture_channels[epcm->channel_id].use = 0;
687*4882a593Smuzhiyun 	/* FIXME: maybe zero others */
688*4882a593Smuzhiyun 	return 0;
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun 
snd_ca0106_pcm_open_0_capture(struct snd_pcm_substream * substream)691*4882a593Smuzhiyun static int snd_ca0106_pcm_open_0_capture(struct snd_pcm_substream *substream)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun 	return snd_ca0106_pcm_open_capture_channel(substream, 0);
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun 
snd_ca0106_pcm_open_1_capture(struct snd_pcm_substream * substream)696*4882a593Smuzhiyun static int snd_ca0106_pcm_open_1_capture(struct snd_pcm_substream *substream)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun 	return snd_ca0106_pcm_open_capture_channel(substream, 1);
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun 
snd_ca0106_pcm_open_2_capture(struct snd_pcm_substream * substream)701*4882a593Smuzhiyun static int snd_ca0106_pcm_open_2_capture(struct snd_pcm_substream *substream)
702*4882a593Smuzhiyun {
703*4882a593Smuzhiyun 	return snd_ca0106_pcm_open_capture_channel(substream, 2);
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun 
snd_ca0106_pcm_open_3_capture(struct snd_pcm_substream * substream)706*4882a593Smuzhiyun static int snd_ca0106_pcm_open_3_capture(struct snd_pcm_substream *substream)
707*4882a593Smuzhiyun {
708*4882a593Smuzhiyun 	return snd_ca0106_pcm_open_capture_channel(substream, 3);
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun /* prepare playback callback */
snd_ca0106_pcm_prepare_playback(struct snd_pcm_substream * substream)712*4882a593Smuzhiyun static int snd_ca0106_pcm_prepare_playback(struct snd_pcm_substream *substream)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun 	struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
715*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
716*4882a593Smuzhiyun 	struct snd_ca0106_pcm *epcm = runtime->private_data;
717*4882a593Smuzhiyun 	int channel = epcm->channel_id;
718*4882a593Smuzhiyun 	u32 *table_base = (u32 *)(emu->buffer.area+(8*16*channel));
719*4882a593Smuzhiyun 	u32 period_size_bytes = frames_to_bytes(runtime, runtime->period_size);
720*4882a593Smuzhiyun 	u32 hcfg_mask = HCFG_PLAYBACK_S32_LE;
721*4882a593Smuzhiyun 	u32 hcfg_set = 0x00000000;
722*4882a593Smuzhiyun 	u32 hcfg;
723*4882a593Smuzhiyun 	u32 reg40_mask = 0x30000 << (channel<<1);
724*4882a593Smuzhiyun 	u32 reg40_set = 0;
725*4882a593Smuzhiyun 	u32 reg40;
726*4882a593Smuzhiyun 	/* FIXME: Depending on mixer selection of SPDIF out or not, select the spdif rate or the DAC rate. */
727*4882a593Smuzhiyun 	u32 reg71_mask = 0x03030000 ; /* Global. Set SPDIF rate. We only support 44100 to spdif, not to DAC. */
728*4882a593Smuzhiyun 	u32 reg71_set = 0;
729*4882a593Smuzhiyun 	u32 reg71;
730*4882a593Smuzhiyun 	int i;
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun #if 0 /* debug */
733*4882a593Smuzhiyun 	dev_dbg(emu->card->dev,
734*4882a593Smuzhiyun 		   "prepare:channel_number=%d, rate=%d, format=0x%x, "
735*4882a593Smuzhiyun 		   "channels=%d, buffer_size=%ld, period_size=%ld, "
736*4882a593Smuzhiyun 		   "periods=%u, frames_to_bytes=%d\n",
737*4882a593Smuzhiyun 		   channel, runtime->rate, runtime->format,
738*4882a593Smuzhiyun 		   runtime->channels, runtime->buffer_size,
739*4882a593Smuzhiyun 		   runtime->period_size, runtime->periods,
740*4882a593Smuzhiyun 		   frames_to_bytes(runtime, 1));
741*4882a593Smuzhiyun 	dev_dbg(emu->card->dev,
742*4882a593Smuzhiyun 		"dma_addr=%x, dma_area=%p, table_base=%p\n",
743*4882a593Smuzhiyun 		   runtime->dma_addr, runtime->dma_area, table_base);
744*4882a593Smuzhiyun 	dev_dbg(emu->card->dev,
745*4882a593Smuzhiyun 		"dma_addr=%x, dma_area=%p, dma_bytes(size)=%x\n",
746*4882a593Smuzhiyun 		   emu->buffer.addr, emu->buffer.area, emu->buffer.bytes);
747*4882a593Smuzhiyun #endif /* debug */
748*4882a593Smuzhiyun 	/* Rate can be set per channel. */
749*4882a593Smuzhiyun 	/* reg40 control host to fifo */
750*4882a593Smuzhiyun 	/* reg71 controls DAC rate. */
751*4882a593Smuzhiyun 	switch (runtime->rate) {
752*4882a593Smuzhiyun 	case 44100:
753*4882a593Smuzhiyun 		reg40_set = 0x10000 << (channel<<1);
754*4882a593Smuzhiyun 		reg71_set = 0x01010000;
755*4882a593Smuzhiyun 		break;
756*4882a593Smuzhiyun         case 48000:
757*4882a593Smuzhiyun 		reg40_set = 0;
758*4882a593Smuzhiyun 		reg71_set = 0;
759*4882a593Smuzhiyun 		break;
760*4882a593Smuzhiyun 	case 96000:
761*4882a593Smuzhiyun 		reg40_set = 0x20000 << (channel<<1);
762*4882a593Smuzhiyun 		reg71_set = 0x02020000;
763*4882a593Smuzhiyun 		break;
764*4882a593Smuzhiyun 	case 192000:
765*4882a593Smuzhiyun 		reg40_set = 0x30000 << (channel<<1);
766*4882a593Smuzhiyun 		reg71_set = 0x03030000;
767*4882a593Smuzhiyun 		break;
768*4882a593Smuzhiyun 	default:
769*4882a593Smuzhiyun 		reg40_set = 0;
770*4882a593Smuzhiyun 		reg71_set = 0;
771*4882a593Smuzhiyun 		break;
772*4882a593Smuzhiyun 	}
773*4882a593Smuzhiyun 	/* Format is a global setting */
774*4882a593Smuzhiyun 	/* FIXME: Only let the first channel accessed set this. */
775*4882a593Smuzhiyun 	switch (runtime->format) {
776*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S16_LE:
777*4882a593Smuzhiyun 		hcfg_set = 0;
778*4882a593Smuzhiyun 		break;
779*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S32_LE:
780*4882a593Smuzhiyun 		hcfg_set = HCFG_PLAYBACK_S32_LE;
781*4882a593Smuzhiyun 		break;
782*4882a593Smuzhiyun 	default:
783*4882a593Smuzhiyun 		hcfg_set = 0;
784*4882a593Smuzhiyun 		break;
785*4882a593Smuzhiyun 	}
786*4882a593Smuzhiyun 	hcfg = inl(emu->port + HCFG) ;
787*4882a593Smuzhiyun 	hcfg = (hcfg & ~hcfg_mask) | hcfg_set;
788*4882a593Smuzhiyun 	outl(hcfg, emu->port + HCFG);
789*4882a593Smuzhiyun 	reg40 = snd_ca0106_ptr_read(emu, 0x40, 0);
790*4882a593Smuzhiyun 	reg40 = (reg40 & ~reg40_mask) | reg40_set;
791*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, 0x40, 0, reg40);
792*4882a593Smuzhiyun 	reg71 = snd_ca0106_ptr_read(emu, 0x71, 0);
793*4882a593Smuzhiyun 	reg71 = (reg71 & ~reg71_mask) | reg71_set;
794*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, 0x71, 0, reg71);
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun 	/* FIXME: Check emu->buffer.size before actually writing to it. */
797*4882a593Smuzhiyun         for(i=0; i < runtime->periods; i++) {
798*4882a593Smuzhiyun 		table_base[i*2] = runtime->dma_addr + (i * period_size_bytes);
799*4882a593Smuzhiyun 		table_base[i*2+1] = period_size_bytes << 16;
800*4882a593Smuzhiyun 	}
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, PLAYBACK_LIST_ADDR, channel, emu->buffer.addr+(8*16*channel));
803*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, PLAYBACK_LIST_SIZE, channel, (runtime->periods - 1) << 19);
804*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, PLAYBACK_LIST_PTR, channel, 0);
805*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, PLAYBACK_DMA_ADDR, channel, runtime->dma_addr);
806*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, PLAYBACK_PERIOD_SIZE, channel, frames_to_bytes(runtime, runtime->period_size)<<16); // buffer size in bytes
807*4882a593Smuzhiyun 	/* FIXME  test what 0 bytes does. */
808*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, PLAYBACK_PERIOD_SIZE, channel, 0); // buffer size in bytes
809*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, PLAYBACK_POINTER, channel, 0);
810*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, 0x07, channel, 0x0);
811*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, 0x08, channel, 0);
812*4882a593Smuzhiyun         snd_ca0106_ptr_write(emu, PLAYBACK_MUTE, 0x0, 0x0); /* Unmute output */
813*4882a593Smuzhiyun #if 0
814*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, SPCS0, 0,
815*4882a593Smuzhiyun 			       SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
816*4882a593Smuzhiyun 			       SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
817*4882a593Smuzhiyun 			       SPCS_GENERATIONSTATUS | 0x00001200 |
818*4882a593Smuzhiyun 			       0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT );
819*4882a593Smuzhiyun #endif
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun 	return 0;
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun /* prepare capture callback */
snd_ca0106_pcm_prepare_capture(struct snd_pcm_substream * substream)825*4882a593Smuzhiyun static int snd_ca0106_pcm_prepare_capture(struct snd_pcm_substream *substream)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun 	struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
828*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
829*4882a593Smuzhiyun 	struct snd_ca0106_pcm *epcm = runtime->private_data;
830*4882a593Smuzhiyun 	int channel = epcm->channel_id;
831*4882a593Smuzhiyun 	u32 hcfg_mask = HCFG_CAPTURE_S32_LE;
832*4882a593Smuzhiyun 	u32 hcfg_set = 0x00000000;
833*4882a593Smuzhiyun 	u32 hcfg;
834*4882a593Smuzhiyun 	u32 over_sampling=0x2;
835*4882a593Smuzhiyun 	u32 reg71_mask = 0x0000c000 ; /* Global. Set ADC rate. */
836*4882a593Smuzhiyun 	u32 reg71_set = 0;
837*4882a593Smuzhiyun 	u32 reg71;
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun #if 0 /* debug */
840*4882a593Smuzhiyun 	dev_dbg(emu->card->dev,
841*4882a593Smuzhiyun 		   "prepare:channel_number=%d, rate=%d, format=0x%x, "
842*4882a593Smuzhiyun 		   "channels=%d, buffer_size=%ld, period_size=%ld, "
843*4882a593Smuzhiyun 		   "periods=%u, frames_to_bytes=%d\n",
844*4882a593Smuzhiyun 		   channel, runtime->rate, runtime->format,
845*4882a593Smuzhiyun 		   runtime->channels, runtime->buffer_size,
846*4882a593Smuzhiyun 		   runtime->period_size, runtime->periods,
847*4882a593Smuzhiyun 		   frames_to_bytes(runtime, 1));
848*4882a593Smuzhiyun 	dev_dbg(emu->card->dev,
849*4882a593Smuzhiyun 		"dma_addr=%x, dma_area=%p, table_base=%p\n",
850*4882a593Smuzhiyun 		   runtime->dma_addr, runtime->dma_area, table_base);
851*4882a593Smuzhiyun 	dev_dbg(emu->card->dev,
852*4882a593Smuzhiyun 		"dma_addr=%x, dma_area=%p, dma_bytes(size)=%x\n",
853*4882a593Smuzhiyun 		   emu->buffer.addr, emu->buffer.area, emu->buffer.bytes);
854*4882a593Smuzhiyun #endif /* debug */
855*4882a593Smuzhiyun 	/* reg71 controls ADC rate. */
856*4882a593Smuzhiyun 	switch (runtime->rate) {
857*4882a593Smuzhiyun 	case 44100:
858*4882a593Smuzhiyun 		reg71_set = 0x00004000;
859*4882a593Smuzhiyun 		break;
860*4882a593Smuzhiyun         case 48000:
861*4882a593Smuzhiyun 		reg71_set = 0;
862*4882a593Smuzhiyun 		break;
863*4882a593Smuzhiyun 	case 96000:
864*4882a593Smuzhiyun 		reg71_set = 0x00008000;
865*4882a593Smuzhiyun 		over_sampling=0xa;
866*4882a593Smuzhiyun 		break;
867*4882a593Smuzhiyun 	case 192000:
868*4882a593Smuzhiyun 		reg71_set = 0x0000c000;
869*4882a593Smuzhiyun 		over_sampling=0xa;
870*4882a593Smuzhiyun 		break;
871*4882a593Smuzhiyun 	default:
872*4882a593Smuzhiyun 		reg71_set = 0;
873*4882a593Smuzhiyun 		break;
874*4882a593Smuzhiyun 	}
875*4882a593Smuzhiyun 	/* Format is a global setting */
876*4882a593Smuzhiyun 	/* FIXME: Only let the first channel accessed set this. */
877*4882a593Smuzhiyun 	switch (runtime->format) {
878*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S16_LE:
879*4882a593Smuzhiyun 		hcfg_set = 0;
880*4882a593Smuzhiyun 		break;
881*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S32_LE:
882*4882a593Smuzhiyun 		hcfg_set = HCFG_CAPTURE_S32_LE;
883*4882a593Smuzhiyun 		break;
884*4882a593Smuzhiyun 	default:
885*4882a593Smuzhiyun 		hcfg_set = 0;
886*4882a593Smuzhiyun 		break;
887*4882a593Smuzhiyun 	}
888*4882a593Smuzhiyun 	hcfg = inl(emu->port + HCFG) ;
889*4882a593Smuzhiyun 	hcfg = (hcfg & ~hcfg_mask) | hcfg_set;
890*4882a593Smuzhiyun 	outl(hcfg, emu->port + HCFG);
891*4882a593Smuzhiyun 	reg71 = snd_ca0106_ptr_read(emu, 0x71, 0);
892*4882a593Smuzhiyun 	reg71 = (reg71 & ~reg71_mask) | reg71_set;
893*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, 0x71, 0, reg71);
894*4882a593Smuzhiyun         if (emu->details->i2c_adc == 1) { /* The SB0410 and SB0413 use I2C to control ADC. */
895*4882a593Smuzhiyun 	        snd_ca0106_i2c_write(emu, ADC_MASTER, over_sampling); /* Adjust the over sampler to better suit the capture rate. */
896*4882a593Smuzhiyun 	}
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun 
899*4882a593Smuzhiyun 	/*
900*4882a593Smuzhiyun 	dev_dbg(emu->card->dev,
901*4882a593Smuzhiyun 	       "prepare:channel_number=%d, rate=%d, format=0x%x, channels=%d, "
902*4882a593Smuzhiyun 	       "buffer_size=%ld, period_size=%ld, frames_to_bytes=%d\n",
903*4882a593Smuzhiyun 	       channel, runtime->rate, runtime->format, runtime->channels,
904*4882a593Smuzhiyun 	       runtime->buffer_size, runtime->period_size,
905*4882a593Smuzhiyun 	       frames_to_bytes(runtime, 1));
906*4882a593Smuzhiyun 	*/
907*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, 0x13, channel, 0);
908*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, CAPTURE_DMA_ADDR, channel, runtime->dma_addr);
909*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, CAPTURE_BUFFER_SIZE, channel, frames_to_bytes(runtime, runtime->buffer_size)<<16); // buffer size in bytes
910*4882a593Smuzhiyun 	snd_ca0106_ptr_write(emu, CAPTURE_POINTER, channel, 0);
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	return 0;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun 
915*4882a593Smuzhiyun /* trigger_playback callback */
snd_ca0106_pcm_trigger_playback(struct snd_pcm_substream * substream,int cmd)916*4882a593Smuzhiyun static int snd_ca0106_pcm_trigger_playback(struct snd_pcm_substream *substream,
917*4882a593Smuzhiyun 				    int cmd)
918*4882a593Smuzhiyun {
919*4882a593Smuzhiyun 	struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
920*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime;
921*4882a593Smuzhiyun 	struct snd_ca0106_pcm *epcm;
922*4882a593Smuzhiyun 	int channel;
923*4882a593Smuzhiyun 	int result = 0;
924*4882a593Smuzhiyun         struct snd_pcm_substream *s;
925*4882a593Smuzhiyun 	u32 basic = 0;
926*4882a593Smuzhiyun 	u32 extended = 0;
927*4882a593Smuzhiyun 	u32 bits;
928*4882a593Smuzhiyun 	int running = 0;
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun 	switch (cmd) {
931*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
932*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_RESUME:
933*4882a593Smuzhiyun 		running = 1;
934*4882a593Smuzhiyun 		break;
935*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
936*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_SUSPEND:
937*4882a593Smuzhiyun 	default:
938*4882a593Smuzhiyun 		running = 0;
939*4882a593Smuzhiyun 		break;
940*4882a593Smuzhiyun 	}
941*4882a593Smuzhiyun         snd_pcm_group_for_each_entry(s, substream) {
942*4882a593Smuzhiyun 		if (snd_pcm_substream_chip(s) != emu ||
943*4882a593Smuzhiyun 		    s->stream != SNDRV_PCM_STREAM_PLAYBACK)
944*4882a593Smuzhiyun 			continue;
945*4882a593Smuzhiyun 		runtime = s->runtime;
946*4882a593Smuzhiyun 		epcm = runtime->private_data;
947*4882a593Smuzhiyun 		channel = epcm->channel_id;
948*4882a593Smuzhiyun 		/* dev_dbg(emu->card->dev, "channel=%d\n", channel); */
949*4882a593Smuzhiyun 		epcm->running = running;
950*4882a593Smuzhiyun 		basic |= (0x1 << channel);
951*4882a593Smuzhiyun 		extended |= (0x10 << channel);
952*4882a593Smuzhiyun                 snd_pcm_trigger_done(s, substream);
953*4882a593Smuzhiyun         }
954*4882a593Smuzhiyun 	/* dev_dbg(emu->card->dev, "basic=0x%x, extended=0x%x\n",basic, extended); */
955*4882a593Smuzhiyun 
956*4882a593Smuzhiyun 	switch (cmd) {
957*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
958*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_RESUME:
959*4882a593Smuzhiyun 		bits = snd_ca0106_ptr_read(emu, EXTENDED_INT_MASK, 0);
960*4882a593Smuzhiyun 		bits |= extended;
961*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, EXTENDED_INT_MASK, 0, bits);
962*4882a593Smuzhiyun 		bits = snd_ca0106_ptr_read(emu, BASIC_INTERRUPT, 0);
963*4882a593Smuzhiyun 		bits |= basic;
964*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, BASIC_INTERRUPT, 0, bits);
965*4882a593Smuzhiyun 		break;
966*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
967*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_SUSPEND:
968*4882a593Smuzhiyun 		bits = snd_ca0106_ptr_read(emu, BASIC_INTERRUPT, 0);
969*4882a593Smuzhiyun 		bits &= ~basic;
970*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, BASIC_INTERRUPT, 0, bits);
971*4882a593Smuzhiyun 		bits = snd_ca0106_ptr_read(emu, EXTENDED_INT_MASK, 0);
972*4882a593Smuzhiyun 		bits &= ~extended;
973*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, EXTENDED_INT_MASK, 0, bits);
974*4882a593Smuzhiyun 		break;
975*4882a593Smuzhiyun 	default:
976*4882a593Smuzhiyun 		result = -EINVAL;
977*4882a593Smuzhiyun 		break;
978*4882a593Smuzhiyun 	}
979*4882a593Smuzhiyun 	return result;
980*4882a593Smuzhiyun }
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun /* trigger_capture callback */
snd_ca0106_pcm_trigger_capture(struct snd_pcm_substream * substream,int cmd)983*4882a593Smuzhiyun static int snd_ca0106_pcm_trigger_capture(struct snd_pcm_substream *substream,
984*4882a593Smuzhiyun 				    int cmd)
985*4882a593Smuzhiyun {
986*4882a593Smuzhiyun 	struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
987*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
988*4882a593Smuzhiyun 	struct snd_ca0106_pcm *epcm = runtime->private_data;
989*4882a593Smuzhiyun 	int channel = epcm->channel_id;
990*4882a593Smuzhiyun 	int result = 0;
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	switch (cmd) {
993*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
994*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, EXTENDED_INT_MASK, 0, snd_ca0106_ptr_read(emu, EXTENDED_INT_MASK, 0) | (0x110000<<channel));
995*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, BASIC_INTERRUPT, 0, snd_ca0106_ptr_read(emu, BASIC_INTERRUPT, 0)|(0x100<<channel));
996*4882a593Smuzhiyun 		epcm->running = 1;
997*4882a593Smuzhiyun 		break;
998*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
999*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, BASIC_INTERRUPT, 0, snd_ca0106_ptr_read(emu, BASIC_INTERRUPT, 0) & ~(0x100<<channel));
1000*4882a593Smuzhiyun 		snd_ca0106_ptr_write(emu, EXTENDED_INT_MASK, 0, snd_ca0106_ptr_read(emu, EXTENDED_INT_MASK, 0) & ~(0x110000<<channel));
1001*4882a593Smuzhiyun 		epcm->running = 0;
1002*4882a593Smuzhiyun 		break;
1003*4882a593Smuzhiyun 	default:
1004*4882a593Smuzhiyun 		result = -EINVAL;
1005*4882a593Smuzhiyun 		break;
1006*4882a593Smuzhiyun 	}
1007*4882a593Smuzhiyun 	return result;
1008*4882a593Smuzhiyun }
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun /* pointer_playback callback */
1011*4882a593Smuzhiyun static snd_pcm_uframes_t
snd_ca0106_pcm_pointer_playback(struct snd_pcm_substream * substream)1012*4882a593Smuzhiyun snd_ca0106_pcm_pointer_playback(struct snd_pcm_substream *substream)
1013*4882a593Smuzhiyun {
1014*4882a593Smuzhiyun 	struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
1015*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
1016*4882a593Smuzhiyun 	struct snd_ca0106_pcm *epcm = runtime->private_data;
1017*4882a593Smuzhiyun 	unsigned int ptr, prev_ptr;
1018*4882a593Smuzhiyun 	int channel = epcm->channel_id;
1019*4882a593Smuzhiyun 	int timeout = 10;
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun 	if (!epcm->running)
1022*4882a593Smuzhiyun 		return 0;
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	prev_ptr = -1;
1025*4882a593Smuzhiyun 	do {
1026*4882a593Smuzhiyun 		ptr = snd_ca0106_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
1027*4882a593Smuzhiyun 		ptr = (ptr >> 3) * runtime->period_size;
1028*4882a593Smuzhiyun 		ptr += bytes_to_frames(runtime,
1029*4882a593Smuzhiyun 			snd_ca0106_ptr_read(emu, PLAYBACK_POINTER, channel));
1030*4882a593Smuzhiyun 		if (ptr >= runtime->buffer_size)
1031*4882a593Smuzhiyun 			ptr -= runtime->buffer_size;
1032*4882a593Smuzhiyun 		if (prev_ptr == ptr)
1033*4882a593Smuzhiyun 			return ptr;
1034*4882a593Smuzhiyun 		prev_ptr = ptr;
1035*4882a593Smuzhiyun 	} while (--timeout);
1036*4882a593Smuzhiyun 	dev_warn(emu->card->dev, "ca0106: unstable DMA pointer!\n");
1037*4882a593Smuzhiyun 	return 0;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun /* pointer_capture callback */
1041*4882a593Smuzhiyun static snd_pcm_uframes_t
snd_ca0106_pcm_pointer_capture(struct snd_pcm_substream * substream)1042*4882a593Smuzhiyun snd_ca0106_pcm_pointer_capture(struct snd_pcm_substream *substream)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun 	struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
1045*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
1046*4882a593Smuzhiyun 	struct snd_ca0106_pcm *epcm = runtime->private_data;
1047*4882a593Smuzhiyun 	snd_pcm_uframes_t ptr, ptr1, ptr2 = 0;
1048*4882a593Smuzhiyun 	int channel = epcm->channel_id;
1049*4882a593Smuzhiyun 
1050*4882a593Smuzhiyun 	if (!epcm->running)
1051*4882a593Smuzhiyun 		return 0;
1052*4882a593Smuzhiyun 
1053*4882a593Smuzhiyun 	ptr1 = snd_ca0106_ptr_read(emu, CAPTURE_POINTER, channel);
1054*4882a593Smuzhiyun 	ptr2 = bytes_to_frames(runtime, ptr1);
1055*4882a593Smuzhiyun 	ptr=ptr2;
1056*4882a593Smuzhiyun         if (ptr >= runtime->buffer_size)
1057*4882a593Smuzhiyun 		ptr -= runtime->buffer_size;
1058*4882a593Smuzhiyun 	/*
1059*4882a593Smuzhiyun 	dev_dbg(emu->card->dev, "ptr1 = 0x%lx, ptr2=0x%lx, ptr=0x%lx, "
1060*4882a593Smuzhiyun 	       "buffer_size = 0x%x, period_size = 0x%x, bits=%d, rate=%d\n",
1061*4882a593Smuzhiyun 	       ptr1, ptr2, ptr, (int)runtime->buffer_size,
1062*4882a593Smuzhiyun 	       (int)runtime->period_size, (int)runtime->frame_bits,
1063*4882a593Smuzhiyun 	       (int)runtime->rate);
1064*4882a593Smuzhiyun 	*/
1065*4882a593Smuzhiyun 	return ptr;
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun /* operators */
1069*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ca0106_playback_front_ops = {
1070*4882a593Smuzhiyun 	.open =        snd_ca0106_pcm_open_playback_front,
1071*4882a593Smuzhiyun 	.close =       snd_ca0106_pcm_close_playback,
1072*4882a593Smuzhiyun 	.prepare =     snd_ca0106_pcm_prepare_playback,
1073*4882a593Smuzhiyun 	.trigger =     snd_ca0106_pcm_trigger_playback,
1074*4882a593Smuzhiyun 	.pointer =     snd_ca0106_pcm_pointer_playback,
1075*4882a593Smuzhiyun };
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ca0106_capture_0_ops = {
1078*4882a593Smuzhiyun 	.open =        snd_ca0106_pcm_open_0_capture,
1079*4882a593Smuzhiyun 	.close =       snd_ca0106_pcm_close_capture,
1080*4882a593Smuzhiyun 	.prepare =     snd_ca0106_pcm_prepare_capture,
1081*4882a593Smuzhiyun 	.trigger =     snd_ca0106_pcm_trigger_capture,
1082*4882a593Smuzhiyun 	.pointer =     snd_ca0106_pcm_pointer_capture,
1083*4882a593Smuzhiyun };
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ca0106_capture_1_ops = {
1086*4882a593Smuzhiyun 	.open =        snd_ca0106_pcm_open_1_capture,
1087*4882a593Smuzhiyun 	.close =       snd_ca0106_pcm_close_capture,
1088*4882a593Smuzhiyun 	.prepare =     snd_ca0106_pcm_prepare_capture,
1089*4882a593Smuzhiyun 	.trigger =     snd_ca0106_pcm_trigger_capture,
1090*4882a593Smuzhiyun 	.pointer =     snd_ca0106_pcm_pointer_capture,
1091*4882a593Smuzhiyun };
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ca0106_capture_2_ops = {
1094*4882a593Smuzhiyun 	.open =        snd_ca0106_pcm_open_2_capture,
1095*4882a593Smuzhiyun 	.close =       snd_ca0106_pcm_close_capture,
1096*4882a593Smuzhiyun 	.prepare =     snd_ca0106_pcm_prepare_capture,
1097*4882a593Smuzhiyun 	.trigger =     snd_ca0106_pcm_trigger_capture,
1098*4882a593Smuzhiyun 	.pointer =     snd_ca0106_pcm_pointer_capture,
1099*4882a593Smuzhiyun };
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ca0106_capture_3_ops = {
1102*4882a593Smuzhiyun 	.open =        snd_ca0106_pcm_open_3_capture,
1103*4882a593Smuzhiyun 	.close =       snd_ca0106_pcm_close_capture,
1104*4882a593Smuzhiyun 	.prepare =     snd_ca0106_pcm_prepare_capture,
1105*4882a593Smuzhiyun 	.trigger =     snd_ca0106_pcm_trigger_capture,
1106*4882a593Smuzhiyun 	.pointer =     snd_ca0106_pcm_pointer_capture,
1107*4882a593Smuzhiyun };
1108*4882a593Smuzhiyun 
1109*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ca0106_playback_center_lfe_ops = {
1110*4882a593Smuzhiyun         .open =         snd_ca0106_pcm_open_playback_center_lfe,
1111*4882a593Smuzhiyun         .close =        snd_ca0106_pcm_close_playback,
1112*4882a593Smuzhiyun         .prepare =      snd_ca0106_pcm_prepare_playback,
1113*4882a593Smuzhiyun         .trigger =      snd_ca0106_pcm_trigger_playback,
1114*4882a593Smuzhiyun         .pointer =      snd_ca0106_pcm_pointer_playback,
1115*4882a593Smuzhiyun };
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ca0106_playback_unknown_ops = {
1118*4882a593Smuzhiyun         .open =         snd_ca0106_pcm_open_playback_unknown,
1119*4882a593Smuzhiyun         .close =        snd_ca0106_pcm_close_playback,
1120*4882a593Smuzhiyun         .prepare =      snd_ca0106_pcm_prepare_playback,
1121*4882a593Smuzhiyun         .trigger =      snd_ca0106_pcm_trigger_playback,
1122*4882a593Smuzhiyun         .pointer =      snd_ca0106_pcm_pointer_playback,
1123*4882a593Smuzhiyun };
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ca0106_playback_rear_ops = {
1126*4882a593Smuzhiyun         .open =         snd_ca0106_pcm_open_playback_rear,
1127*4882a593Smuzhiyun         .close =        snd_ca0106_pcm_close_playback,
1128*4882a593Smuzhiyun         .prepare =      snd_ca0106_pcm_prepare_playback,
1129*4882a593Smuzhiyun         .trigger =      snd_ca0106_pcm_trigger_playback,
1130*4882a593Smuzhiyun         .pointer =      snd_ca0106_pcm_pointer_playback,
1131*4882a593Smuzhiyun };
1132*4882a593Smuzhiyun 
1133*4882a593Smuzhiyun 
snd_ca0106_ac97_read(struct snd_ac97 * ac97,unsigned short reg)1134*4882a593Smuzhiyun static unsigned short snd_ca0106_ac97_read(struct snd_ac97 *ac97,
1135*4882a593Smuzhiyun 					     unsigned short reg)
1136*4882a593Smuzhiyun {
1137*4882a593Smuzhiyun 	struct snd_ca0106 *emu = ac97->private_data;
1138*4882a593Smuzhiyun 	unsigned long flags;
1139*4882a593Smuzhiyun 	unsigned short val;
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	spin_lock_irqsave(&emu->emu_lock, flags);
1142*4882a593Smuzhiyun 	outb(reg, emu->port + AC97ADDRESS);
1143*4882a593Smuzhiyun 	val = inw(emu->port + AC97DATA);
1144*4882a593Smuzhiyun 	spin_unlock_irqrestore(&emu->emu_lock, flags);
1145*4882a593Smuzhiyun 	return val;
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun 
snd_ca0106_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)1148*4882a593Smuzhiyun static void snd_ca0106_ac97_write(struct snd_ac97 *ac97,
1149*4882a593Smuzhiyun 				    unsigned short reg, unsigned short val)
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun 	struct snd_ca0106 *emu = ac97->private_data;
1152*4882a593Smuzhiyun 	unsigned long flags;
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun 	spin_lock_irqsave(&emu->emu_lock, flags);
1155*4882a593Smuzhiyun 	outb(reg, emu->port + AC97ADDRESS);
1156*4882a593Smuzhiyun 	outw(val, emu->port + AC97DATA);
1157*4882a593Smuzhiyun 	spin_unlock_irqrestore(&emu->emu_lock, flags);
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun 
snd_ca0106_ac97(struct snd_ca0106 * chip)1160*4882a593Smuzhiyun static int snd_ca0106_ac97(struct snd_ca0106 *chip)
1161*4882a593Smuzhiyun {
1162*4882a593Smuzhiyun 	struct snd_ac97_bus *pbus;
1163*4882a593Smuzhiyun 	struct snd_ac97_template ac97;
1164*4882a593Smuzhiyun 	int err;
1165*4882a593Smuzhiyun 	static const struct snd_ac97_bus_ops ops = {
1166*4882a593Smuzhiyun 		.write = snd_ca0106_ac97_write,
1167*4882a593Smuzhiyun 		.read = snd_ca0106_ac97_read,
1168*4882a593Smuzhiyun 	};
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1171*4882a593Smuzhiyun 		return err;
1172*4882a593Smuzhiyun 	pbus->no_vra = 1; /* we don't need VRA */
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun 	memset(&ac97, 0, sizeof(ac97));
1175*4882a593Smuzhiyun 	ac97.private_data = chip;
1176*4882a593Smuzhiyun 	ac97.scaps = AC97_SCAP_NO_SPDIF;
1177*4882a593Smuzhiyun 	return snd_ac97_mixer(pbus, &ac97, &chip->ac97);
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun static void ca0106_stop_chip(struct snd_ca0106 *chip);
1181*4882a593Smuzhiyun 
snd_ca0106_free(struct snd_ca0106 * chip)1182*4882a593Smuzhiyun static int snd_ca0106_free(struct snd_ca0106 *chip)
1183*4882a593Smuzhiyun {
1184*4882a593Smuzhiyun 	if (chip->res_port != NULL) {
1185*4882a593Smuzhiyun 		/* avoid access to already used hardware */
1186*4882a593Smuzhiyun 		ca0106_stop_chip(chip);
1187*4882a593Smuzhiyun 	}
1188*4882a593Smuzhiyun 	if (chip->irq >= 0)
1189*4882a593Smuzhiyun 		free_irq(chip->irq, chip);
1190*4882a593Smuzhiyun 	// release the data
1191*4882a593Smuzhiyun #if 1
1192*4882a593Smuzhiyun 	if (chip->buffer.area)
1193*4882a593Smuzhiyun 		snd_dma_free_pages(&chip->buffer);
1194*4882a593Smuzhiyun #endif
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun 	// release the i/o port
1197*4882a593Smuzhiyun 	release_and_free_resource(chip->res_port);
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun 	pci_disable_device(chip->pci);
1200*4882a593Smuzhiyun 	kfree(chip);
1201*4882a593Smuzhiyun 	return 0;
1202*4882a593Smuzhiyun }
1203*4882a593Smuzhiyun 
snd_ca0106_dev_free(struct snd_device * device)1204*4882a593Smuzhiyun static int snd_ca0106_dev_free(struct snd_device *device)
1205*4882a593Smuzhiyun {
1206*4882a593Smuzhiyun 	struct snd_ca0106 *chip = device->device_data;
1207*4882a593Smuzhiyun 	return snd_ca0106_free(chip);
1208*4882a593Smuzhiyun }
1209*4882a593Smuzhiyun 
snd_ca0106_interrupt(int irq,void * dev_id)1210*4882a593Smuzhiyun static irqreturn_t snd_ca0106_interrupt(int irq, void *dev_id)
1211*4882a593Smuzhiyun {
1212*4882a593Smuzhiyun 	unsigned int status;
1213*4882a593Smuzhiyun 
1214*4882a593Smuzhiyun 	struct snd_ca0106 *chip = dev_id;
1215*4882a593Smuzhiyun 	int i;
1216*4882a593Smuzhiyun 	int mask;
1217*4882a593Smuzhiyun         unsigned int stat76;
1218*4882a593Smuzhiyun 	struct snd_ca0106_channel *pchannel;
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun 	status = inl(chip->port + IPR);
1221*4882a593Smuzhiyun 	if (! status)
1222*4882a593Smuzhiyun 		return IRQ_NONE;
1223*4882a593Smuzhiyun 
1224*4882a593Smuzhiyun         stat76 = snd_ca0106_ptr_read(chip, EXTENDED_INT, 0);
1225*4882a593Smuzhiyun 	/*
1226*4882a593Smuzhiyun 	dev_dbg(emu->card->dev, "interrupt status = 0x%08x, stat76=0x%08x\n",
1227*4882a593Smuzhiyun 		   status, stat76);
1228*4882a593Smuzhiyun 	dev_dbg(emu->card->dev, "ptr=0x%08x\n",
1229*4882a593Smuzhiyun 		   snd_ca0106_ptr_read(chip, PLAYBACK_POINTER, 0));
1230*4882a593Smuzhiyun 	*/
1231*4882a593Smuzhiyun         mask = 0x11; /* 0x1 for one half, 0x10 for the other half period. */
1232*4882a593Smuzhiyun 	for(i = 0; i < 4; i++) {
1233*4882a593Smuzhiyun 		pchannel = &(chip->playback_channels[i]);
1234*4882a593Smuzhiyun 		if (stat76 & mask) {
1235*4882a593Smuzhiyun /* FIXME: Select the correct substream for period elapsed */
1236*4882a593Smuzhiyun 			if(pchannel->use) {
1237*4882a593Smuzhiyun 				snd_pcm_period_elapsed(pchannel->epcm->substream);
1238*4882a593Smuzhiyun 				/* dev_dbg(emu->card->dev, "interrupt [%d] used\n", i); */
1239*4882a593Smuzhiyun                         }
1240*4882a593Smuzhiyun 		}
1241*4882a593Smuzhiyun 		/*
1242*4882a593Smuzhiyun 		dev_dbg(emu->card->dev, "channel=%p\n", pchannel);
1243*4882a593Smuzhiyun 		dev_dbg(emu->card->dev, "interrupt stat76[%d] = %08x, use=%d, channel=%d\n", i, stat76, pchannel->use, pchannel->number);
1244*4882a593Smuzhiyun 		*/
1245*4882a593Smuzhiyun 		mask <<= 1;
1246*4882a593Smuzhiyun 	}
1247*4882a593Smuzhiyun         mask = 0x110000; /* 0x1 for one half, 0x10 for the other half period. */
1248*4882a593Smuzhiyun 	for(i = 0; i < 4; i++) {
1249*4882a593Smuzhiyun 		pchannel = &(chip->capture_channels[i]);
1250*4882a593Smuzhiyun 		if (stat76 & mask) {
1251*4882a593Smuzhiyun /* FIXME: Select the correct substream for period elapsed */
1252*4882a593Smuzhiyun 			if(pchannel->use) {
1253*4882a593Smuzhiyun 				snd_pcm_period_elapsed(pchannel->epcm->substream);
1254*4882a593Smuzhiyun 				/* dev_dbg(emu->card->dev, "interrupt [%d] used\n", i); */
1255*4882a593Smuzhiyun                         }
1256*4882a593Smuzhiyun 		}
1257*4882a593Smuzhiyun 		/*
1258*4882a593Smuzhiyun 		dev_dbg(emu->card->dev, "channel=%p\n", pchannel);
1259*4882a593Smuzhiyun 		dev_dbg(emu->card->dev, "interrupt stat76[%d] = %08x, use=%d, channel=%d\n", i, stat76, pchannel->use, pchannel->number);
1260*4882a593Smuzhiyun 		*/
1261*4882a593Smuzhiyun 		mask <<= 1;
1262*4882a593Smuzhiyun 	}
1263*4882a593Smuzhiyun 
1264*4882a593Smuzhiyun         snd_ca0106_ptr_write(chip, EXTENDED_INT, 0, stat76);
1265*4882a593Smuzhiyun 
1266*4882a593Smuzhiyun 	if (chip->midi.dev_id &&
1267*4882a593Smuzhiyun 	    (status & (chip->midi.ipr_tx|chip->midi.ipr_rx))) {
1268*4882a593Smuzhiyun 		if (chip->midi.interrupt)
1269*4882a593Smuzhiyun 			chip->midi.interrupt(&chip->midi, status);
1270*4882a593Smuzhiyun 		else
1271*4882a593Smuzhiyun 			chip->midi.interrupt_disable(&chip->midi, chip->midi.tx_enable | chip->midi.rx_enable);
1272*4882a593Smuzhiyun 	}
1273*4882a593Smuzhiyun 
1274*4882a593Smuzhiyun 	// acknowledge the interrupt if necessary
1275*4882a593Smuzhiyun 	outl(status, chip->port+IPR);
1276*4882a593Smuzhiyun 
1277*4882a593Smuzhiyun 	return IRQ_HANDLED;
1278*4882a593Smuzhiyun }
1279*4882a593Smuzhiyun 
1280*4882a593Smuzhiyun static const struct snd_pcm_chmap_elem surround_map[] = {
1281*4882a593Smuzhiyun 	{ .channels = 2,
1282*4882a593Smuzhiyun 	  .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1283*4882a593Smuzhiyun 	{ }
1284*4882a593Smuzhiyun };
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun static const struct snd_pcm_chmap_elem clfe_map[] = {
1287*4882a593Smuzhiyun 	{ .channels = 2,
1288*4882a593Smuzhiyun 	  .map = { SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE } },
1289*4882a593Smuzhiyun 	{ }
1290*4882a593Smuzhiyun };
1291*4882a593Smuzhiyun 
1292*4882a593Smuzhiyun static const struct snd_pcm_chmap_elem side_map[] = {
1293*4882a593Smuzhiyun 	{ .channels = 2,
1294*4882a593Smuzhiyun 	  .map = { SNDRV_CHMAP_SL, SNDRV_CHMAP_SR } },
1295*4882a593Smuzhiyun 	{ }
1296*4882a593Smuzhiyun };
1297*4882a593Smuzhiyun 
snd_ca0106_pcm(struct snd_ca0106 * emu,int device)1298*4882a593Smuzhiyun static int snd_ca0106_pcm(struct snd_ca0106 *emu, int device)
1299*4882a593Smuzhiyun {
1300*4882a593Smuzhiyun 	struct snd_pcm *pcm;
1301*4882a593Smuzhiyun 	struct snd_pcm_substream *substream;
1302*4882a593Smuzhiyun 	const struct snd_pcm_chmap_elem *map = NULL;
1303*4882a593Smuzhiyun 	int err;
1304*4882a593Smuzhiyun 
1305*4882a593Smuzhiyun 	err = snd_pcm_new(emu->card, "ca0106", device, 1, 1, &pcm);
1306*4882a593Smuzhiyun 	if (err < 0)
1307*4882a593Smuzhiyun 		return err;
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	pcm->private_data = emu;
1310*4882a593Smuzhiyun 
1311*4882a593Smuzhiyun 	switch (device) {
1312*4882a593Smuzhiyun 	case 0:
1313*4882a593Smuzhiyun 	  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ca0106_playback_front_ops);
1314*4882a593Smuzhiyun 	  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ca0106_capture_0_ops);
1315*4882a593Smuzhiyun 	  map = snd_pcm_std_chmaps;
1316*4882a593Smuzhiyun           break;
1317*4882a593Smuzhiyun 	case 1:
1318*4882a593Smuzhiyun 	  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ca0106_playback_rear_ops);
1319*4882a593Smuzhiyun 	  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ca0106_capture_1_ops);
1320*4882a593Smuzhiyun 	  map = surround_map;
1321*4882a593Smuzhiyun           break;
1322*4882a593Smuzhiyun 	case 2:
1323*4882a593Smuzhiyun 	  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ca0106_playback_center_lfe_ops);
1324*4882a593Smuzhiyun 	  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ca0106_capture_2_ops);
1325*4882a593Smuzhiyun 	  map = clfe_map;
1326*4882a593Smuzhiyun           break;
1327*4882a593Smuzhiyun 	case 3:
1328*4882a593Smuzhiyun 	  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ca0106_playback_unknown_ops);
1329*4882a593Smuzhiyun 	  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ca0106_capture_3_ops);
1330*4882a593Smuzhiyun 	  map = side_map;
1331*4882a593Smuzhiyun           break;
1332*4882a593Smuzhiyun         }
1333*4882a593Smuzhiyun 
1334*4882a593Smuzhiyun 	pcm->info_flags = 0;
1335*4882a593Smuzhiyun 	strcpy(pcm->name, "CA0106");
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 	for(substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
1338*4882a593Smuzhiyun 	    substream;
1339*4882a593Smuzhiyun 	    substream = substream->next) {
1340*4882a593Smuzhiyun 		snd_pcm_set_managed_buffer(substream, SNDRV_DMA_TYPE_DEV,
1341*4882a593Smuzhiyun 					   &emu->pci->dev,
1342*4882a593Smuzhiyun 					   64*1024, 64*1024);
1343*4882a593Smuzhiyun 	}
1344*4882a593Smuzhiyun 
1345*4882a593Smuzhiyun 	for (substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
1346*4882a593Smuzhiyun 	      substream;
1347*4882a593Smuzhiyun 	      substream = substream->next) {
1348*4882a593Smuzhiyun 		snd_pcm_set_managed_buffer(substream, SNDRV_DMA_TYPE_DEV,
1349*4882a593Smuzhiyun 					   &emu->pci->dev,
1350*4882a593Smuzhiyun 					   64*1024, 64*1024);
1351*4882a593Smuzhiyun 	}
1352*4882a593Smuzhiyun 
1353*4882a593Smuzhiyun 	err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, map, 2,
1354*4882a593Smuzhiyun 				     1 << 2, NULL);
1355*4882a593Smuzhiyun 	if (err < 0)
1356*4882a593Smuzhiyun 		return err;
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 	emu->pcm[device] = pcm;
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	return 0;
1361*4882a593Smuzhiyun }
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun #define SPI_REG(reg, value)	(((reg) << SPI_REG_SHIFT) | (value))
1364*4882a593Smuzhiyun static const unsigned int spi_dac_init[] = {
1365*4882a593Smuzhiyun 	SPI_REG(SPI_LDA1_REG,	SPI_DA_BIT_0dB), /* 0dB dig. attenuation */
1366*4882a593Smuzhiyun 	SPI_REG(SPI_RDA1_REG,	SPI_DA_BIT_0dB),
1367*4882a593Smuzhiyun 	SPI_REG(SPI_PL_REG,	SPI_PL_BIT_L_L | SPI_PL_BIT_R_R | SPI_IZD_BIT),
1368*4882a593Smuzhiyun 	SPI_REG(SPI_FMT_REG,	SPI_FMT_BIT_I2S | SPI_IWL_BIT_24),
1369*4882a593Smuzhiyun 	SPI_REG(SPI_LDA2_REG,	SPI_DA_BIT_0dB),
1370*4882a593Smuzhiyun 	SPI_REG(SPI_RDA2_REG,	SPI_DA_BIT_0dB),
1371*4882a593Smuzhiyun 	SPI_REG(SPI_LDA3_REG,	SPI_DA_BIT_0dB),
1372*4882a593Smuzhiyun 	SPI_REG(SPI_RDA3_REG,	SPI_DA_BIT_0dB),
1373*4882a593Smuzhiyun 	SPI_REG(SPI_MASTDA_REG,	SPI_DA_BIT_0dB),
1374*4882a593Smuzhiyun 	SPI_REG(9,		0x00),
1375*4882a593Smuzhiyun 	SPI_REG(SPI_MS_REG,	SPI_DACD0_BIT | SPI_DACD1_BIT | SPI_DACD2_BIT),
1376*4882a593Smuzhiyun 	SPI_REG(12,		0x00),
1377*4882a593Smuzhiyun 	SPI_REG(SPI_LDA4_REG,	SPI_DA_BIT_0dB),
1378*4882a593Smuzhiyun 	SPI_REG(SPI_RDA4_REG,	SPI_DA_BIT_0dB | SPI_DA_BIT_UPDATE),
1379*4882a593Smuzhiyun 	SPI_REG(SPI_DACD4_REG,	SPI_DACD4_BIT),
1380*4882a593Smuzhiyun };
1381*4882a593Smuzhiyun 
1382*4882a593Smuzhiyun static const unsigned int i2c_adc_init[][2] = {
1383*4882a593Smuzhiyun 	{ 0x17, 0x00 }, /* Reset */
1384*4882a593Smuzhiyun 	{ 0x07, 0x00 }, /* Timeout */
1385*4882a593Smuzhiyun 	{ 0x0b, 0x22 },  /* Interface control */
1386*4882a593Smuzhiyun 	{ 0x0c, 0x22 },  /* Master mode control */
1387*4882a593Smuzhiyun 	{ 0x0d, 0x08 },  /* Powerdown control */
1388*4882a593Smuzhiyun 	{ 0x0e, 0xcf },  /* Attenuation Left  0x01 = -103dB, 0xff = 24dB */
1389*4882a593Smuzhiyun 	{ 0x0f, 0xcf },  /* Attenuation Right 0.5dB steps */
1390*4882a593Smuzhiyun 	{ 0x10, 0x7b },  /* ALC Control 1 */
1391*4882a593Smuzhiyun 	{ 0x11, 0x00 },  /* ALC Control 2 */
1392*4882a593Smuzhiyun 	{ 0x12, 0x32 },  /* ALC Control 3 */
1393*4882a593Smuzhiyun 	{ 0x13, 0x00 },  /* Noise gate control */
1394*4882a593Smuzhiyun 	{ 0x14, 0xa6 },  /* Limiter control */
1395*4882a593Smuzhiyun 	{ 0x15, ADC_MUX_LINEIN },  /* ADC Mixer control */
1396*4882a593Smuzhiyun };
1397*4882a593Smuzhiyun 
ca0106_init_chip(struct snd_ca0106 * chip,int resume)1398*4882a593Smuzhiyun static void ca0106_init_chip(struct snd_ca0106 *chip, int resume)
1399*4882a593Smuzhiyun {
1400*4882a593Smuzhiyun 	int ch;
1401*4882a593Smuzhiyun 	unsigned int def_bits;
1402*4882a593Smuzhiyun 
1403*4882a593Smuzhiyun 	outl(0, chip->port + INTE);
1404*4882a593Smuzhiyun 
1405*4882a593Smuzhiyun 	/*
1406*4882a593Smuzhiyun 	 *  Init to 0x02109204 :
1407*4882a593Smuzhiyun 	 *  Clock accuracy    = 0     (1000ppm)
1408*4882a593Smuzhiyun 	 *  Sample Rate       = 2     (48kHz)
1409*4882a593Smuzhiyun 	 *  Audio Channel     = 1     (Left of 2)
1410*4882a593Smuzhiyun 	 *  Source Number     = 0     (Unspecified)
1411*4882a593Smuzhiyun 	 *  Generation Status = 1     (Original for Cat Code 12)
1412*4882a593Smuzhiyun 	 *  Cat Code          = 12    (Digital Signal Mixer)
1413*4882a593Smuzhiyun 	 *  Mode              = 0     (Mode 0)
1414*4882a593Smuzhiyun 	 *  Emphasis          = 0     (None)
1415*4882a593Smuzhiyun 	 *  CP                = 1     (Copyright unasserted)
1416*4882a593Smuzhiyun 	 *  AN                = 0     (Audio data)
1417*4882a593Smuzhiyun 	 *  P                 = 0     (Consumer)
1418*4882a593Smuzhiyun 	 */
1419*4882a593Smuzhiyun 	def_bits =
1420*4882a593Smuzhiyun 		SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1421*4882a593Smuzhiyun 		SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
1422*4882a593Smuzhiyun 		SPCS_GENERATIONSTATUS | 0x00001200 |
1423*4882a593Smuzhiyun 		0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
1424*4882a593Smuzhiyun 	if (!resume) {
1425*4882a593Smuzhiyun 		chip->spdif_str_bits[0] = chip->spdif_bits[0] = def_bits;
1426*4882a593Smuzhiyun 		chip->spdif_str_bits[1] = chip->spdif_bits[1] = def_bits;
1427*4882a593Smuzhiyun 		chip->spdif_str_bits[2] = chip->spdif_bits[2] = def_bits;
1428*4882a593Smuzhiyun 		chip->spdif_str_bits[3] = chip->spdif_bits[3] = def_bits;
1429*4882a593Smuzhiyun 	}
1430*4882a593Smuzhiyun 	/* Only SPCS1 has been tested */
1431*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, SPCS1, 0, chip->spdif_str_bits[1]);
1432*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, SPCS0, 0, chip->spdif_str_bits[0]);
1433*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, SPCS2, 0, chip->spdif_str_bits[2]);
1434*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, SPCS3, 0, chip->spdif_str_bits[3]);
1435*4882a593Smuzhiyun 
1436*4882a593Smuzhiyun         snd_ca0106_ptr_write(chip, PLAYBACK_MUTE, 0, 0x00fc0000);
1437*4882a593Smuzhiyun         snd_ca0106_ptr_write(chip, CAPTURE_MUTE, 0, 0x00fc0000);
1438*4882a593Smuzhiyun 
1439*4882a593Smuzhiyun         /* Write 0x8000 to AC97_REC_GAIN to mute it. */
1440*4882a593Smuzhiyun         outb(AC97_REC_GAIN, chip->port + AC97ADDRESS);
1441*4882a593Smuzhiyun         outw(0x8000, chip->port + AC97DATA);
1442*4882a593Smuzhiyun #if 0 /* FIXME: what are these? */
1443*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, SPCS0, 0, 0x2108006);
1444*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, 0x42, 0, 0x2108006);
1445*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, 0x43, 0, 0x2108006);
1446*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, 0x44, 0, 0x2108006);
1447*4882a593Smuzhiyun #endif
1448*4882a593Smuzhiyun 
1449*4882a593Smuzhiyun 	/* OSS drivers set this. */
1450*4882a593Smuzhiyun 	/* snd_ca0106_ptr_write(chip, SPDIF_SELECT2, 0, 0xf0f003f); */
1451*4882a593Smuzhiyun 
1452*4882a593Smuzhiyun 	/* Analog or Digital output */
1453*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, SPDIF_SELECT1, 0, 0xf);
1454*4882a593Smuzhiyun 	/* 0x0b000000 for digital, 0x000b0000 for analog, from win2000 drivers.
1455*4882a593Smuzhiyun 	 * Use 0x000f0000 for surround71
1456*4882a593Smuzhiyun 	 */
1457*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, SPDIF_SELECT2, 0, 0x000f0000);
1458*4882a593Smuzhiyun 
1459*4882a593Smuzhiyun 	chip->spdif_enable = 0; /* Set digital SPDIF output off */
1460*4882a593Smuzhiyun 	/*snd_ca0106_ptr_write(chip, 0x45, 0, 0);*/ /* Analogue out */
1461*4882a593Smuzhiyun 	/*snd_ca0106_ptr_write(chip, 0x45, 0, 0xf00);*/ /* Digital out */
1462*4882a593Smuzhiyun 
1463*4882a593Smuzhiyun 	/* goes to 0x40c80000 when doing SPDIF IN/OUT */
1464*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, CAPTURE_CONTROL, 0, 0x40c81000);
1465*4882a593Smuzhiyun 	/* (Mute) CAPTURE feedback into PLAYBACK volume.
1466*4882a593Smuzhiyun 	 * Only lower 16 bits matter.
1467*4882a593Smuzhiyun 	 */
1468*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, CAPTURE_CONTROL, 1, 0xffffffff);
1469*4882a593Smuzhiyun 	/* SPDIF IN Volume */
1470*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, CAPTURE_CONTROL, 2, 0x30300000);
1471*4882a593Smuzhiyun 	/* SPDIF IN Volume, 0x70 = (vol & 0x3f) | 0x40 */
1472*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, CAPTURE_CONTROL, 3, 0x00700000);
1473*4882a593Smuzhiyun 
1474*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, PLAYBACK_ROUTING1, 0, 0x32765410);
1475*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, PLAYBACK_ROUTING2, 0, 0x76767676);
1476*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, CAPTURE_ROUTING1, 0, 0x32765410);
1477*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, CAPTURE_ROUTING2, 0, 0x76767676);
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	for (ch = 0; ch < 4; ch++) {
1480*4882a593Smuzhiyun 		/* Only high 16 bits matter */
1481*4882a593Smuzhiyun 		snd_ca0106_ptr_write(chip, CAPTURE_VOLUME1, ch, 0x30303030);
1482*4882a593Smuzhiyun 		snd_ca0106_ptr_write(chip, CAPTURE_VOLUME2, ch, 0x30303030);
1483*4882a593Smuzhiyun #if 0 /* Mute */
1484*4882a593Smuzhiyun 		snd_ca0106_ptr_write(chip, PLAYBACK_VOLUME1, ch, 0x40404040);
1485*4882a593Smuzhiyun 		snd_ca0106_ptr_write(chip, PLAYBACK_VOLUME2, ch, 0x40404040);
1486*4882a593Smuzhiyun 		snd_ca0106_ptr_write(chip, PLAYBACK_VOLUME1, ch, 0xffffffff);
1487*4882a593Smuzhiyun 		snd_ca0106_ptr_write(chip, PLAYBACK_VOLUME2, ch, 0xffffffff);
1488*4882a593Smuzhiyun #endif
1489*4882a593Smuzhiyun 	}
1490*4882a593Smuzhiyun 	if (chip->details->i2c_adc == 1) {
1491*4882a593Smuzhiyun 	        /* Select MIC, Line in, TAD in, AUX in */
1492*4882a593Smuzhiyun 	        snd_ca0106_ptr_write(chip, CAPTURE_SOURCE, 0x0, 0x333300e4);
1493*4882a593Smuzhiyun 		/* Default to CAPTURE_SOURCE to i2s in */
1494*4882a593Smuzhiyun 		if (!resume)
1495*4882a593Smuzhiyun 			chip->capture_source = 3;
1496*4882a593Smuzhiyun 	} else if (chip->details->ac97 == 1) {
1497*4882a593Smuzhiyun 	        /* Default to AC97 in */
1498*4882a593Smuzhiyun 	        snd_ca0106_ptr_write(chip, CAPTURE_SOURCE, 0x0, 0x444400e4);
1499*4882a593Smuzhiyun 		/* Default to CAPTURE_SOURCE to AC97 in */
1500*4882a593Smuzhiyun 		if (!resume)
1501*4882a593Smuzhiyun 			chip->capture_source = 4;
1502*4882a593Smuzhiyun 	} else {
1503*4882a593Smuzhiyun 	        /* Select MIC, Line in, TAD in, AUX in */
1504*4882a593Smuzhiyun 	        snd_ca0106_ptr_write(chip, CAPTURE_SOURCE, 0x0, 0x333300e4);
1505*4882a593Smuzhiyun 		/* Default to Set CAPTURE_SOURCE to i2s in */
1506*4882a593Smuzhiyun 		if (!resume)
1507*4882a593Smuzhiyun 			chip->capture_source = 3;
1508*4882a593Smuzhiyun 	}
1509*4882a593Smuzhiyun 
1510*4882a593Smuzhiyun 	if (chip->details->gpio_type == 2) {
1511*4882a593Smuzhiyun 		/* The SB0438 use GPIO differently. */
1512*4882a593Smuzhiyun 		/* FIXME: Still need to find out what the other GPIO bits do.
1513*4882a593Smuzhiyun 		 * E.g. For digital spdif out.
1514*4882a593Smuzhiyun 		 */
1515*4882a593Smuzhiyun 		outl(0x0, chip->port+GPIO);
1516*4882a593Smuzhiyun 		/* outl(0x00f0e000, chip->port+GPIO); */ /* Analog */
1517*4882a593Smuzhiyun 		outl(0x005f5301, chip->port+GPIO); /* Analog */
1518*4882a593Smuzhiyun 	} else if (chip->details->gpio_type == 1) {
1519*4882a593Smuzhiyun 		/* The SB0410 and SB0413 use GPIO differently. */
1520*4882a593Smuzhiyun 		/* FIXME: Still need to find out what the other GPIO bits do.
1521*4882a593Smuzhiyun 		 * E.g. For digital spdif out.
1522*4882a593Smuzhiyun 		 */
1523*4882a593Smuzhiyun 		outl(0x0, chip->port+GPIO);
1524*4882a593Smuzhiyun 		/* outl(0x00f0e000, chip->port+GPIO); */ /* Analog */
1525*4882a593Smuzhiyun 		outl(0x005f5301, chip->port+GPIO); /* Analog */
1526*4882a593Smuzhiyun 	} else {
1527*4882a593Smuzhiyun 		outl(0x0, chip->port+GPIO);
1528*4882a593Smuzhiyun 		outl(0x005f03a3, chip->port+GPIO); /* Analog */
1529*4882a593Smuzhiyun 		/* outl(0x005f02a2, chip->port+GPIO); */ /* SPDIF */
1530*4882a593Smuzhiyun 	}
1531*4882a593Smuzhiyun 	snd_ca0106_intr_enable(chip, 0x105); /* Win2000 uses 0x1e0 */
1532*4882a593Smuzhiyun 
1533*4882a593Smuzhiyun 	/* outl(HCFG_LOCKSOUNDCACHE|HCFG_AUDIOENABLE, chip->port+HCFG); */
1534*4882a593Smuzhiyun 	/* 0x1000 causes AC3 to fails. Maybe it effects 24 bit output. */
1535*4882a593Smuzhiyun 	/* outl(0x00001409, chip->port+HCFG); */
1536*4882a593Smuzhiyun 	/* outl(0x00000009, chip->port+HCFG); */
1537*4882a593Smuzhiyun 	/* AC97 2.0, Enable outputs. */
1538*4882a593Smuzhiyun 	outl(HCFG_AC97 | HCFG_AUDIOENABLE, chip->port+HCFG);
1539*4882a593Smuzhiyun 
1540*4882a593Smuzhiyun 	if (chip->details->i2c_adc == 1) {
1541*4882a593Smuzhiyun 		/* The SB0410 and SB0413 use I2C to control ADC. */
1542*4882a593Smuzhiyun 		int size, n;
1543*4882a593Smuzhiyun 
1544*4882a593Smuzhiyun 		size = ARRAY_SIZE(i2c_adc_init);
1545*4882a593Smuzhiyun 		/* dev_dbg(emu->card->dev, "I2C:array size=0x%x\n", size); */
1546*4882a593Smuzhiyun 		for (n = 0; n < size; n++)
1547*4882a593Smuzhiyun 			snd_ca0106_i2c_write(chip, i2c_adc_init[n][0],
1548*4882a593Smuzhiyun 					     i2c_adc_init[n][1]);
1549*4882a593Smuzhiyun 		for (n = 0; n < 4; n++) {
1550*4882a593Smuzhiyun 			chip->i2c_capture_volume[n][0] = 0xcf;
1551*4882a593Smuzhiyun 			chip->i2c_capture_volume[n][1] = 0xcf;
1552*4882a593Smuzhiyun 		}
1553*4882a593Smuzhiyun 		chip->i2c_capture_source = 2; /* Line in */
1554*4882a593Smuzhiyun 		/* Enable Line-in capture. MIC in currently untested. */
1555*4882a593Smuzhiyun 		/* snd_ca0106_i2c_write(chip, ADC_MUX, ADC_MUX_LINEIN); */
1556*4882a593Smuzhiyun 	}
1557*4882a593Smuzhiyun 
1558*4882a593Smuzhiyun 	if (chip->details->spi_dac) {
1559*4882a593Smuzhiyun 		/* The SB0570 use SPI to control DAC. */
1560*4882a593Smuzhiyun 		int size, n;
1561*4882a593Smuzhiyun 
1562*4882a593Smuzhiyun 		size = ARRAY_SIZE(spi_dac_init);
1563*4882a593Smuzhiyun 		for (n = 0; n < size; n++) {
1564*4882a593Smuzhiyun 			int reg = spi_dac_init[n] >> SPI_REG_SHIFT;
1565*4882a593Smuzhiyun 
1566*4882a593Smuzhiyun 			snd_ca0106_spi_write(chip, spi_dac_init[n]);
1567*4882a593Smuzhiyun 			if (reg < ARRAY_SIZE(chip->spi_dac_reg))
1568*4882a593Smuzhiyun 				chip->spi_dac_reg[reg] = spi_dac_init[n];
1569*4882a593Smuzhiyun 		}
1570*4882a593Smuzhiyun 
1571*4882a593Smuzhiyun 		/* Enable front dac only */
1572*4882a593Smuzhiyun 		snd_ca0106_pcm_power_dac(chip, PCM_FRONT_CHANNEL, 1);
1573*4882a593Smuzhiyun 	}
1574*4882a593Smuzhiyun }
1575*4882a593Smuzhiyun 
ca0106_stop_chip(struct snd_ca0106 * chip)1576*4882a593Smuzhiyun static void ca0106_stop_chip(struct snd_ca0106 *chip)
1577*4882a593Smuzhiyun {
1578*4882a593Smuzhiyun 	/* disable interrupts */
1579*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, BASIC_INTERRUPT, 0, 0);
1580*4882a593Smuzhiyun 	outl(0, chip->port + INTE);
1581*4882a593Smuzhiyun 	snd_ca0106_ptr_write(chip, EXTENDED_INT_MASK, 0, 0);
1582*4882a593Smuzhiyun 	udelay(1000);
1583*4882a593Smuzhiyun 	/* disable audio */
1584*4882a593Smuzhiyun 	/* outl(HCFG_LOCKSOUNDCACHE, chip->port + HCFG); */
1585*4882a593Smuzhiyun 	outl(0, chip->port + HCFG);
1586*4882a593Smuzhiyun 	/* FIXME: We need to stop and DMA transfers here.
1587*4882a593Smuzhiyun 	 *        But as I am not sure how yet, we cannot from the dma pages.
1588*4882a593Smuzhiyun 	 * So we can fix: snd-malloc: Memory leak?  pages not freed = 8
1589*4882a593Smuzhiyun 	 */
1590*4882a593Smuzhiyun }
1591*4882a593Smuzhiyun 
snd_ca0106_create(int dev,struct snd_card * card,struct pci_dev * pci,struct snd_ca0106 ** rchip)1592*4882a593Smuzhiyun static int snd_ca0106_create(int dev, struct snd_card *card,
1593*4882a593Smuzhiyun 					 struct pci_dev *pci,
1594*4882a593Smuzhiyun 					 struct snd_ca0106 **rchip)
1595*4882a593Smuzhiyun {
1596*4882a593Smuzhiyun 	struct snd_ca0106 *chip;
1597*4882a593Smuzhiyun 	const struct snd_ca0106_details *c;
1598*4882a593Smuzhiyun 	int err;
1599*4882a593Smuzhiyun 	static const struct snd_device_ops ops = {
1600*4882a593Smuzhiyun 		.dev_free = snd_ca0106_dev_free,
1601*4882a593Smuzhiyun 	};
1602*4882a593Smuzhiyun 
1603*4882a593Smuzhiyun 	*rchip = NULL;
1604*4882a593Smuzhiyun 
1605*4882a593Smuzhiyun 	err = pci_enable_device(pci);
1606*4882a593Smuzhiyun 	if (err < 0)
1607*4882a593Smuzhiyun 		return err;
1608*4882a593Smuzhiyun 	if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0 ||
1609*4882a593Smuzhiyun 	    dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) {
1610*4882a593Smuzhiyun 		dev_err(card->dev, "error to set 32bit mask DMA\n");
1611*4882a593Smuzhiyun 		pci_disable_device(pci);
1612*4882a593Smuzhiyun 		return -ENXIO;
1613*4882a593Smuzhiyun 	}
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun 	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1616*4882a593Smuzhiyun 	if (chip == NULL) {
1617*4882a593Smuzhiyun 		pci_disable_device(pci);
1618*4882a593Smuzhiyun 		return -ENOMEM;
1619*4882a593Smuzhiyun 	}
1620*4882a593Smuzhiyun 
1621*4882a593Smuzhiyun 	chip->card = card;
1622*4882a593Smuzhiyun 	chip->pci = pci;
1623*4882a593Smuzhiyun 	chip->irq = -1;
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun 	spin_lock_init(&chip->emu_lock);
1626*4882a593Smuzhiyun 
1627*4882a593Smuzhiyun 	chip->port = pci_resource_start(pci, 0);
1628*4882a593Smuzhiyun 	chip->res_port = request_region(chip->port, 0x20, "snd_ca0106");
1629*4882a593Smuzhiyun 	if (!chip->res_port) {
1630*4882a593Smuzhiyun 		snd_ca0106_free(chip);
1631*4882a593Smuzhiyun 		dev_err(card->dev, "cannot allocate the port\n");
1632*4882a593Smuzhiyun 		return -EBUSY;
1633*4882a593Smuzhiyun 	}
1634*4882a593Smuzhiyun 
1635*4882a593Smuzhiyun 	if (request_irq(pci->irq, snd_ca0106_interrupt,
1636*4882a593Smuzhiyun 			IRQF_SHARED, KBUILD_MODNAME, chip)) {
1637*4882a593Smuzhiyun 		snd_ca0106_free(chip);
1638*4882a593Smuzhiyun 		dev_err(card->dev, "cannot grab irq\n");
1639*4882a593Smuzhiyun 		return -EBUSY;
1640*4882a593Smuzhiyun 	}
1641*4882a593Smuzhiyun 	chip->irq = pci->irq;
1642*4882a593Smuzhiyun 	card->sync_irq = chip->irq;
1643*4882a593Smuzhiyun 
1644*4882a593Smuzhiyun 	/* This stores the periods table. */
1645*4882a593Smuzhiyun 	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
1646*4882a593Smuzhiyun 				1024, &chip->buffer) < 0) {
1647*4882a593Smuzhiyun 		snd_ca0106_free(chip);
1648*4882a593Smuzhiyun 		return -ENOMEM;
1649*4882a593Smuzhiyun 	}
1650*4882a593Smuzhiyun 
1651*4882a593Smuzhiyun 	pci_set_master(pci);
1652*4882a593Smuzhiyun 	/* read serial */
1653*4882a593Smuzhiyun 	pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &chip->serial);
1654*4882a593Smuzhiyun 	pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &chip->model);
1655*4882a593Smuzhiyun 	dev_info(card->dev, "Model %04x Rev %08x Serial %08x\n",
1656*4882a593Smuzhiyun 	       chip->model, pci->revision, chip->serial);
1657*4882a593Smuzhiyun 	strcpy(card->driver, "CA0106");
1658*4882a593Smuzhiyun 	strcpy(card->shortname, "CA0106");
1659*4882a593Smuzhiyun 
1660*4882a593Smuzhiyun 	for (c = ca0106_chip_details; c->serial; c++) {
1661*4882a593Smuzhiyun 		if (subsystem[dev]) {
1662*4882a593Smuzhiyun 			if (c->serial == subsystem[dev])
1663*4882a593Smuzhiyun 				break;
1664*4882a593Smuzhiyun 		} else if (c->serial == chip->serial)
1665*4882a593Smuzhiyun 			break;
1666*4882a593Smuzhiyun 	}
1667*4882a593Smuzhiyun 	chip->details = c;
1668*4882a593Smuzhiyun 	if (subsystem[dev]) {
1669*4882a593Smuzhiyun 		dev_info(card->dev, "Sound card name=%s, "
1670*4882a593Smuzhiyun 		       "subsystem=0x%x. Forced to subsystem=0x%x\n",
1671*4882a593Smuzhiyun 		       c->name, chip->serial, subsystem[dev]);
1672*4882a593Smuzhiyun 	}
1673*4882a593Smuzhiyun 
1674*4882a593Smuzhiyun 	sprintf(card->longname, "%s at 0x%lx irq %i",
1675*4882a593Smuzhiyun 		c->name, chip->port, chip->irq);
1676*4882a593Smuzhiyun 
1677*4882a593Smuzhiyun 	ca0106_init_chip(chip, 0);
1678*4882a593Smuzhiyun 
1679*4882a593Smuzhiyun 	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1680*4882a593Smuzhiyun 	if (err < 0) {
1681*4882a593Smuzhiyun 		snd_ca0106_free(chip);
1682*4882a593Smuzhiyun 		return err;
1683*4882a593Smuzhiyun 	}
1684*4882a593Smuzhiyun 	*rchip = chip;
1685*4882a593Smuzhiyun 	return 0;
1686*4882a593Smuzhiyun }
1687*4882a593Smuzhiyun 
1688*4882a593Smuzhiyun 
ca0106_midi_interrupt_enable(struct snd_ca_midi * midi,int intr)1689*4882a593Smuzhiyun static void ca0106_midi_interrupt_enable(struct snd_ca_midi *midi, int intr)
1690*4882a593Smuzhiyun {
1691*4882a593Smuzhiyun 	snd_ca0106_intr_enable((struct snd_ca0106 *)(midi->dev_id), intr);
1692*4882a593Smuzhiyun }
1693*4882a593Smuzhiyun 
ca0106_midi_interrupt_disable(struct snd_ca_midi * midi,int intr)1694*4882a593Smuzhiyun static void ca0106_midi_interrupt_disable(struct snd_ca_midi *midi, int intr)
1695*4882a593Smuzhiyun {
1696*4882a593Smuzhiyun 	snd_ca0106_intr_disable((struct snd_ca0106 *)(midi->dev_id), intr);
1697*4882a593Smuzhiyun }
1698*4882a593Smuzhiyun 
ca0106_midi_read(struct snd_ca_midi * midi,int idx)1699*4882a593Smuzhiyun static unsigned char ca0106_midi_read(struct snd_ca_midi *midi, int idx)
1700*4882a593Smuzhiyun {
1701*4882a593Smuzhiyun 	return (unsigned char)snd_ca0106_ptr_read((struct snd_ca0106 *)(midi->dev_id),
1702*4882a593Smuzhiyun 						  midi->port + idx, 0);
1703*4882a593Smuzhiyun }
1704*4882a593Smuzhiyun 
ca0106_midi_write(struct snd_ca_midi * midi,int data,int idx)1705*4882a593Smuzhiyun static void ca0106_midi_write(struct snd_ca_midi *midi, int data, int idx)
1706*4882a593Smuzhiyun {
1707*4882a593Smuzhiyun 	snd_ca0106_ptr_write((struct snd_ca0106 *)(midi->dev_id), midi->port + idx, 0, data);
1708*4882a593Smuzhiyun }
1709*4882a593Smuzhiyun 
ca0106_dev_id_card(void * dev_id)1710*4882a593Smuzhiyun static struct snd_card *ca0106_dev_id_card(void *dev_id)
1711*4882a593Smuzhiyun {
1712*4882a593Smuzhiyun 	return ((struct snd_ca0106 *)dev_id)->card;
1713*4882a593Smuzhiyun }
1714*4882a593Smuzhiyun 
ca0106_dev_id_port(void * dev_id)1715*4882a593Smuzhiyun static int ca0106_dev_id_port(void *dev_id)
1716*4882a593Smuzhiyun {
1717*4882a593Smuzhiyun 	return ((struct snd_ca0106 *)dev_id)->port;
1718*4882a593Smuzhiyun }
1719*4882a593Smuzhiyun 
snd_ca0106_midi(struct snd_ca0106 * chip,unsigned int channel)1720*4882a593Smuzhiyun static int snd_ca0106_midi(struct snd_ca0106 *chip, unsigned int channel)
1721*4882a593Smuzhiyun {
1722*4882a593Smuzhiyun 	struct snd_ca_midi *midi;
1723*4882a593Smuzhiyun 	char *name;
1724*4882a593Smuzhiyun 	int err;
1725*4882a593Smuzhiyun 
1726*4882a593Smuzhiyun 	if (channel == CA0106_MIDI_CHAN_B) {
1727*4882a593Smuzhiyun 		name = "CA0106 MPU-401 (UART) B";
1728*4882a593Smuzhiyun 		midi =  &chip->midi2;
1729*4882a593Smuzhiyun 		midi->tx_enable = INTE_MIDI_TX_B;
1730*4882a593Smuzhiyun 		midi->rx_enable = INTE_MIDI_RX_B;
1731*4882a593Smuzhiyun 		midi->ipr_tx = IPR_MIDI_TX_B;
1732*4882a593Smuzhiyun 		midi->ipr_rx = IPR_MIDI_RX_B;
1733*4882a593Smuzhiyun 		midi->port = MIDI_UART_B_DATA;
1734*4882a593Smuzhiyun 	} else {
1735*4882a593Smuzhiyun 		name = "CA0106 MPU-401 (UART)";
1736*4882a593Smuzhiyun 		midi =  &chip->midi;
1737*4882a593Smuzhiyun 		midi->tx_enable = INTE_MIDI_TX_A;
1738*4882a593Smuzhiyun 		midi->rx_enable = INTE_MIDI_TX_B;
1739*4882a593Smuzhiyun 		midi->ipr_tx = IPR_MIDI_TX_A;
1740*4882a593Smuzhiyun 		midi->ipr_rx = IPR_MIDI_RX_A;
1741*4882a593Smuzhiyun 		midi->port = MIDI_UART_A_DATA;
1742*4882a593Smuzhiyun 	}
1743*4882a593Smuzhiyun 
1744*4882a593Smuzhiyun 	midi->reset = CA0106_MPU401_RESET;
1745*4882a593Smuzhiyun 	midi->enter_uart = CA0106_MPU401_ENTER_UART;
1746*4882a593Smuzhiyun 	midi->ack = CA0106_MPU401_ACK;
1747*4882a593Smuzhiyun 
1748*4882a593Smuzhiyun 	midi->input_avail = CA0106_MIDI_INPUT_AVAIL;
1749*4882a593Smuzhiyun 	midi->output_ready = CA0106_MIDI_OUTPUT_READY;
1750*4882a593Smuzhiyun 
1751*4882a593Smuzhiyun 	midi->channel = channel;
1752*4882a593Smuzhiyun 
1753*4882a593Smuzhiyun 	midi->interrupt_enable = ca0106_midi_interrupt_enable;
1754*4882a593Smuzhiyun 	midi->interrupt_disable = ca0106_midi_interrupt_disable;
1755*4882a593Smuzhiyun 
1756*4882a593Smuzhiyun 	midi->read = ca0106_midi_read;
1757*4882a593Smuzhiyun 	midi->write = ca0106_midi_write;
1758*4882a593Smuzhiyun 
1759*4882a593Smuzhiyun 	midi->get_dev_id_card = ca0106_dev_id_card;
1760*4882a593Smuzhiyun 	midi->get_dev_id_port = ca0106_dev_id_port;
1761*4882a593Smuzhiyun 
1762*4882a593Smuzhiyun 	midi->dev_id = chip;
1763*4882a593Smuzhiyun 
1764*4882a593Smuzhiyun 	if ((err = ca_midi_init(chip, midi, 0, name)) < 0)
1765*4882a593Smuzhiyun 		return err;
1766*4882a593Smuzhiyun 
1767*4882a593Smuzhiyun 	return 0;
1768*4882a593Smuzhiyun }
1769*4882a593Smuzhiyun 
1770*4882a593Smuzhiyun 
snd_ca0106_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1771*4882a593Smuzhiyun static int snd_ca0106_probe(struct pci_dev *pci,
1772*4882a593Smuzhiyun 					const struct pci_device_id *pci_id)
1773*4882a593Smuzhiyun {
1774*4882a593Smuzhiyun 	static int dev;
1775*4882a593Smuzhiyun 	struct snd_card *card;
1776*4882a593Smuzhiyun 	struct snd_ca0106 *chip;
1777*4882a593Smuzhiyun 	int i, err;
1778*4882a593Smuzhiyun 
1779*4882a593Smuzhiyun 	if (dev >= SNDRV_CARDS)
1780*4882a593Smuzhiyun 		return -ENODEV;
1781*4882a593Smuzhiyun 	if (!enable[dev]) {
1782*4882a593Smuzhiyun 		dev++;
1783*4882a593Smuzhiyun 		return -ENOENT;
1784*4882a593Smuzhiyun 	}
1785*4882a593Smuzhiyun 
1786*4882a593Smuzhiyun 	err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1787*4882a593Smuzhiyun 			   0, &card);
1788*4882a593Smuzhiyun 	if (err < 0)
1789*4882a593Smuzhiyun 		return err;
1790*4882a593Smuzhiyun 
1791*4882a593Smuzhiyun 	err = snd_ca0106_create(dev, card, pci, &chip);
1792*4882a593Smuzhiyun 	if (err < 0)
1793*4882a593Smuzhiyun 		goto error;
1794*4882a593Smuzhiyun 	card->private_data = chip;
1795*4882a593Smuzhiyun 
1796*4882a593Smuzhiyun 	for (i = 0; i < 4; i++) {
1797*4882a593Smuzhiyun 		err = snd_ca0106_pcm(chip, i);
1798*4882a593Smuzhiyun 		if (err < 0)
1799*4882a593Smuzhiyun 			goto error;
1800*4882a593Smuzhiyun 	}
1801*4882a593Smuzhiyun 
1802*4882a593Smuzhiyun 	if (chip->details->ac97 == 1) {
1803*4882a593Smuzhiyun 		/* The SB0410 and SB0413 do not have an AC97 chip. */
1804*4882a593Smuzhiyun 		err = snd_ca0106_ac97(chip);
1805*4882a593Smuzhiyun 		if (err < 0)
1806*4882a593Smuzhiyun 			goto error;
1807*4882a593Smuzhiyun 	}
1808*4882a593Smuzhiyun 	err = snd_ca0106_mixer(chip);
1809*4882a593Smuzhiyun 	if (err < 0)
1810*4882a593Smuzhiyun 		goto error;
1811*4882a593Smuzhiyun 
1812*4882a593Smuzhiyun 	dev_dbg(card->dev, "probe for MIDI channel A ...");
1813*4882a593Smuzhiyun 	err = snd_ca0106_midi(chip, CA0106_MIDI_CHAN_A);
1814*4882a593Smuzhiyun 	if (err < 0)
1815*4882a593Smuzhiyun 		goto error;
1816*4882a593Smuzhiyun 	dev_dbg(card->dev, " done.\n");
1817*4882a593Smuzhiyun 
1818*4882a593Smuzhiyun #ifdef CONFIG_SND_PROC_FS
1819*4882a593Smuzhiyun 	snd_ca0106_proc_init(chip);
1820*4882a593Smuzhiyun #endif
1821*4882a593Smuzhiyun 
1822*4882a593Smuzhiyun 	err = snd_card_register(card);
1823*4882a593Smuzhiyun 	if (err < 0)
1824*4882a593Smuzhiyun 		goto error;
1825*4882a593Smuzhiyun 
1826*4882a593Smuzhiyun 	pci_set_drvdata(pci, card);
1827*4882a593Smuzhiyun 	dev++;
1828*4882a593Smuzhiyun 	return 0;
1829*4882a593Smuzhiyun 
1830*4882a593Smuzhiyun  error:
1831*4882a593Smuzhiyun 	snd_card_free(card);
1832*4882a593Smuzhiyun 	return err;
1833*4882a593Smuzhiyun }
1834*4882a593Smuzhiyun 
snd_ca0106_remove(struct pci_dev * pci)1835*4882a593Smuzhiyun static void snd_ca0106_remove(struct pci_dev *pci)
1836*4882a593Smuzhiyun {
1837*4882a593Smuzhiyun 	snd_card_free(pci_get_drvdata(pci));
1838*4882a593Smuzhiyun }
1839*4882a593Smuzhiyun 
1840*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
snd_ca0106_suspend(struct device * dev)1841*4882a593Smuzhiyun static int snd_ca0106_suspend(struct device *dev)
1842*4882a593Smuzhiyun {
1843*4882a593Smuzhiyun 	struct snd_card *card = dev_get_drvdata(dev);
1844*4882a593Smuzhiyun 	struct snd_ca0106 *chip = card->private_data;
1845*4882a593Smuzhiyun 
1846*4882a593Smuzhiyun 	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1847*4882a593Smuzhiyun 	if (chip->details->ac97)
1848*4882a593Smuzhiyun 		snd_ac97_suspend(chip->ac97);
1849*4882a593Smuzhiyun 	snd_ca0106_mixer_suspend(chip);
1850*4882a593Smuzhiyun 
1851*4882a593Smuzhiyun 	ca0106_stop_chip(chip);
1852*4882a593Smuzhiyun 	return 0;
1853*4882a593Smuzhiyun }
1854*4882a593Smuzhiyun 
snd_ca0106_resume(struct device * dev)1855*4882a593Smuzhiyun static int snd_ca0106_resume(struct device *dev)
1856*4882a593Smuzhiyun {
1857*4882a593Smuzhiyun 	struct snd_card *card = dev_get_drvdata(dev);
1858*4882a593Smuzhiyun 	struct snd_ca0106 *chip = card->private_data;
1859*4882a593Smuzhiyun 	int i;
1860*4882a593Smuzhiyun 
1861*4882a593Smuzhiyun 	ca0106_init_chip(chip, 1);
1862*4882a593Smuzhiyun 
1863*4882a593Smuzhiyun 	if (chip->details->ac97)
1864*4882a593Smuzhiyun 		snd_ac97_resume(chip->ac97);
1865*4882a593Smuzhiyun 	snd_ca0106_mixer_resume(chip);
1866*4882a593Smuzhiyun 	if (chip->details->spi_dac) {
1867*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(chip->spi_dac_reg); i++)
1868*4882a593Smuzhiyun 			snd_ca0106_spi_write(chip, chip->spi_dac_reg[i]);
1869*4882a593Smuzhiyun 	}
1870*4882a593Smuzhiyun 
1871*4882a593Smuzhiyun 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1872*4882a593Smuzhiyun 	return 0;
1873*4882a593Smuzhiyun }
1874*4882a593Smuzhiyun 
1875*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(snd_ca0106_pm, snd_ca0106_suspend, snd_ca0106_resume);
1876*4882a593Smuzhiyun #define SND_CA0106_PM_OPS	&snd_ca0106_pm
1877*4882a593Smuzhiyun #else
1878*4882a593Smuzhiyun #define SND_CA0106_PM_OPS	NULL
1879*4882a593Smuzhiyun #endif
1880*4882a593Smuzhiyun 
1881*4882a593Smuzhiyun // PCI IDs
1882*4882a593Smuzhiyun static const struct pci_device_id snd_ca0106_ids[] = {
1883*4882a593Smuzhiyun 	{ PCI_VDEVICE(CREATIVE, 0x0007), 0 },	/* Audigy LS or Live 24bit */
1884*4882a593Smuzhiyun 	{ 0, }
1885*4882a593Smuzhiyun };
1886*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_ca0106_ids);
1887*4882a593Smuzhiyun 
1888*4882a593Smuzhiyun // pci_driver definition
1889*4882a593Smuzhiyun static struct pci_driver ca0106_driver = {
1890*4882a593Smuzhiyun 	.name = KBUILD_MODNAME,
1891*4882a593Smuzhiyun 	.id_table = snd_ca0106_ids,
1892*4882a593Smuzhiyun 	.probe = snd_ca0106_probe,
1893*4882a593Smuzhiyun 	.remove = snd_ca0106_remove,
1894*4882a593Smuzhiyun 	.driver = {
1895*4882a593Smuzhiyun 		.pm = SND_CA0106_PM_OPS,
1896*4882a593Smuzhiyun 	},
1897*4882a593Smuzhiyun };
1898*4882a593Smuzhiyun 
1899*4882a593Smuzhiyun module_pci_driver(ca0106_driver);
1900