1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /***************************************************************************** 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and 5*4882a593Smuzhiyun * Jean-Christian Hassler <jhassler@free.fr> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file is part of the Audiowerk2 ALSA driver 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun *****************************************************************************/ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* SAA7146 registers */ 12*4882a593Smuzhiyun #define PCI_BT_A 0x4C 13*4882a593Smuzhiyun #define IICTFR 0x8C 14*4882a593Smuzhiyun #define IICSTA 0x90 15*4882a593Smuzhiyun #define BaseA1_in 0x94 16*4882a593Smuzhiyun #define ProtA1_in 0x98 17*4882a593Smuzhiyun #define PageA1_in 0x9C 18*4882a593Smuzhiyun #define BaseA1_out 0xA0 19*4882a593Smuzhiyun #define ProtA1_out 0xA4 20*4882a593Smuzhiyun #define PageA1_out 0xA8 21*4882a593Smuzhiyun #define BaseA2_in 0xAC 22*4882a593Smuzhiyun #define ProtA2_in 0xB0 23*4882a593Smuzhiyun #define PageA2_in 0xB4 24*4882a593Smuzhiyun #define BaseA2_out 0xB8 25*4882a593Smuzhiyun #define ProtA2_out 0xBC 26*4882a593Smuzhiyun #define PageA2_out 0xC0 27*4882a593Smuzhiyun #define IER 0xDC 28*4882a593Smuzhiyun #define GPIO_CTRL 0xE0 29*4882a593Smuzhiyun #define ACON1 0xF4 30*4882a593Smuzhiyun #define ACON2 0xF8 31*4882a593Smuzhiyun #define MC1 0xFC 32*4882a593Smuzhiyun #define MC2 0x100 33*4882a593Smuzhiyun #define ISR 0x10C 34*4882a593Smuzhiyun #define PSR 0x110 35*4882a593Smuzhiyun #define SSR 0x114 36*4882a593Smuzhiyun #define PCI_ADP1 0x12C 37*4882a593Smuzhiyun #define PCI_ADP2 0x130 38*4882a593Smuzhiyun #define PCI_ADP3 0x134 39*4882a593Smuzhiyun #define PCI_ADP4 0x138 40*4882a593Smuzhiyun #define LEVEL_REP 0x140 41*4882a593Smuzhiyun #define FB_BUFFER1 0x144 42*4882a593Smuzhiyun #define FB_BUFFER2 0x148 43*4882a593Smuzhiyun #define TSL1 0x180 44*4882a593Smuzhiyun #define TSL2 0x1C0 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define ME (1UL << 11) 47*4882a593Smuzhiyun #define LIMIT (1UL << 4) 48*4882a593Smuzhiyun #define PV (1UL << 3) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* PSR/ISR/IER */ 51*4882a593Smuzhiyun #define PPEF (1UL << 31) 52*4882a593Smuzhiyun #define PABO (1UL << 30) 53*4882a593Smuzhiyun #define IIC_S (1UL << 17) 54*4882a593Smuzhiyun #define IIC_E (1UL << 16) 55*4882a593Smuzhiyun #define A2_in (1UL << 15) 56*4882a593Smuzhiyun #define A2_out (1UL << 14) 57*4882a593Smuzhiyun #define A1_in (1UL << 13) 58*4882a593Smuzhiyun #define A1_out (1UL << 12) 59*4882a593Smuzhiyun #define AFOU (1UL << 11) 60*4882a593Smuzhiyun #define PIN3 (1UL << 6) 61*4882a593Smuzhiyun #define PIN2 (1UL << 5) 62*4882a593Smuzhiyun #define PIN1 (1UL << 4) 63*4882a593Smuzhiyun #define PIN0 (1UL << 3) 64*4882a593Smuzhiyun #define ECS (1UL << 2) 65*4882a593Smuzhiyun #define EC3S (1UL << 1) 66*4882a593Smuzhiyun #define EC0S (1UL << 0) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* SSR */ 69*4882a593Smuzhiyun #define PRQ (1UL << 31) 70*4882a593Smuzhiyun #define PMA (1UL << 30) 71*4882a593Smuzhiyun #define IIC_EA (1UL << 21) 72*4882a593Smuzhiyun #define IIC_EW (1UL << 20) 73*4882a593Smuzhiyun #define IIC_ER (1UL << 19) 74*4882a593Smuzhiyun #define IIC_EL (1UL << 18) 75*4882a593Smuzhiyun #define IIC_EF (1UL << 17) 76*4882a593Smuzhiyun #define AF2_in (1UL << 10) 77*4882a593Smuzhiyun #define AF2_out (1UL << 9) 78*4882a593Smuzhiyun #define AF1_in (1UL << 8) 79*4882a593Smuzhiyun #define AF1_out (1UL << 7) 80*4882a593Smuzhiyun #define EC5S (1UL << 3) 81*4882a593Smuzhiyun #define EC4S (1UL << 2) 82*4882a593Smuzhiyun #define EC2S (1UL << 1) 83*4882a593Smuzhiyun #define EC1S (1UL << 0) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* PCI_BT_A */ 86*4882a593Smuzhiyun #define BurstA1_in (1UL << 26) 87*4882a593Smuzhiyun #define ThreshA1_in (1UL << 24) 88*4882a593Smuzhiyun #define BurstA1_out (1UL << 18) 89*4882a593Smuzhiyun #define ThreshA1_out (1UL << 16) 90*4882a593Smuzhiyun #define BurstA2_in (1UL << 10) 91*4882a593Smuzhiyun #define ThreshA2_in (1UL << 8) 92*4882a593Smuzhiyun #define BurstA2_out (1UL << 2) 93*4882a593Smuzhiyun #define ThreshA2_out (1UL << 0) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* MC1 */ 96*4882a593Smuzhiyun #define MRST_N (1UL << 15) 97*4882a593Smuzhiyun #define EAP (1UL << 9) 98*4882a593Smuzhiyun #define EI2C (1UL << 8) 99*4882a593Smuzhiyun #define TR_E_A2_OUT (1UL << 3) 100*4882a593Smuzhiyun #define TR_E_A2_IN (1UL << 2) 101*4882a593Smuzhiyun #define TR_E_A1_OUT (1UL << 1) 102*4882a593Smuzhiyun #define TR_E_A1_IN (1UL << 0) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* MC2 */ 105*4882a593Smuzhiyun #define UPLD_IIC (1UL << 0) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* ACON1 */ 108*4882a593Smuzhiyun #define AUDIO_MODE (1UL << 29) 109*4882a593Smuzhiyun #define MAXLEVEL (1UL << 22) 110*4882a593Smuzhiyun #define A1_SWAP (1UL << 21) 111*4882a593Smuzhiyun #define A2_SWAP (1UL << 20) 112*4882a593Smuzhiyun #define WS0_CTRL (1UL << 18) 113*4882a593Smuzhiyun #define WS0_SYNC (1UL << 16) 114*4882a593Smuzhiyun #define WS1_CTRL (1UL << 14) 115*4882a593Smuzhiyun #define WS1_SYNC (1UL << 12) 116*4882a593Smuzhiyun #define WS2_CTRL (1UL << 10) 117*4882a593Smuzhiyun #define WS2_SYNC (1UL << 8) 118*4882a593Smuzhiyun #define WS3_CTRL (1UL << 6) 119*4882a593Smuzhiyun #define WS3_SYNC (1UL << 4) 120*4882a593Smuzhiyun #define WS4_CTRL (1UL << 2) 121*4882a593Smuzhiyun #define WS4_SYNC (1UL << 0) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* ACON2 */ 124*4882a593Smuzhiyun #define A1_CLKSRC (1UL << 27) 125*4882a593Smuzhiyun #define A2_CLKSRC (1UL << 22) 126*4882a593Smuzhiyun #define INVERT_BCLK1 (1UL << 21) 127*4882a593Smuzhiyun #define INVERT_BCLK2 (1UL << 20) 128*4882a593Smuzhiyun #define BCLK1_OEN (1UL << 19) 129*4882a593Smuzhiyun #define BCLK2_OEN (1UL << 18) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* IICSTA */ 132*4882a593Smuzhiyun #define IICCC (1UL << 8) 133*4882a593Smuzhiyun #define ABORT (1UL << 7) 134*4882a593Smuzhiyun #define SPERR (1UL << 6) 135*4882a593Smuzhiyun #define APERR (1UL << 5) 136*4882a593Smuzhiyun #define DTERR (1UL << 4) 137*4882a593Smuzhiyun #define DRERR (1UL << 3) 138*4882a593Smuzhiyun #define AL (1UL << 2) 139*4882a593Smuzhiyun #define ERR (1UL << 1) 140*4882a593Smuzhiyun #define BUSY (1UL << 0) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* IICTFR */ 143*4882a593Smuzhiyun #define BYTE2 (1UL << 24) 144*4882a593Smuzhiyun #define BYTE1 (1UL << 16) 145*4882a593Smuzhiyun #define BYTE0 (1UL << 8) 146*4882a593Smuzhiyun #define ATRR2 (1UL << 6) 147*4882a593Smuzhiyun #define ATRR1 (1UL << 4) 148*4882a593Smuzhiyun #define ATRR0 (1UL << 2) 149*4882a593Smuzhiyun #define ERR (1UL << 1) 150*4882a593Smuzhiyun #define BUSY (1UL << 0) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define START 3 153*4882a593Smuzhiyun #define CONT 2 154*4882a593Smuzhiyun #define STOP 1 155*4882a593Smuzhiyun #define NOP 0 156