1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /***************************************************************************** 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and 5*4882a593Smuzhiyun * Jean-Christian Hassler <jhassler@free.fr> 6*4882a593Smuzhiyun * Copyright 1998 Emagic Soft- und Hardware GmbH 7*4882a593Smuzhiyun * Copyright 2002 Martijn Sipkema 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This file is part of the Audiowerk2 ALSA driver 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun *****************************************************************************/ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define TSL_WS0 (1UL << 31) 14*4882a593Smuzhiyun #define TSL_WS1 (1UL << 30) 15*4882a593Smuzhiyun #define TSL_WS2 (1UL << 29) 16*4882a593Smuzhiyun #define TSL_WS3 (1UL << 28) 17*4882a593Smuzhiyun #define TSL_WS4 (1UL << 27) 18*4882a593Smuzhiyun #define TSL_DIS_A1 (1UL << 24) 19*4882a593Smuzhiyun #define TSL_SDW_A1 (1UL << 23) 20*4882a593Smuzhiyun #define TSL_SIB_A1 (1UL << 22) 21*4882a593Smuzhiyun #define TSL_SF_A1 (1UL << 21) 22*4882a593Smuzhiyun #define TSL_LF_A1 (1UL << 20) 23*4882a593Smuzhiyun #define TSL_BSEL_A1 (1UL << 17) 24*4882a593Smuzhiyun #define TSL_DOD_A1 (1UL << 15) 25*4882a593Smuzhiyun #define TSL_LOW_A1 (1UL << 14) 26*4882a593Smuzhiyun #define TSL_DIS_A2 (1UL << 11) 27*4882a593Smuzhiyun #define TSL_SDW_A2 (1UL << 10) 28*4882a593Smuzhiyun #define TSL_SIB_A2 (1UL << 9) 29*4882a593Smuzhiyun #define TSL_SF_A2 (1UL << 8) 30*4882a593Smuzhiyun #define TSL_LF_A2 (1UL << 7) 31*4882a593Smuzhiyun #define TSL_BSEL_A2 (1UL << 4) 32*4882a593Smuzhiyun #define TSL_DOD_A2 (1UL << 2) 33*4882a593Smuzhiyun #define TSL_LOW_A2 (1UL << 1) 34*4882a593Smuzhiyun #define TSL_EOS (1UL << 0) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Audiowerk8 hardware setup: */ 37*4882a593Smuzhiyun /* WS0, SD4, TSL1 - Analog/ digital in */ 38*4882a593Smuzhiyun /* WS1, SD0, TSL1 - Analog out #1, digital out */ 39*4882a593Smuzhiyun /* WS2, SD2, TSL1 - Analog out #2 */ 40*4882a593Smuzhiyun /* WS3, SD1, TSL2 - Analog out #3 */ 41*4882a593Smuzhiyun /* WS4, SD3, TSL2 - Analog out #4 */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Audiowerk8 timing: */ 44*4882a593Smuzhiyun /* Timeslot: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ... */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* A1_INPUT: */ 47*4882a593Smuzhiyun /* SD4: <_ADC-L_>-------<_ADC-R_>-------< */ 48*4882a593Smuzhiyun /* WS0: _______________/---------------\_ */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* A1_OUTPUT: */ 51*4882a593Smuzhiyun /* SD0: <_1-L___>-------<_1-R___>-------< */ 52*4882a593Smuzhiyun /* WS1: _______________/---------------\_ */ 53*4882a593Smuzhiyun /* SD2: >-------<_2-L___>-------<_2-R___> */ 54*4882a593Smuzhiyun /* WS2: -------\_______________/--------- */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* A2_OUTPUT: */ 57*4882a593Smuzhiyun /* SD1: <_3-L___>-------<_3-R___>-------< */ 58*4882a593Smuzhiyun /* WS3: _______________/---------------\_ */ 59*4882a593Smuzhiyun /* SD3: >-------<_4-L___>-------<_4-R___> */ 60*4882a593Smuzhiyun /* WS4: -------\_______________/--------- */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun static const int tsl1[8] = { 63*4882a593Smuzhiyun 1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 | 64*4882a593Smuzhiyun 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_LF_A1, 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun 1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 | 67*4882a593Smuzhiyun 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun 0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 | 70*4882a593Smuzhiyun 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun 0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 | 73*4882a593Smuzhiyun 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun 1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 | 76*4882a593Smuzhiyun 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0, 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun 1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 79*4882a593Smuzhiyun 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0, 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 | 82*4882a593Smuzhiyun 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0, 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun 0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * TSL_DIS_A1 | 85*4882a593Smuzhiyun 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | TSL_SF_A1 | TSL_EOS, 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun static const int tsl2[8] = { 89*4882a593Smuzhiyun 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_LF_A2, 90*4882a593Smuzhiyun 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2, 91*4882a593Smuzhiyun 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2, 92*4882a593Smuzhiyun 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2, 93*4882a593Smuzhiyun 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2, 94*4882a593Smuzhiyun 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2, 95*4882a593Smuzhiyun 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2, 96*4882a593Smuzhiyun 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2 | TSL_EOS 97*4882a593Smuzhiyun }; 98