1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /*************************************************************************** 3*4882a593Smuzhiyun * WT register offsets. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Wed Oct 22 13:50:20 2003 6*4882a593Smuzhiyun * Copyright 2003 mjander 7*4882a593Smuzhiyun * mjander@users.sourceforge.org 8*4882a593Smuzhiyun ****************************************************************************/ 9*4882a593Smuzhiyun #ifndef _AU88X0_WT_H 10*4882a593Smuzhiyun #define _AU88X0_WT_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* WT channels are grouped in banks. Each bank has 0x20 channels. */ 13*4882a593Smuzhiyun /* Bank register address boundary is 0x8000 */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define NR_WT_PB 0x20 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* WT bank base register (as dword address). */ 18*4882a593Smuzhiyun #define WT_BAR(x) (((x)&0xffe0)<<0x8) 19*4882a593Smuzhiyun #define WT_BANK(x) (x>>5) 20*4882a593Smuzhiyun /* WT Bank registers */ 21*4882a593Smuzhiyun #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */ 22*4882a593Smuzhiyun #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */ 23*4882a593Smuzhiyun #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */ 24*4882a593Smuzhiyun #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */ 25*4882a593Smuzhiyun #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */ 26*4882a593Smuzhiyun #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */ 27*4882a593Smuzhiyun /* WT Voice registers */ 28*4882a593Smuzhiyun #define WT_STEREO(voice) ((WT_BAR(voice)+ 0x20 +(((voice)&0x1f)>>1))<<2) /* 0x0080 */ 29*4882a593Smuzhiyun #define WT_MUTE(voice) ((WT_BAR(voice)+ 0x40 +((voice)&0x1f))<<2) /* 0x0100 */ 30*4882a593Smuzhiyun #define WT_RUN(voice) ((WT_BAR(voice)+ 0x60 +((voice)&0x1f))<<2) /* 0x0180 */ 31*4882a593Smuzhiyun /* Some kind of parameters. */ 32*4882a593Smuzhiyun /* PARM0, PARM1 : Filter (0xFF000000), SampleRate (0x0000FFFF) */ 33*4882a593Smuzhiyun /* PARM2, PARM3 : Still unknown */ 34*4882a593Smuzhiyun #define WT_PARM(x,y) (((WT_BAR(x))+ 0x80 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0200 */ 35*4882a593Smuzhiyun #define WT_DELAY(x,y) (((WT_BAR(x))+ 0x100 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0400 */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Numeric indexes used by SetReg() and GetReg() */ 38*4882a593Smuzhiyun #if 0 39*4882a593Smuzhiyun enum { 40*4882a593Smuzhiyun run = 0, /* 0 W 1:run 0:stop */ 41*4882a593Smuzhiyun parm0, /* 1 W filter, samplerate */ 42*4882a593Smuzhiyun parm1, /* 2 W filter, samplerate */ 43*4882a593Smuzhiyun parm2, /* 3 W */ 44*4882a593Smuzhiyun parm3, /* 4 RW volume. This value is calculated using floating point ops. */ 45*4882a593Smuzhiyun sramp, /* 5 W */ 46*4882a593Smuzhiyun mute, /* 6 W 1:mute, 0:unmute */ 47*4882a593Smuzhiyun gmode, /* 7 RO Looks like only bit0 is used. */ 48*4882a593Smuzhiyun aramp, /* 8 W */ 49*4882a593Smuzhiyun mramp, /* 9 W */ 50*4882a593Smuzhiyun ctrl, /* a W */ 51*4882a593Smuzhiyun delay, /* b W All 4 values are written at once with same value. */ 52*4882a593Smuzhiyun dsreg, /* c (R)W */ 53*4882a593Smuzhiyun } wt_reg; 54*4882a593Smuzhiyun #endif 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun typedef struct { 57*4882a593Smuzhiyun u32 parm0; /* this_1E4 */ 58*4882a593Smuzhiyun u32 parm1; /* this_1E8 */ 59*4882a593Smuzhiyun u32 parm2; /* this_1EC */ 60*4882a593Smuzhiyun u32 parm3; /* this_1F0 */ 61*4882a593Smuzhiyun u32 this_1D0; 62*4882a593Smuzhiyun } wt_voice_t; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* _AU88X0_WT_H */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* End of file */ 67