1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __SOUND_AU88X0_H 6*4882a593Smuzhiyun #define __SOUND_AU88X0_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/pci.h> 9*4882a593Smuzhiyun #include <linux/io.h> 10*4882a593Smuzhiyun #include <sound/core.h> 11*4882a593Smuzhiyun #include <sound/pcm.h> 12*4882a593Smuzhiyun #include <sound/rawmidi.h> 13*4882a593Smuzhiyun #include <sound/mpu401.h> 14*4882a593Smuzhiyun #include <sound/hwdep.h> 15*4882a593Smuzhiyun #include <sound/ac97_codec.h> 16*4882a593Smuzhiyun #include <sound/tlv.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef CHIP_AU8820 19*4882a593Smuzhiyun #include "au88x0_eq.h" 20*4882a593Smuzhiyun #include "au88x0_a3d.h" 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun #ifndef CHIP_AU8810 23*4882a593Smuzhiyun #include "au88x0_wt.h" 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define hwread(x,y) readl((x)+(y)) 27*4882a593Smuzhiyun #define hwwrite(x,y,z) writel((z),(x)+(y)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Vortex MPU401 defines. */ 30*4882a593Smuzhiyun #define MIDI_CLOCK_DIV 0x61 31*4882a593Smuzhiyun /* Standart MPU401 defines. */ 32*4882a593Smuzhiyun #define MPU401_RESET 0xff 33*4882a593Smuzhiyun #define MPU401_ENTER_UART 0x3f 34*4882a593Smuzhiyun #define MPU401_ACK 0xfe 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun // Get src register value to convert from x to y. 37*4882a593Smuzhiyun #define SRC_RATIO(x,y) ((((x<<15)/y) + 1)/2) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* FIFO software state constants. */ 40*4882a593Smuzhiyun #define FIFO_STOP 0 41*4882a593Smuzhiyun #define FIFO_START 1 42*4882a593Smuzhiyun #define FIFO_PAUSE 2 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* IRQ flags */ 45*4882a593Smuzhiyun #define IRQ_ERR_MASK 0x00ff 46*4882a593Smuzhiyun #define IRQ_FATAL 0x0001 47*4882a593Smuzhiyun #define IRQ_PARITY 0x0002 48*4882a593Smuzhiyun #define IRQ_REG 0x0004 49*4882a593Smuzhiyun #define IRQ_FIFO 0x0008 50*4882a593Smuzhiyun #define IRQ_DMA 0x0010 51*4882a593Smuzhiyun #define IRQ_PCMOUT 0x0020 /* PCM OUT page crossing */ 52*4882a593Smuzhiyun #define IRQ_TIMER 0x1000 53*4882a593Smuzhiyun #define IRQ_MIDI 0x2000 54*4882a593Smuzhiyun #define IRQ_MODEM 0x4000 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* ADB Resource */ 57*4882a593Smuzhiyun #define VORTEX_RESOURCE_DMA 0x00000000 58*4882a593Smuzhiyun #define VORTEX_RESOURCE_SRC 0x00000001 59*4882a593Smuzhiyun #define VORTEX_RESOURCE_MIXIN 0x00000002 60*4882a593Smuzhiyun #define VORTEX_RESOURCE_MIXOUT 0x00000003 61*4882a593Smuzhiyun #define VORTEX_RESOURCE_A3D 0x00000004 62*4882a593Smuzhiyun #define VORTEX_RESOURCE_LAST 0x00000005 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* codec io: VORTEX_CODEC_IO bits */ 65*4882a593Smuzhiyun #define VORTEX_CODEC_ID_SHIFT 24 66*4882a593Smuzhiyun #define VORTEX_CODEC_WRITE 0x00800000 67*4882a593Smuzhiyun #define VORTEX_CODEC_ADDSHIFT 16 68*4882a593Smuzhiyun #define VORTEX_CODEC_ADDMASK 0x7f0000 69*4882a593Smuzhiyun #define VORTEX_CODEC_DATSHIFT 0 70*4882a593Smuzhiyun #define VORTEX_CODEC_DATMASK 0xffff 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Check for SDAC bit in "Extended audio ID" AC97 register */ 73*4882a593Smuzhiyun //#define VORTEX_IS_QUAD(x) (((x)->codec == NULL) ? 0 : ((x)->codec->ext_id&0x80)) 74*4882a593Smuzhiyun #define VORTEX_IS_QUAD(x) ((x)->isquad) 75*4882a593Smuzhiyun /* Check if chip has bug. */ 76*4882a593Smuzhiyun #define IS_BAD_CHIP(x) (\ 77*4882a593Smuzhiyun (x->rev == 0xfe && x->device == PCI_DEVICE_ID_AUREAL_VORTEX_2) || \ 78*4882a593Smuzhiyun (x->rev == 0xfe && x->device == PCI_DEVICE_ID_AUREAL_ADVANTAGE)) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* PCM devices */ 82*4882a593Smuzhiyun #define VORTEX_PCM_ADB 0 83*4882a593Smuzhiyun #define VORTEX_PCM_SPDIF 1 84*4882a593Smuzhiyun #define VORTEX_PCM_A3D 2 85*4882a593Smuzhiyun #define VORTEX_PCM_WT 3 86*4882a593Smuzhiyun #define VORTEX_PCM_I2S 4 87*4882a593Smuzhiyun #define VORTEX_PCM_LAST 5 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define MIX_CAPT(x) (vortex->mixcapt[x]) 90*4882a593Smuzhiyun #define MIX_PLAYB(x) (vortex->mixplayb[x]) 91*4882a593Smuzhiyun #define MIX_SPDIF(x) (vortex->mixspdif[x]) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define NR_WTPB 0x20 /* WT channels per each bank. */ 94*4882a593Smuzhiyun #define NR_PCM 0x10 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct pcm_vol { 97*4882a593Smuzhiyun struct snd_kcontrol *kctl; 98*4882a593Smuzhiyun int active; 99*4882a593Smuzhiyun int dma; 100*4882a593Smuzhiyun int mixin[4]; 101*4882a593Smuzhiyun int vol[4]; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Structs */ 105*4882a593Smuzhiyun typedef struct { 106*4882a593Smuzhiyun //int this_08; /* Still unknown */ 107*4882a593Smuzhiyun int fifo_enabled; /* this_24 */ 108*4882a593Smuzhiyun int fifo_status; /* this_1c */ 109*4882a593Smuzhiyun u32 dma_ctrl; /* this_78 (ADB), this_7c (WT) */ 110*4882a593Smuzhiyun int dma_unknown; /* this_74 (ADB), this_78 (WT). WDM: +8 */ 111*4882a593Smuzhiyun int cfg0; 112*4882a593Smuzhiyun int cfg1; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun int nr_ch; /* Nr of PCM channels in use */ 115*4882a593Smuzhiyun int type; /* Output type (ac97, a3d, spdif, i2s, dsp) */ 116*4882a593Smuzhiyun int dma; /* Hardware DMA index. */ 117*4882a593Smuzhiyun int dir; /* Stream Direction. */ 118*4882a593Smuzhiyun u32 resources[5]; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Virtual page extender stuff */ 121*4882a593Smuzhiyun int nr_periods; 122*4882a593Smuzhiyun int period_bytes; 123*4882a593Smuzhiyun int period_real; 124*4882a593Smuzhiyun int period_virt; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun struct snd_pcm_substream *substream; 127*4882a593Smuzhiyun } stream_t; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun typedef struct snd_vortex vortex_t; 130*4882a593Smuzhiyun struct snd_vortex { 131*4882a593Smuzhiyun /* ALSA structs. */ 132*4882a593Smuzhiyun struct snd_card *card; 133*4882a593Smuzhiyun struct snd_pcm *pcm[VORTEX_PCM_LAST]; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun struct snd_rawmidi *rmidi; /* Legacy Midi interface. */ 136*4882a593Smuzhiyun struct snd_ac97 *codec; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* Stream structs. */ 139*4882a593Smuzhiyun stream_t dma_adb[NR_ADB]; 140*4882a593Smuzhiyun int spdif_sr; 141*4882a593Smuzhiyun #ifndef CHIP_AU8810 142*4882a593Smuzhiyun stream_t dma_wt[NR_WT]; 143*4882a593Smuzhiyun wt_voice_t wt_voice[NR_WT]; /* WT register cache. */ 144*4882a593Smuzhiyun s8 mixwt[(NR_WT / NR_WTPB) * 6]; /* WT mixin objects */ 145*4882a593Smuzhiyun #endif 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* Global resources */ 148*4882a593Smuzhiyun s8 mixcapt[2]; 149*4882a593Smuzhiyun s8 mixplayb[4]; 150*4882a593Smuzhiyun #ifndef CHIP_AU8820 151*4882a593Smuzhiyun s8 mixspdif[2]; 152*4882a593Smuzhiyun s8 mixa3d[2]; /* mixers which collect all a3d streams. */ 153*4882a593Smuzhiyun s8 mixxtlk[2]; /* crosstalk canceler mixer inputs. */ 154*4882a593Smuzhiyun #endif 155*4882a593Smuzhiyun u32 fixed_res[5]; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #ifndef CHIP_AU8820 158*4882a593Smuzhiyun /* Hardware equalizer structs */ 159*4882a593Smuzhiyun eqlzr_t eq; 160*4882a593Smuzhiyun /* A3D structs */ 161*4882a593Smuzhiyun a3dsrc_t a3d[NR_A3D]; 162*4882a593Smuzhiyun /* Xtalk canceler */ 163*4882a593Smuzhiyun int xt_mode; /* 1: speakers, 0:headphones. */ 164*4882a593Smuzhiyun #endif 165*4882a593Smuzhiyun struct pcm_vol pcm_vol[NR_PCM]; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun int isquad; /* cache of extended ID codec flag. */ 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* Gameport stuff. */ 170*4882a593Smuzhiyun struct gameport *gameport; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* PCI hardware resources */ 173*4882a593Smuzhiyun unsigned long io; 174*4882a593Smuzhiyun void __iomem *mmio; 175*4882a593Smuzhiyun unsigned int irq; 176*4882a593Smuzhiyun spinlock_t lock; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* PCI device */ 179*4882a593Smuzhiyun struct pci_dev *pci_dev; 180*4882a593Smuzhiyun u16 vendor; 181*4882a593Smuzhiyun u16 device; 182*4882a593Smuzhiyun u8 rev; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* Functions. */ 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* SRC */ 188*4882a593Smuzhiyun static void vortex_adb_setsrc(vortex_t * vortex, int adbdma, 189*4882a593Smuzhiyun unsigned int cvrt, int dir); 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* DMA Engines. */ 192*4882a593Smuzhiyun static void vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma, 193*4882a593Smuzhiyun int size, int count); 194*4882a593Smuzhiyun static void vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, 195*4882a593Smuzhiyun int dir, int fmt, int d, 196*4882a593Smuzhiyun u32 offset); 197*4882a593Smuzhiyun static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb); 198*4882a593Smuzhiyun #ifndef CHIP_AU8810 199*4882a593Smuzhiyun static void vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma, 200*4882a593Smuzhiyun int size, int count); 201*4882a593Smuzhiyun static void vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d, /*int e, */ 202*4882a593Smuzhiyun u32 offset); 203*4882a593Smuzhiyun static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb); 204*4882a593Smuzhiyun #endif 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma); 207*4882a593Smuzhiyun //static void vortex_adbdma_stopfifo(vortex_t *vortex, int adbdma); 208*4882a593Smuzhiyun static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma); 209*4882a593Smuzhiyun static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma); 210*4882a593Smuzhiyun static inline int vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma); 211*4882a593Smuzhiyun static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma); 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #ifndef CHIP_AU8810 214*4882a593Smuzhiyun static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma); 215*4882a593Smuzhiyun static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma); 216*4882a593Smuzhiyun static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma); 217*4882a593Smuzhiyun static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma); 218*4882a593Smuzhiyun static inline int vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma); 219*4882a593Smuzhiyun #endif 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* global stuff. */ 222*4882a593Smuzhiyun static void vortex_codec_init(vortex_t * vortex); 223*4882a593Smuzhiyun static void vortex_codec_write(struct snd_ac97 * codec, unsigned short addr, 224*4882a593Smuzhiyun unsigned short data); 225*4882a593Smuzhiyun static unsigned short vortex_codec_read(struct snd_ac97 * codec, unsigned short addr); 226*4882a593Smuzhiyun static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode); 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun static int vortex_core_init(vortex_t * card); 229*4882a593Smuzhiyun static int vortex_core_shutdown(vortex_t * card); 230*4882a593Smuzhiyun static void vortex_enable_int(vortex_t * card); 231*4882a593Smuzhiyun static irqreturn_t vortex_interrupt(int irq, void *dev_id); 232*4882a593Smuzhiyun static int vortex_alsafmt_aspfmt(snd_pcm_format_t alsafmt, vortex_t *v); 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* Connection stuff. */ 235*4882a593Smuzhiyun static void vortex_connect_default(vortex_t * vortex, int en); 236*4882a593Smuzhiyun static int vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, 237*4882a593Smuzhiyun int dir, int type, int subdev); 238*4882a593Smuzhiyun static int vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, 239*4882a593Smuzhiyun int restype); 240*4882a593Smuzhiyun #ifndef CHIP_AU8810 241*4882a593Smuzhiyun static int vortex_wt_allocroute(vortex_t * vortex, int dma, int nr_ch); 242*4882a593Smuzhiyun static void vortex_wt_connect(vortex_t * vortex, int en); 243*4882a593Smuzhiyun static void vortex_wt_init(vortex_t * vortex); 244*4882a593Smuzhiyun #endif 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun static void vortex_route(vortex_t * vortex, int en, unsigned char channel, 247*4882a593Smuzhiyun unsigned char source, unsigned char dest); 248*4882a593Smuzhiyun #if 0 249*4882a593Smuzhiyun static void vortex_routes(vortex_t * vortex, int en, unsigned char channel, 250*4882a593Smuzhiyun unsigned char source, unsigned char dest0, 251*4882a593Smuzhiyun unsigned char dest1); 252*4882a593Smuzhiyun #endif 253*4882a593Smuzhiyun static void vortex_connection_mixin_mix(vortex_t * vortex, int en, 254*4882a593Smuzhiyun unsigned char mixin, 255*4882a593Smuzhiyun unsigned char mix, int a); 256*4882a593Smuzhiyun static void vortex_mix_setinputvolumebyte(vortex_t * vortex, 257*4882a593Smuzhiyun unsigned char mix, int mixin, 258*4882a593Smuzhiyun unsigned char vol); 259*4882a593Smuzhiyun static void vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix, 260*4882a593Smuzhiyun unsigned char vol); 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun /* A3D functions. */ 263*4882a593Smuzhiyun #ifndef CHIP_AU8820 264*4882a593Smuzhiyun static void vortex_Vort3D_enable(vortex_t * v); 265*4882a593Smuzhiyun static void vortex_Vort3D_disable(vortex_t * v); 266*4882a593Smuzhiyun static void vortex_Vort3D_connect(vortex_t * vortex, int en); 267*4882a593Smuzhiyun static void vortex_Vort3D_InitializeSource(a3dsrc_t *a, int en, vortex_t *v); 268*4882a593Smuzhiyun #endif 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun /* Driver stuff. */ 271*4882a593Smuzhiyun static int vortex_gameport_register(vortex_t * card); 272*4882a593Smuzhiyun static void vortex_gameport_unregister(vortex_t * card); 273*4882a593Smuzhiyun #ifndef CHIP_AU8820 274*4882a593Smuzhiyun static int vortex_eq_init(vortex_t * vortex); 275*4882a593Smuzhiyun static int vortex_eq_free(vortex_t * vortex); 276*4882a593Smuzhiyun #endif 277*4882a593Smuzhiyun /* ALSA stuff. */ 278*4882a593Smuzhiyun static int snd_vortex_new_pcm(vortex_t * vortex, int idx, int nr); 279*4882a593Smuzhiyun static int snd_vortex_mixer(vortex_t * vortex); 280*4882a593Smuzhiyun static int snd_vortex_midi(vortex_t * vortex); 281*4882a593Smuzhiyun #endif 282