1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ALSA driver for ATI IXP 150/200/250 AC97 modem controllers
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/pci.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/mutex.h>
16*4882a593Smuzhiyun #include <sound/core.h>
17*4882a593Smuzhiyun #include <sound/pcm.h>
18*4882a593Smuzhiyun #include <sound/pcm_params.h>
19*4882a593Smuzhiyun #include <sound/info.h>
20*4882a593Smuzhiyun #include <sound/ac97_codec.h>
21*4882a593Smuzhiyun #include <sound/initval.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
24*4882a593Smuzhiyun MODULE_DESCRIPTION("ATI IXP MC97 controller");
25*4882a593Smuzhiyun MODULE_LICENSE("GPL");
26*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250}}");
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static int index = -2; /* Exclude the first card */
29*4882a593Smuzhiyun static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
30*4882a593Smuzhiyun static int ac97_clock = 48000;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun module_param(index, int, 0444);
33*4882a593Smuzhiyun MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
34*4882a593Smuzhiyun module_param(id, charp, 0444);
35*4882a593Smuzhiyun MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
36*4882a593Smuzhiyun module_param(ac97_clock, int, 0444);
37*4882a593Smuzhiyun MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* just for backward compatibility */
40*4882a593Smuzhiyun static bool enable;
41*4882a593Smuzhiyun module_param(enable, bool, 0444);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define ATI_REG_ISR 0x00 /* interrupt source */
48*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_IN_XRUN (1U<<0)
49*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_IN_STATUS (1U<<1)
50*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_OUT1_XRUN (1U<<2)
51*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_OUT1_STATUS (1U<<3)
52*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_OUT2_XRUN (1U<<4)
53*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_OUT2_STATUS (1U<<5)
54*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_OUT3_XRUN (1U<<6)
55*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_OUT3_STATUS (1U<<7)
56*4882a593Smuzhiyun #define ATI_REG_ISR_PHYS_INTR (1U<<8)
57*4882a593Smuzhiyun #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
58*4882a593Smuzhiyun #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
59*4882a593Smuzhiyun #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
60*4882a593Smuzhiyun #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
61*4882a593Smuzhiyun #define ATI_REG_ISR_NEW_FRAME (1U<<13)
62*4882a593Smuzhiyun #define ATI_REG_ISR_MODEM_GPIO_DATA (1U<<14)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define ATI_REG_IER 0x04 /* interrupt enable */
65*4882a593Smuzhiyun #define ATI_REG_IER_MODEM_IN_XRUN_EN (1U<<0)
66*4882a593Smuzhiyun #define ATI_REG_IER_MODEM_STATUS_EN (1U<<1)
67*4882a593Smuzhiyun #define ATI_REG_IER_MODEM_OUT1_XRUN_EN (1U<<2)
68*4882a593Smuzhiyun #define ATI_REG_IER_MODEM_OUT2_XRUN_EN (1U<<4)
69*4882a593Smuzhiyun #define ATI_REG_IER_MODEM_OUT3_XRUN_EN (1U<<6)
70*4882a593Smuzhiyun #define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
71*4882a593Smuzhiyun #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
72*4882a593Smuzhiyun #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
73*4882a593Smuzhiyun #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
74*4882a593Smuzhiyun #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
75*4882a593Smuzhiyun #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
76*4882a593Smuzhiyun #define ATI_REG_IER_MODEM_GPIO_DATA_EN (1U<<14) /* (WO) modem is running */
77*4882a593Smuzhiyun #define ATI_REG_IER_MODEM_SET_BUS_BUSY (1U<<15)
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define ATI_REG_CMD 0x08 /* command */
80*4882a593Smuzhiyun #define ATI_REG_CMD_POWERDOWN (1U<<0)
81*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_RECEIVE_EN (1U<<1) /* modem only */
82*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_SEND1_EN (1U<<2) /* modem only */
83*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_SEND2_EN (1U<<3) /* modem only */
84*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_SEND3_EN (1U<<4) /* modem only */
85*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_STATUS_MEM (1U<<5) /* modem only */
86*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_IN_DMA_EN (1U<<8) /* modem only */
87*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_OUT_DMA1_EN (1U<<9) /* modem only */
88*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_OUT_DMA2_EN (1U<<10) /* modem only */
89*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_OUT_DMA3_EN (1U<<11) /* modem only */
90*4882a593Smuzhiyun #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
91*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_GPIO_THRU_DMA (1U<<22) /* modem only */
92*4882a593Smuzhiyun #define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
93*4882a593Smuzhiyun #define ATI_REG_CMD_PACKED_DIS (1U<<24)
94*4882a593Smuzhiyun #define ATI_REG_CMD_BURST_EN (1U<<25)
95*4882a593Smuzhiyun #define ATI_REG_CMD_PANIC_EN (1U<<26)
96*4882a593Smuzhiyun #define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
97*4882a593Smuzhiyun #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
98*4882a593Smuzhiyun #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
99*4882a593Smuzhiyun #define ATI_REG_CMD_AC_SYNC (1U<<30)
100*4882a593Smuzhiyun #define ATI_REG_CMD_AC_RESET (1U<<31)
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #define ATI_REG_PHYS_OUT_ADDR 0x0c
103*4882a593Smuzhiyun #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
104*4882a593Smuzhiyun #define ATI_REG_PHYS_OUT_RW (1U<<2)
105*4882a593Smuzhiyun #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
106*4882a593Smuzhiyun #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
107*4882a593Smuzhiyun #define ATI_REG_PHYS_OUT_DATA_SHIFT 16
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #define ATI_REG_PHYS_IN_ADDR 0x10
110*4882a593Smuzhiyun #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
111*4882a593Smuzhiyun #define ATI_REG_PHYS_IN_ADDR_SHIFT 9
112*4882a593Smuzhiyun #define ATI_REG_PHYS_IN_DATA_SHIFT 16
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #define ATI_REG_SLOTREQ 0x14
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun #define ATI_REG_COUNTER 0x18
117*4882a593Smuzhiyun #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
118*4882a593Smuzhiyun #define ATI_REG_COUNTER_BITCLOCK (31U<<8)
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #define ATI_REG_MODEM_IN_DMA_LINKPTR 0x20
123*4882a593Smuzhiyun #define ATI_REG_MODEM_IN_DMA_DT_START 0x24 /* RO */
124*4882a593Smuzhiyun #define ATI_REG_MODEM_IN_DMA_DT_NEXT 0x28 /* RO */
125*4882a593Smuzhiyun #define ATI_REG_MODEM_IN_DMA_DT_CUR 0x2c /* RO */
126*4882a593Smuzhiyun #define ATI_REG_MODEM_IN_DMA_DT_SIZE 0x30
127*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_FIFO 0x34 /* output threshold */
128*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK (0xf<<16)
129*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT 16
130*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA1_LINKPTR 0x38
131*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA2_LINKPTR 0x3c
132*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA3_LINKPTR 0x40
133*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA1_DT_START 0x44
134*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA1_DT_NEXT 0x48
135*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA1_DT_CUR 0x4c
136*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA2_DT_START 0x50
137*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA2_DT_NEXT 0x54
138*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA2_DT_CUR 0x58
139*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA3_DT_START 0x5c
140*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA3_DT_NEXT 0x60
141*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA3_DT_CUR 0x64
142*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA12_DT_SIZE 0x68
143*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_DMA3_DT_SIZE 0x6c
144*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_FIFO_USED 0x70
145*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_GPIO 0x74
146*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_GPIO_EN 1
147*4882a593Smuzhiyun #define ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT 5
148*4882a593Smuzhiyun #define ATI_REG_MODEM_IN_GPIO 0x78
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun #define ATI_REG_MODEM_MIRROR 0x7c
151*4882a593Smuzhiyun #define ATI_REG_AUDIO_MIRROR 0x80
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun #define ATI_REG_MODEM_FIFO_FLUSH 0x88
154*4882a593Smuzhiyun #define ATI_REG_MODEM_FIFO_OUT1_FLUSH (1U<<0)
155*4882a593Smuzhiyun #define ATI_REG_MODEM_FIFO_OUT2_FLUSH (1U<<1)
156*4882a593Smuzhiyun #define ATI_REG_MODEM_FIFO_OUT3_FLUSH (1U<<2)
157*4882a593Smuzhiyun #define ATI_REG_MODEM_FIFO_IN_FLUSH (1U<<3)
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* LINKPTR */
160*4882a593Smuzhiyun #define ATI_REG_LINKPTR_EN (1U<<0)
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun struct atiixp_modem;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /*
168*4882a593Smuzhiyun * DMA packate descriptor
169*4882a593Smuzhiyun */
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun struct atiixp_dma_desc {
172*4882a593Smuzhiyun __le32 addr; /* DMA buffer address */
173*4882a593Smuzhiyun u16 status; /* status bits */
174*4882a593Smuzhiyun u16 size; /* size of the packet in dwords */
175*4882a593Smuzhiyun __le32 next; /* address of the next packet descriptor */
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /*
179*4882a593Smuzhiyun * stream enum
180*4882a593Smuzhiyun */
181*4882a593Smuzhiyun enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, NUM_ATI_DMAS }; /* DMAs */
182*4882a593Smuzhiyun enum { ATI_PCM_OUT, ATI_PCM_IN, NUM_ATI_PCMS }; /* AC97 pcm slots */
183*4882a593Smuzhiyun enum { ATI_PCMDEV_ANALOG, NUM_ATI_PCMDEVS }; /* pcm devices */
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun #define NUM_ATI_CODECS 3
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /*
189*4882a593Smuzhiyun * constants and callbacks for each DMA type
190*4882a593Smuzhiyun */
191*4882a593Smuzhiyun struct atiixp_dma_ops {
192*4882a593Smuzhiyun int type; /* ATI_DMA_XXX */
193*4882a593Smuzhiyun unsigned int llp_offset; /* LINKPTR offset */
194*4882a593Smuzhiyun unsigned int dt_cur; /* DT_CUR offset */
195*4882a593Smuzhiyun /* called from open callback */
196*4882a593Smuzhiyun void (*enable_dma)(struct atiixp_modem *chip, int on);
197*4882a593Smuzhiyun /* called from trigger (START/STOP) */
198*4882a593Smuzhiyun void (*enable_transfer)(struct atiixp_modem *chip, int on);
199*4882a593Smuzhiyun /* called from trigger (STOP only) */
200*4882a593Smuzhiyun void (*flush_dma)(struct atiixp_modem *chip);
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /*
204*4882a593Smuzhiyun * DMA stream
205*4882a593Smuzhiyun */
206*4882a593Smuzhiyun struct atiixp_dma {
207*4882a593Smuzhiyun const struct atiixp_dma_ops *ops;
208*4882a593Smuzhiyun struct snd_dma_buffer desc_buf;
209*4882a593Smuzhiyun struct snd_pcm_substream *substream; /* assigned PCM substream */
210*4882a593Smuzhiyun unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
211*4882a593Smuzhiyun unsigned int period_bytes, periods;
212*4882a593Smuzhiyun int opened;
213*4882a593Smuzhiyun int running;
214*4882a593Smuzhiyun int pcm_open_flag;
215*4882a593Smuzhiyun int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /*
219*4882a593Smuzhiyun * ATI IXP chip
220*4882a593Smuzhiyun */
221*4882a593Smuzhiyun struct atiixp_modem {
222*4882a593Smuzhiyun struct snd_card *card;
223*4882a593Smuzhiyun struct pci_dev *pci;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun struct resource *res; /* memory i/o */
226*4882a593Smuzhiyun unsigned long addr;
227*4882a593Smuzhiyun void __iomem *remap_addr;
228*4882a593Smuzhiyun int irq;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun struct snd_ac97_bus *ac97_bus;
231*4882a593Smuzhiyun struct snd_ac97 *ac97[NUM_ATI_CODECS];
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun spinlock_t reg_lock;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun struct atiixp_dma dmas[NUM_ATI_DMAS];
236*4882a593Smuzhiyun struct ac97_pcm *pcms[NUM_ATI_PCMS];
237*4882a593Smuzhiyun struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun int max_channels; /* max. channels for PCM out */
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun unsigned int codec_not_ready_bits; /* for codec detection */
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun int spdif_over_aclink; /* passed from the module option */
244*4882a593Smuzhiyun struct mutex open_mutex; /* playback open mutex */
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /*
249*4882a593Smuzhiyun */
250*4882a593Smuzhiyun static const struct pci_device_id snd_atiixp_ids[] = {
251*4882a593Smuzhiyun { PCI_VDEVICE(ATI, 0x434d), 0 }, /* SB200 */
252*4882a593Smuzhiyun { PCI_VDEVICE(ATI, 0x4378), 0 }, /* SB400 */
253*4882a593Smuzhiyun { 0, }
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun /*
260*4882a593Smuzhiyun * lowlevel functions
261*4882a593Smuzhiyun */
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /*
264*4882a593Smuzhiyun * update the bits of the given register.
265*4882a593Smuzhiyun * return 1 if the bits changed.
266*4882a593Smuzhiyun */
snd_atiixp_update_bits(struct atiixp_modem * chip,unsigned int reg,unsigned int mask,unsigned int value)267*4882a593Smuzhiyun static int snd_atiixp_update_bits(struct atiixp_modem *chip, unsigned int reg,
268*4882a593Smuzhiyun unsigned int mask, unsigned int value)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun void __iomem *addr = chip->remap_addr + reg;
271*4882a593Smuzhiyun unsigned int data, old_data;
272*4882a593Smuzhiyun old_data = data = readl(addr);
273*4882a593Smuzhiyun data &= ~mask;
274*4882a593Smuzhiyun data |= value;
275*4882a593Smuzhiyun if (old_data == data)
276*4882a593Smuzhiyun return 0;
277*4882a593Smuzhiyun writel(data, addr);
278*4882a593Smuzhiyun return 1;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /*
282*4882a593Smuzhiyun * macros for easy use
283*4882a593Smuzhiyun */
284*4882a593Smuzhiyun #define atiixp_write(chip,reg,value) \
285*4882a593Smuzhiyun writel(value, chip->remap_addr + ATI_REG_##reg)
286*4882a593Smuzhiyun #define atiixp_read(chip,reg) \
287*4882a593Smuzhiyun readl(chip->remap_addr + ATI_REG_##reg)
288*4882a593Smuzhiyun #define atiixp_update(chip,reg,mask,val) \
289*4882a593Smuzhiyun snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /*
292*4882a593Smuzhiyun * handling DMA packets
293*4882a593Smuzhiyun *
294*4882a593Smuzhiyun * we allocate a linear buffer for the DMA, and split it to each packet.
295*4882a593Smuzhiyun * in a future version, a scatter-gather buffer should be implemented.
296*4882a593Smuzhiyun */
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun #define ATI_DESC_LIST_SIZE \
299*4882a593Smuzhiyun PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /*
302*4882a593Smuzhiyun * build packets ring for the given buffer size.
303*4882a593Smuzhiyun *
304*4882a593Smuzhiyun * IXP handles the buffer descriptors, which are connected as a linked
305*4882a593Smuzhiyun * list. although we can change the list dynamically, in this version,
306*4882a593Smuzhiyun * a static RING of buffer descriptors is used.
307*4882a593Smuzhiyun *
308*4882a593Smuzhiyun * the ring is built in this function, and is set up to the hardware.
309*4882a593Smuzhiyun */
atiixp_build_dma_packets(struct atiixp_modem * chip,struct atiixp_dma * dma,struct snd_pcm_substream * substream,unsigned int periods,unsigned int period_bytes)310*4882a593Smuzhiyun static int atiixp_build_dma_packets(struct atiixp_modem *chip,
311*4882a593Smuzhiyun struct atiixp_dma *dma,
312*4882a593Smuzhiyun struct snd_pcm_substream *substream,
313*4882a593Smuzhiyun unsigned int periods,
314*4882a593Smuzhiyun unsigned int period_bytes)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun unsigned int i;
317*4882a593Smuzhiyun u32 addr, desc_addr;
318*4882a593Smuzhiyun unsigned long flags;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun if (periods > ATI_MAX_DESCRIPTORS)
321*4882a593Smuzhiyun return -ENOMEM;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun if (dma->desc_buf.area == NULL) {
324*4882a593Smuzhiyun if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
325*4882a593Smuzhiyun ATI_DESC_LIST_SIZE, &dma->desc_buf) < 0)
326*4882a593Smuzhiyun return -ENOMEM;
327*4882a593Smuzhiyun dma->period_bytes = dma->periods = 0; /* clear */
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun if (dma->periods == periods && dma->period_bytes == period_bytes)
331*4882a593Smuzhiyun return 0;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /* reset DMA before changing the descriptor table */
334*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
335*4882a593Smuzhiyun writel(0, chip->remap_addr + dma->ops->llp_offset);
336*4882a593Smuzhiyun dma->ops->enable_dma(chip, 0);
337*4882a593Smuzhiyun dma->ops->enable_dma(chip, 1);
338*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun /* fill the entries */
341*4882a593Smuzhiyun addr = (u32)substream->runtime->dma_addr;
342*4882a593Smuzhiyun desc_addr = (u32)dma->desc_buf.addr;
343*4882a593Smuzhiyun for (i = 0; i < periods; i++) {
344*4882a593Smuzhiyun struct atiixp_dma_desc *desc;
345*4882a593Smuzhiyun desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
346*4882a593Smuzhiyun desc->addr = cpu_to_le32(addr);
347*4882a593Smuzhiyun desc->status = 0;
348*4882a593Smuzhiyun desc->size = period_bytes >> 2; /* in dwords */
349*4882a593Smuzhiyun desc_addr += sizeof(struct atiixp_dma_desc);
350*4882a593Smuzhiyun if (i == periods - 1)
351*4882a593Smuzhiyun desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
352*4882a593Smuzhiyun else
353*4882a593Smuzhiyun desc->next = cpu_to_le32(desc_addr);
354*4882a593Smuzhiyun addr += period_bytes;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
358*4882a593Smuzhiyun chip->remap_addr + dma->ops->llp_offset);
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun dma->period_bytes = period_bytes;
361*4882a593Smuzhiyun dma->periods = periods;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun return 0;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /*
367*4882a593Smuzhiyun * remove the ring buffer and release it if assigned
368*4882a593Smuzhiyun */
atiixp_clear_dma_packets(struct atiixp_modem * chip,struct atiixp_dma * dma,struct snd_pcm_substream * substream)369*4882a593Smuzhiyun static void atiixp_clear_dma_packets(struct atiixp_modem *chip,
370*4882a593Smuzhiyun struct atiixp_dma *dma,
371*4882a593Smuzhiyun struct snd_pcm_substream *substream)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun if (dma->desc_buf.area) {
374*4882a593Smuzhiyun writel(0, chip->remap_addr + dma->ops->llp_offset);
375*4882a593Smuzhiyun snd_dma_free_pages(&dma->desc_buf);
376*4882a593Smuzhiyun dma->desc_buf.area = NULL;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /*
381*4882a593Smuzhiyun * AC97 interface
382*4882a593Smuzhiyun */
snd_atiixp_acquire_codec(struct atiixp_modem * chip)383*4882a593Smuzhiyun static int snd_atiixp_acquire_codec(struct atiixp_modem *chip)
384*4882a593Smuzhiyun {
385*4882a593Smuzhiyun int timeout = 1000;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
388*4882a593Smuzhiyun if (! timeout--) {
389*4882a593Smuzhiyun dev_warn(chip->card->dev, "codec acquire timeout\n");
390*4882a593Smuzhiyun return -EBUSY;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun udelay(1);
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun return 0;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
snd_atiixp_codec_read(struct atiixp_modem * chip,unsigned short codec,unsigned short reg)397*4882a593Smuzhiyun static unsigned short snd_atiixp_codec_read(struct atiixp_modem *chip,
398*4882a593Smuzhiyun unsigned short codec,
399*4882a593Smuzhiyun unsigned short reg)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun unsigned int data;
402*4882a593Smuzhiyun int timeout;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun if (snd_atiixp_acquire_codec(chip) < 0)
405*4882a593Smuzhiyun return 0xffff;
406*4882a593Smuzhiyun data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
407*4882a593Smuzhiyun ATI_REG_PHYS_OUT_ADDR_EN |
408*4882a593Smuzhiyun ATI_REG_PHYS_OUT_RW |
409*4882a593Smuzhiyun codec;
410*4882a593Smuzhiyun atiixp_write(chip, PHYS_OUT_ADDR, data);
411*4882a593Smuzhiyun if (snd_atiixp_acquire_codec(chip) < 0)
412*4882a593Smuzhiyun return 0xffff;
413*4882a593Smuzhiyun timeout = 1000;
414*4882a593Smuzhiyun do {
415*4882a593Smuzhiyun data = atiixp_read(chip, PHYS_IN_ADDR);
416*4882a593Smuzhiyun if (data & ATI_REG_PHYS_IN_READ_FLAG)
417*4882a593Smuzhiyun return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
418*4882a593Smuzhiyun udelay(1);
419*4882a593Smuzhiyun } while (--timeout);
420*4882a593Smuzhiyun /* time out may happen during reset */
421*4882a593Smuzhiyun if (reg < 0x7c)
422*4882a593Smuzhiyun dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg);
423*4882a593Smuzhiyun return 0xffff;
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun
snd_atiixp_codec_write(struct atiixp_modem * chip,unsigned short codec,unsigned short reg,unsigned short val)427*4882a593Smuzhiyun static void snd_atiixp_codec_write(struct atiixp_modem *chip,
428*4882a593Smuzhiyun unsigned short codec,
429*4882a593Smuzhiyun unsigned short reg, unsigned short val)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun unsigned int data;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (snd_atiixp_acquire_codec(chip) < 0)
434*4882a593Smuzhiyun return;
435*4882a593Smuzhiyun data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
436*4882a593Smuzhiyun ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
437*4882a593Smuzhiyun ATI_REG_PHYS_OUT_ADDR_EN | codec;
438*4882a593Smuzhiyun atiixp_write(chip, PHYS_OUT_ADDR, data);
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun
snd_atiixp_ac97_read(struct snd_ac97 * ac97,unsigned short reg)442*4882a593Smuzhiyun static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
443*4882a593Smuzhiyun unsigned short reg)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun struct atiixp_modem *chip = ac97->private_data;
446*4882a593Smuzhiyun return snd_atiixp_codec_read(chip, ac97->num, reg);
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
snd_atiixp_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)450*4882a593Smuzhiyun static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
451*4882a593Smuzhiyun unsigned short val)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun struct atiixp_modem *chip = ac97->private_data;
454*4882a593Smuzhiyun if (reg == AC97_GPIO_STATUS) {
455*4882a593Smuzhiyun atiixp_write(chip, MODEM_OUT_GPIO,
456*4882a593Smuzhiyun (val << ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT) | ATI_REG_MODEM_OUT_GPIO_EN);
457*4882a593Smuzhiyun return;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun snd_atiixp_codec_write(chip, ac97->num, reg, val);
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /*
463*4882a593Smuzhiyun * reset AC link
464*4882a593Smuzhiyun */
snd_atiixp_aclink_reset(struct atiixp_modem * chip)465*4882a593Smuzhiyun static int snd_atiixp_aclink_reset(struct atiixp_modem *chip)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun int timeout;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /* reset powerdoewn */
470*4882a593Smuzhiyun if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
471*4882a593Smuzhiyun udelay(10);
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun /* perform a software reset */
474*4882a593Smuzhiyun atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
475*4882a593Smuzhiyun atiixp_read(chip, CMD);
476*4882a593Smuzhiyun udelay(10);
477*4882a593Smuzhiyun atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun timeout = 10;
480*4882a593Smuzhiyun while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
481*4882a593Smuzhiyun /* do a hard reset */
482*4882a593Smuzhiyun atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
483*4882a593Smuzhiyun ATI_REG_CMD_AC_SYNC);
484*4882a593Smuzhiyun atiixp_read(chip, CMD);
485*4882a593Smuzhiyun msleep(1);
486*4882a593Smuzhiyun atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
487*4882a593Smuzhiyun if (!--timeout) {
488*4882a593Smuzhiyun dev_err(chip->card->dev, "codec reset timeout\n");
489*4882a593Smuzhiyun break;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun /* deassert RESET and assert SYNC to make sure */
494*4882a593Smuzhiyun atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
495*4882a593Smuzhiyun ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun return 0;
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
snd_atiixp_aclink_down(struct atiixp_modem * chip)501*4882a593Smuzhiyun static int snd_atiixp_aclink_down(struct atiixp_modem *chip)
502*4882a593Smuzhiyun {
503*4882a593Smuzhiyun // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
504*4882a593Smuzhiyun // return -EBUSY;
505*4882a593Smuzhiyun atiixp_update(chip, CMD,
506*4882a593Smuzhiyun ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
507*4882a593Smuzhiyun ATI_REG_CMD_POWERDOWN);
508*4882a593Smuzhiyun return 0;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun #endif
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun /*
513*4882a593Smuzhiyun * auto-detection of codecs
514*4882a593Smuzhiyun *
515*4882a593Smuzhiyun * the IXP chip can generate interrupts for the non-existing codecs.
516*4882a593Smuzhiyun * NEW_FRAME interrupt is used to make sure that the interrupt is generated
517*4882a593Smuzhiyun * even if all three codecs are connected.
518*4882a593Smuzhiyun */
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun #define ALL_CODEC_NOT_READY \
521*4882a593Smuzhiyun (ATI_REG_ISR_CODEC0_NOT_READY |\
522*4882a593Smuzhiyun ATI_REG_ISR_CODEC1_NOT_READY |\
523*4882a593Smuzhiyun ATI_REG_ISR_CODEC2_NOT_READY)
524*4882a593Smuzhiyun #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
525*4882a593Smuzhiyun
snd_atiixp_codec_detect(struct atiixp_modem * chip)526*4882a593Smuzhiyun static int snd_atiixp_codec_detect(struct atiixp_modem *chip)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun int timeout;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun chip->codec_not_ready_bits = 0;
531*4882a593Smuzhiyun atiixp_write(chip, IER, CODEC_CHECK_BITS);
532*4882a593Smuzhiyun /* wait for the interrupts */
533*4882a593Smuzhiyun timeout = 50;
534*4882a593Smuzhiyun while (timeout-- > 0) {
535*4882a593Smuzhiyun msleep(1);
536*4882a593Smuzhiyun if (chip->codec_not_ready_bits)
537*4882a593Smuzhiyun break;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun atiixp_write(chip, IER, 0); /* disable irqs */
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
542*4882a593Smuzhiyun dev_err(chip->card->dev, "no codec detected!\n");
543*4882a593Smuzhiyun return -ENXIO;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun return 0;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun /*
550*4882a593Smuzhiyun * enable DMA and irqs
551*4882a593Smuzhiyun */
snd_atiixp_chip_start(struct atiixp_modem * chip)552*4882a593Smuzhiyun static int snd_atiixp_chip_start(struct atiixp_modem *chip)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun unsigned int reg;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun /* set up spdif, enable burst mode */
557*4882a593Smuzhiyun reg = atiixp_read(chip, CMD);
558*4882a593Smuzhiyun reg |= ATI_REG_CMD_BURST_EN;
559*4882a593Smuzhiyun if(!(reg & ATI_REG_CMD_MODEM_PRESENT))
560*4882a593Smuzhiyun reg |= ATI_REG_CMD_MODEM_PRESENT;
561*4882a593Smuzhiyun atiixp_write(chip, CMD, reg);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun /* clear all interrupt source */
564*4882a593Smuzhiyun atiixp_write(chip, ISR, 0xffffffff);
565*4882a593Smuzhiyun /* enable irqs */
566*4882a593Smuzhiyun atiixp_write(chip, IER,
567*4882a593Smuzhiyun ATI_REG_IER_MODEM_STATUS_EN |
568*4882a593Smuzhiyun ATI_REG_IER_MODEM_IN_XRUN_EN |
569*4882a593Smuzhiyun ATI_REG_IER_MODEM_OUT1_XRUN_EN);
570*4882a593Smuzhiyun return 0;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun /*
575*4882a593Smuzhiyun * disable DMA and IRQs
576*4882a593Smuzhiyun */
snd_atiixp_chip_stop(struct atiixp_modem * chip)577*4882a593Smuzhiyun static int snd_atiixp_chip_stop(struct atiixp_modem *chip)
578*4882a593Smuzhiyun {
579*4882a593Smuzhiyun /* clear interrupt source */
580*4882a593Smuzhiyun atiixp_write(chip, ISR, atiixp_read(chip, ISR));
581*4882a593Smuzhiyun /* disable irqs */
582*4882a593Smuzhiyun atiixp_write(chip, IER, 0);
583*4882a593Smuzhiyun return 0;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun /*
588*4882a593Smuzhiyun * PCM section
589*4882a593Smuzhiyun */
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun /*
592*4882a593Smuzhiyun * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
593*4882a593Smuzhiyun * position. when SG-buffer is implemented, the offset must be calculated
594*4882a593Smuzhiyun * correctly...
595*4882a593Smuzhiyun */
snd_atiixp_pcm_pointer(struct snd_pcm_substream * substream)596*4882a593Smuzhiyun static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
597*4882a593Smuzhiyun {
598*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
599*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
600*4882a593Smuzhiyun struct atiixp_dma *dma = runtime->private_data;
601*4882a593Smuzhiyun unsigned int curptr;
602*4882a593Smuzhiyun int timeout = 1000;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun while (timeout--) {
605*4882a593Smuzhiyun curptr = readl(chip->remap_addr + dma->ops->dt_cur);
606*4882a593Smuzhiyun if (curptr < dma->buf_addr)
607*4882a593Smuzhiyun continue;
608*4882a593Smuzhiyun curptr -= dma->buf_addr;
609*4882a593Smuzhiyun if (curptr >= dma->buf_bytes)
610*4882a593Smuzhiyun continue;
611*4882a593Smuzhiyun return bytes_to_frames(runtime, curptr);
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n",
614*4882a593Smuzhiyun readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
615*4882a593Smuzhiyun return 0;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun /*
619*4882a593Smuzhiyun * XRUN detected, and stop the PCM substream
620*4882a593Smuzhiyun */
snd_atiixp_xrun_dma(struct atiixp_modem * chip,struct atiixp_dma * dma)621*4882a593Smuzhiyun static void snd_atiixp_xrun_dma(struct atiixp_modem *chip,
622*4882a593Smuzhiyun struct atiixp_dma *dma)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun if (! dma->substream || ! dma->running)
625*4882a593Smuzhiyun return;
626*4882a593Smuzhiyun dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type);
627*4882a593Smuzhiyun snd_pcm_stop_xrun(dma->substream);
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun /*
631*4882a593Smuzhiyun * the period ack. update the substream.
632*4882a593Smuzhiyun */
snd_atiixp_update_dma(struct atiixp_modem * chip,struct atiixp_dma * dma)633*4882a593Smuzhiyun static void snd_atiixp_update_dma(struct atiixp_modem *chip,
634*4882a593Smuzhiyun struct atiixp_dma *dma)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun if (! dma->substream || ! dma->running)
637*4882a593Smuzhiyun return;
638*4882a593Smuzhiyun snd_pcm_period_elapsed(dma->substream);
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun /* set BUS_BUSY interrupt bit if any DMA is running */
642*4882a593Smuzhiyun /* call with spinlock held */
snd_atiixp_check_bus_busy(struct atiixp_modem * chip)643*4882a593Smuzhiyun static void snd_atiixp_check_bus_busy(struct atiixp_modem *chip)
644*4882a593Smuzhiyun {
645*4882a593Smuzhiyun unsigned int bus_busy;
646*4882a593Smuzhiyun if (atiixp_read(chip, CMD) & (ATI_REG_CMD_MODEM_SEND1_EN |
647*4882a593Smuzhiyun ATI_REG_CMD_MODEM_RECEIVE_EN))
648*4882a593Smuzhiyun bus_busy = ATI_REG_IER_MODEM_SET_BUS_BUSY;
649*4882a593Smuzhiyun else
650*4882a593Smuzhiyun bus_busy = 0;
651*4882a593Smuzhiyun atiixp_update(chip, IER, ATI_REG_IER_MODEM_SET_BUS_BUSY, bus_busy);
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun /* common trigger callback
655*4882a593Smuzhiyun * calling the lowlevel callbacks in it
656*4882a593Smuzhiyun */
snd_atiixp_pcm_trigger(struct snd_pcm_substream * substream,int cmd)657*4882a593Smuzhiyun static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
660*4882a593Smuzhiyun struct atiixp_dma *dma = substream->runtime->private_data;
661*4882a593Smuzhiyun int err = 0;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun if (snd_BUG_ON(!dma->ops->enable_transfer ||
664*4882a593Smuzhiyun !dma->ops->flush_dma))
665*4882a593Smuzhiyun return -EINVAL;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
668*4882a593Smuzhiyun switch(cmd) {
669*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
670*4882a593Smuzhiyun dma->ops->enable_transfer(chip, 1);
671*4882a593Smuzhiyun dma->running = 1;
672*4882a593Smuzhiyun break;
673*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
674*4882a593Smuzhiyun dma->ops->enable_transfer(chip, 0);
675*4882a593Smuzhiyun dma->running = 0;
676*4882a593Smuzhiyun break;
677*4882a593Smuzhiyun default:
678*4882a593Smuzhiyun err = -EINVAL;
679*4882a593Smuzhiyun break;
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun if (! err) {
682*4882a593Smuzhiyun snd_atiixp_check_bus_busy(chip);
683*4882a593Smuzhiyun if (cmd == SNDRV_PCM_TRIGGER_STOP) {
684*4882a593Smuzhiyun dma->ops->flush_dma(chip);
685*4882a593Smuzhiyun snd_atiixp_check_bus_busy(chip);
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
689*4882a593Smuzhiyun return err;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun /*
694*4882a593Smuzhiyun * lowlevel callbacks for each DMA type
695*4882a593Smuzhiyun *
696*4882a593Smuzhiyun * every callback is supposed to be called in chip->reg_lock spinlock
697*4882a593Smuzhiyun */
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun /* flush FIFO of analog OUT DMA */
atiixp_out_flush_dma(struct atiixp_modem * chip)700*4882a593Smuzhiyun static void atiixp_out_flush_dma(struct atiixp_modem *chip)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun atiixp_write(chip, MODEM_FIFO_FLUSH, ATI_REG_MODEM_FIFO_OUT1_FLUSH);
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun /* enable/disable analog OUT DMA */
atiixp_out_enable_dma(struct atiixp_modem * chip,int on)706*4882a593Smuzhiyun static void atiixp_out_enable_dma(struct atiixp_modem *chip, int on)
707*4882a593Smuzhiyun {
708*4882a593Smuzhiyun unsigned int data;
709*4882a593Smuzhiyun data = atiixp_read(chip, CMD);
710*4882a593Smuzhiyun if (on) {
711*4882a593Smuzhiyun if (data & ATI_REG_CMD_MODEM_OUT_DMA1_EN)
712*4882a593Smuzhiyun return;
713*4882a593Smuzhiyun atiixp_out_flush_dma(chip);
714*4882a593Smuzhiyun data |= ATI_REG_CMD_MODEM_OUT_DMA1_EN;
715*4882a593Smuzhiyun } else
716*4882a593Smuzhiyun data &= ~ATI_REG_CMD_MODEM_OUT_DMA1_EN;
717*4882a593Smuzhiyun atiixp_write(chip, CMD, data);
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun /* start/stop transfer over OUT DMA */
atiixp_out_enable_transfer(struct atiixp_modem * chip,int on)721*4882a593Smuzhiyun static void atiixp_out_enable_transfer(struct atiixp_modem *chip, int on)
722*4882a593Smuzhiyun {
723*4882a593Smuzhiyun atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_SEND1_EN,
724*4882a593Smuzhiyun on ? ATI_REG_CMD_MODEM_SEND1_EN : 0);
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun /* enable/disable analog IN DMA */
atiixp_in_enable_dma(struct atiixp_modem * chip,int on)728*4882a593Smuzhiyun static void atiixp_in_enable_dma(struct atiixp_modem *chip, int on)
729*4882a593Smuzhiyun {
730*4882a593Smuzhiyun atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_IN_DMA_EN,
731*4882a593Smuzhiyun on ? ATI_REG_CMD_MODEM_IN_DMA_EN : 0);
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun /* start/stop analog IN DMA */
atiixp_in_enable_transfer(struct atiixp_modem * chip,int on)735*4882a593Smuzhiyun static void atiixp_in_enable_transfer(struct atiixp_modem *chip, int on)
736*4882a593Smuzhiyun {
737*4882a593Smuzhiyun if (on) {
738*4882a593Smuzhiyun unsigned int data = atiixp_read(chip, CMD);
739*4882a593Smuzhiyun if (! (data & ATI_REG_CMD_MODEM_RECEIVE_EN)) {
740*4882a593Smuzhiyun data |= ATI_REG_CMD_MODEM_RECEIVE_EN;
741*4882a593Smuzhiyun atiixp_write(chip, CMD, data);
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun } else
744*4882a593Smuzhiyun atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_RECEIVE_EN, 0);
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun /* flush FIFO of analog IN DMA */
atiixp_in_flush_dma(struct atiixp_modem * chip)748*4882a593Smuzhiyun static void atiixp_in_flush_dma(struct atiixp_modem *chip)
749*4882a593Smuzhiyun {
750*4882a593Smuzhiyun atiixp_write(chip, MODEM_FIFO_FLUSH, ATI_REG_MODEM_FIFO_IN_FLUSH);
751*4882a593Smuzhiyun }
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun /* set up slots and formats for analog OUT */
snd_atiixp_playback_prepare(struct snd_pcm_substream * substream)754*4882a593Smuzhiyun static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
757*4882a593Smuzhiyun unsigned int data;
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun spin_lock_irq(&chip->reg_lock);
760*4882a593Smuzhiyun /* set output threshold */
761*4882a593Smuzhiyun data = atiixp_read(chip, MODEM_OUT_FIFO);
762*4882a593Smuzhiyun data &= ~ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK;
763*4882a593Smuzhiyun data |= 0x04 << ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT;
764*4882a593Smuzhiyun atiixp_write(chip, MODEM_OUT_FIFO, data);
765*4882a593Smuzhiyun spin_unlock_irq(&chip->reg_lock);
766*4882a593Smuzhiyun return 0;
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun /* set up slots and formats for analog IN */
snd_atiixp_capture_prepare(struct snd_pcm_substream * substream)770*4882a593Smuzhiyun static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
771*4882a593Smuzhiyun {
772*4882a593Smuzhiyun return 0;
773*4882a593Smuzhiyun }
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun /*
776*4882a593Smuzhiyun * hw_params - allocate the buffer and set up buffer descriptors
777*4882a593Smuzhiyun */
snd_atiixp_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)778*4882a593Smuzhiyun static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
779*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params)
780*4882a593Smuzhiyun {
781*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
782*4882a593Smuzhiyun struct atiixp_dma *dma = substream->runtime->private_data;
783*4882a593Smuzhiyun int err;
784*4882a593Smuzhiyun int i;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun dma->buf_addr = substream->runtime->dma_addr;
787*4882a593Smuzhiyun dma->buf_bytes = params_buffer_bytes(hw_params);
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun err = atiixp_build_dma_packets(chip, dma, substream,
790*4882a593Smuzhiyun params_periods(hw_params),
791*4882a593Smuzhiyun params_period_bytes(hw_params));
792*4882a593Smuzhiyun if (err < 0)
793*4882a593Smuzhiyun return err;
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun /* set up modem rate */
796*4882a593Smuzhiyun for (i = 0; i < NUM_ATI_CODECS; i++) {
797*4882a593Smuzhiyun if (! chip->ac97[i])
798*4882a593Smuzhiyun continue;
799*4882a593Smuzhiyun snd_ac97_write(chip->ac97[i], AC97_LINE1_RATE, params_rate(hw_params));
800*4882a593Smuzhiyun snd_ac97_write(chip->ac97[i], AC97_LINE1_LEVEL, 0);
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun return err;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
snd_atiixp_pcm_hw_free(struct snd_pcm_substream * substream)806*4882a593Smuzhiyun static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
807*4882a593Smuzhiyun {
808*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
809*4882a593Smuzhiyun struct atiixp_dma *dma = substream->runtime->private_data;
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun atiixp_clear_dma_packets(chip, dma, substream);
812*4882a593Smuzhiyun return 0;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun /*
817*4882a593Smuzhiyun * pcm hardware definition, identical for all DMA types
818*4882a593Smuzhiyun */
819*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_atiixp_pcm_hw =
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
822*4882a593Smuzhiyun SNDRV_PCM_INFO_BLOCK_TRANSFER |
823*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
824*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S16_LE,
825*4882a593Smuzhiyun .rates = (SNDRV_PCM_RATE_8000 |
826*4882a593Smuzhiyun SNDRV_PCM_RATE_16000 |
827*4882a593Smuzhiyun SNDRV_PCM_RATE_KNOT),
828*4882a593Smuzhiyun .rate_min = 8000,
829*4882a593Smuzhiyun .rate_max = 16000,
830*4882a593Smuzhiyun .channels_min = 2,
831*4882a593Smuzhiyun .channels_max = 2,
832*4882a593Smuzhiyun .buffer_bytes_max = 256 * 1024,
833*4882a593Smuzhiyun .period_bytes_min = 32,
834*4882a593Smuzhiyun .period_bytes_max = 128 * 1024,
835*4882a593Smuzhiyun .periods_min = 2,
836*4882a593Smuzhiyun .periods_max = ATI_MAX_DESCRIPTORS,
837*4882a593Smuzhiyun };
838*4882a593Smuzhiyun
snd_atiixp_pcm_open(struct snd_pcm_substream * substream,struct atiixp_dma * dma,int pcm_type)839*4882a593Smuzhiyun static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
840*4882a593Smuzhiyun struct atiixp_dma *dma, int pcm_type)
841*4882a593Smuzhiyun {
842*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
843*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
844*4882a593Smuzhiyun int err;
845*4882a593Smuzhiyun static const unsigned int rates[] = { 8000, 9600, 12000, 16000 };
846*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
847*4882a593Smuzhiyun .count = ARRAY_SIZE(rates),
848*4882a593Smuzhiyun .list = rates,
849*4882a593Smuzhiyun .mask = 0,
850*4882a593Smuzhiyun };
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
853*4882a593Smuzhiyun return -EINVAL;
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun if (dma->opened)
856*4882a593Smuzhiyun return -EBUSY;
857*4882a593Smuzhiyun dma->substream = substream;
858*4882a593Smuzhiyun runtime->hw = snd_atiixp_pcm_hw;
859*4882a593Smuzhiyun dma->ac97_pcm_type = pcm_type;
860*4882a593Smuzhiyun if ((err = snd_pcm_hw_constraint_list(runtime, 0,
861*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE,
862*4882a593Smuzhiyun &hw_constraints_rates)) < 0)
863*4882a593Smuzhiyun return err;
864*4882a593Smuzhiyun if ((err = snd_pcm_hw_constraint_integer(runtime,
865*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
866*4882a593Smuzhiyun return err;
867*4882a593Smuzhiyun runtime->private_data = dma;
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun /* enable DMA bits */
870*4882a593Smuzhiyun spin_lock_irq(&chip->reg_lock);
871*4882a593Smuzhiyun dma->ops->enable_dma(chip, 1);
872*4882a593Smuzhiyun spin_unlock_irq(&chip->reg_lock);
873*4882a593Smuzhiyun dma->opened = 1;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun return 0;
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun
snd_atiixp_pcm_close(struct snd_pcm_substream * substream,struct atiixp_dma * dma)878*4882a593Smuzhiyun static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
879*4882a593Smuzhiyun struct atiixp_dma *dma)
880*4882a593Smuzhiyun {
881*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
882*4882a593Smuzhiyun /* disable DMA bits */
883*4882a593Smuzhiyun if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
884*4882a593Smuzhiyun return -EINVAL;
885*4882a593Smuzhiyun spin_lock_irq(&chip->reg_lock);
886*4882a593Smuzhiyun dma->ops->enable_dma(chip, 0);
887*4882a593Smuzhiyun spin_unlock_irq(&chip->reg_lock);
888*4882a593Smuzhiyun dma->substream = NULL;
889*4882a593Smuzhiyun dma->opened = 0;
890*4882a593Smuzhiyun return 0;
891*4882a593Smuzhiyun }
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun /*
894*4882a593Smuzhiyun */
snd_atiixp_playback_open(struct snd_pcm_substream * substream)895*4882a593Smuzhiyun static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
896*4882a593Smuzhiyun {
897*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
898*4882a593Smuzhiyun int err;
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun mutex_lock(&chip->open_mutex);
901*4882a593Smuzhiyun err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
902*4882a593Smuzhiyun mutex_unlock(&chip->open_mutex);
903*4882a593Smuzhiyun if (err < 0)
904*4882a593Smuzhiyun return err;
905*4882a593Smuzhiyun return 0;
906*4882a593Smuzhiyun }
907*4882a593Smuzhiyun
snd_atiixp_playback_close(struct snd_pcm_substream * substream)908*4882a593Smuzhiyun static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
909*4882a593Smuzhiyun {
910*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
911*4882a593Smuzhiyun int err;
912*4882a593Smuzhiyun mutex_lock(&chip->open_mutex);
913*4882a593Smuzhiyun err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
914*4882a593Smuzhiyun mutex_unlock(&chip->open_mutex);
915*4882a593Smuzhiyun return err;
916*4882a593Smuzhiyun }
917*4882a593Smuzhiyun
snd_atiixp_capture_open(struct snd_pcm_substream * substream)918*4882a593Smuzhiyun static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
919*4882a593Smuzhiyun {
920*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
921*4882a593Smuzhiyun return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
922*4882a593Smuzhiyun }
923*4882a593Smuzhiyun
snd_atiixp_capture_close(struct snd_pcm_substream * substream)924*4882a593Smuzhiyun static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
925*4882a593Smuzhiyun {
926*4882a593Smuzhiyun struct atiixp_modem *chip = snd_pcm_substream_chip(substream);
927*4882a593Smuzhiyun return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
928*4882a593Smuzhiyun }
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun /* AC97 playback */
932*4882a593Smuzhiyun static const struct snd_pcm_ops snd_atiixp_playback_ops = {
933*4882a593Smuzhiyun .open = snd_atiixp_playback_open,
934*4882a593Smuzhiyun .close = snd_atiixp_playback_close,
935*4882a593Smuzhiyun .hw_params = snd_atiixp_pcm_hw_params,
936*4882a593Smuzhiyun .hw_free = snd_atiixp_pcm_hw_free,
937*4882a593Smuzhiyun .prepare = snd_atiixp_playback_prepare,
938*4882a593Smuzhiyun .trigger = snd_atiixp_pcm_trigger,
939*4882a593Smuzhiyun .pointer = snd_atiixp_pcm_pointer,
940*4882a593Smuzhiyun };
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun /* AC97 capture */
943*4882a593Smuzhiyun static const struct snd_pcm_ops snd_atiixp_capture_ops = {
944*4882a593Smuzhiyun .open = snd_atiixp_capture_open,
945*4882a593Smuzhiyun .close = snd_atiixp_capture_close,
946*4882a593Smuzhiyun .hw_params = snd_atiixp_pcm_hw_params,
947*4882a593Smuzhiyun .hw_free = snd_atiixp_pcm_hw_free,
948*4882a593Smuzhiyun .prepare = snd_atiixp_capture_prepare,
949*4882a593Smuzhiyun .trigger = snd_atiixp_pcm_trigger,
950*4882a593Smuzhiyun .pointer = snd_atiixp_pcm_pointer,
951*4882a593Smuzhiyun };
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
954*4882a593Smuzhiyun .type = ATI_DMA_PLAYBACK,
955*4882a593Smuzhiyun .llp_offset = ATI_REG_MODEM_OUT_DMA1_LINKPTR,
956*4882a593Smuzhiyun .dt_cur = ATI_REG_MODEM_OUT_DMA1_DT_CUR,
957*4882a593Smuzhiyun .enable_dma = atiixp_out_enable_dma,
958*4882a593Smuzhiyun .enable_transfer = atiixp_out_enable_transfer,
959*4882a593Smuzhiyun .flush_dma = atiixp_out_flush_dma,
960*4882a593Smuzhiyun };
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
963*4882a593Smuzhiyun .type = ATI_DMA_CAPTURE,
964*4882a593Smuzhiyun .llp_offset = ATI_REG_MODEM_IN_DMA_LINKPTR,
965*4882a593Smuzhiyun .dt_cur = ATI_REG_MODEM_IN_DMA_DT_CUR,
966*4882a593Smuzhiyun .enable_dma = atiixp_in_enable_dma,
967*4882a593Smuzhiyun .enable_transfer = atiixp_in_enable_transfer,
968*4882a593Smuzhiyun .flush_dma = atiixp_in_flush_dma,
969*4882a593Smuzhiyun };
970*4882a593Smuzhiyun
snd_atiixp_pcm_new(struct atiixp_modem * chip)971*4882a593Smuzhiyun static int snd_atiixp_pcm_new(struct atiixp_modem *chip)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun struct snd_pcm *pcm;
974*4882a593Smuzhiyun int err;
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun /* initialize constants */
977*4882a593Smuzhiyun chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
978*4882a593Smuzhiyun chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun /* PCM #0: analog I/O */
981*4882a593Smuzhiyun err = snd_pcm_new(chip->card, "ATI IXP MC97", ATI_PCMDEV_ANALOG, 1, 1, &pcm);
982*4882a593Smuzhiyun if (err < 0)
983*4882a593Smuzhiyun return err;
984*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
985*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
986*4882a593Smuzhiyun pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
987*4882a593Smuzhiyun pcm->private_data = chip;
988*4882a593Smuzhiyun strcpy(pcm->name, "ATI IXP MC97");
989*4882a593Smuzhiyun chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
992*4882a593Smuzhiyun &chip->pci->dev, 64*1024, 128*1024);
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun return 0;
995*4882a593Smuzhiyun }
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun /*
1000*4882a593Smuzhiyun * interrupt handler
1001*4882a593Smuzhiyun */
snd_atiixp_interrupt(int irq,void * dev_id)1002*4882a593Smuzhiyun static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
1003*4882a593Smuzhiyun {
1004*4882a593Smuzhiyun struct atiixp_modem *chip = dev_id;
1005*4882a593Smuzhiyun unsigned int status;
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun status = atiixp_read(chip, ISR);
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun if (! status)
1010*4882a593Smuzhiyun return IRQ_NONE;
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun /* process audio DMA */
1013*4882a593Smuzhiyun if (status & ATI_REG_ISR_MODEM_OUT1_XRUN)
1014*4882a593Smuzhiyun snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1015*4882a593Smuzhiyun else if (status & ATI_REG_ISR_MODEM_OUT1_STATUS)
1016*4882a593Smuzhiyun snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1017*4882a593Smuzhiyun if (status & ATI_REG_ISR_MODEM_IN_XRUN)
1018*4882a593Smuzhiyun snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1019*4882a593Smuzhiyun else if (status & ATI_REG_ISR_MODEM_IN_STATUS)
1020*4882a593Smuzhiyun snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun /* for codec detection */
1023*4882a593Smuzhiyun if (status & CODEC_CHECK_BITS) {
1024*4882a593Smuzhiyun unsigned int detected;
1025*4882a593Smuzhiyun detected = status & CODEC_CHECK_BITS;
1026*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
1027*4882a593Smuzhiyun chip->codec_not_ready_bits |= detected;
1028*4882a593Smuzhiyun atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1029*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun /* ack */
1033*4882a593Smuzhiyun atiixp_write(chip, ISR, status);
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun return IRQ_HANDLED;
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun /*
1040*4882a593Smuzhiyun * ac97 mixer section
1041*4882a593Smuzhiyun */
1042*4882a593Smuzhiyun
snd_atiixp_mixer_new(struct atiixp_modem * chip,int clock)1043*4882a593Smuzhiyun static int snd_atiixp_mixer_new(struct atiixp_modem *chip, int clock)
1044*4882a593Smuzhiyun {
1045*4882a593Smuzhiyun struct snd_ac97_bus *pbus;
1046*4882a593Smuzhiyun struct snd_ac97_template ac97;
1047*4882a593Smuzhiyun int i, err;
1048*4882a593Smuzhiyun int codec_count;
1049*4882a593Smuzhiyun static const struct snd_ac97_bus_ops ops = {
1050*4882a593Smuzhiyun .write = snd_atiixp_ac97_write,
1051*4882a593Smuzhiyun .read = snd_atiixp_ac97_read,
1052*4882a593Smuzhiyun };
1053*4882a593Smuzhiyun static const unsigned int codec_skip[NUM_ATI_CODECS] = {
1054*4882a593Smuzhiyun ATI_REG_ISR_CODEC0_NOT_READY,
1055*4882a593Smuzhiyun ATI_REG_ISR_CODEC1_NOT_READY,
1056*4882a593Smuzhiyun ATI_REG_ISR_CODEC2_NOT_READY,
1057*4882a593Smuzhiyun };
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun if (snd_atiixp_codec_detect(chip) < 0)
1060*4882a593Smuzhiyun return -ENXIO;
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
1063*4882a593Smuzhiyun return err;
1064*4882a593Smuzhiyun pbus->clock = clock;
1065*4882a593Smuzhiyun chip->ac97_bus = pbus;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun codec_count = 0;
1068*4882a593Smuzhiyun for (i = 0; i < NUM_ATI_CODECS; i++) {
1069*4882a593Smuzhiyun if (chip->codec_not_ready_bits & codec_skip[i])
1070*4882a593Smuzhiyun continue;
1071*4882a593Smuzhiyun memset(&ac97, 0, sizeof(ac97));
1072*4882a593Smuzhiyun ac97.private_data = chip;
1073*4882a593Smuzhiyun ac97.pci = chip->pci;
1074*4882a593Smuzhiyun ac97.num = i;
1075*4882a593Smuzhiyun ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
1076*4882a593Smuzhiyun if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1077*4882a593Smuzhiyun chip->ac97[i] = NULL; /* to be sure */
1078*4882a593Smuzhiyun dev_dbg(chip->card->dev,
1079*4882a593Smuzhiyun "codec %d not available for modem\n", i);
1080*4882a593Smuzhiyun continue;
1081*4882a593Smuzhiyun }
1082*4882a593Smuzhiyun codec_count++;
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun if (! codec_count) {
1086*4882a593Smuzhiyun dev_err(chip->card->dev, "no codec available\n");
1087*4882a593Smuzhiyun return -ENODEV;
1088*4882a593Smuzhiyun }
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun /* snd_ac97_tune_hardware(chip->ac97, ac97_quirks); */
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun return 0;
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
1097*4882a593Smuzhiyun /*
1098*4882a593Smuzhiyun * power management
1099*4882a593Smuzhiyun */
snd_atiixp_suspend(struct device * dev)1100*4882a593Smuzhiyun static int snd_atiixp_suspend(struct device *dev)
1101*4882a593Smuzhiyun {
1102*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
1103*4882a593Smuzhiyun struct atiixp_modem *chip = card->private_data;
1104*4882a593Smuzhiyun int i;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1107*4882a593Smuzhiyun for (i = 0; i < NUM_ATI_CODECS; i++)
1108*4882a593Smuzhiyun snd_ac97_suspend(chip->ac97[i]);
1109*4882a593Smuzhiyun snd_atiixp_aclink_down(chip);
1110*4882a593Smuzhiyun snd_atiixp_chip_stop(chip);
1111*4882a593Smuzhiyun return 0;
1112*4882a593Smuzhiyun }
1113*4882a593Smuzhiyun
snd_atiixp_resume(struct device * dev)1114*4882a593Smuzhiyun static int snd_atiixp_resume(struct device *dev)
1115*4882a593Smuzhiyun {
1116*4882a593Smuzhiyun struct snd_card *card = dev_get_drvdata(dev);
1117*4882a593Smuzhiyun struct atiixp_modem *chip = card->private_data;
1118*4882a593Smuzhiyun int i;
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun snd_atiixp_aclink_reset(chip);
1121*4882a593Smuzhiyun snd_atiixp_chip_start(chip);
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun for (i = 0; i < NUM_ATI_CODECS; i++)
1124*4882a593Smuzhiyun snd_ac97_resume(chip->ac97[i]);
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1127*4882a593Smuzhiyun return 0;
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
1131*4882a593Smuzhiyun #define SND_ATIIXP_PM_OPS &snd_atiixp_pm
1132*4882a593Smuzhiyun #else
1133*4882a593Smuzhiyun #define SND_ATIIXP_PM_OPS NULL
1134*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun /*
1137*4882a593Smuzhiyun * proc interface for register dump
1138*4882a593Smuzhiyun */
1139*4882a593Smuzhiyun
snd_atiixp_proc_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1140*4882a593Smuzhiyun static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1141*4882a593Smuzhiyun struct snd_info_buffer *buffer)
1142*4882a593Smuzhiyun {
1143*4882a593Smuzhiyun struct atiixp_modem *chip = entry->private_data;
1144*4882a593Smuzhiyun int i;
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun for (i = 0; i < 256; i += 4)
1147*4882a593Smuzhiyun snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun
snd_atiixp_proc_init(struct atiixp_modem * chip)1150*4882a593Smuzhiyun static void snd_atiixp_proc_init(struct atiixp_modem *chip)
1151*4882a593Smuzhiyun {
1152*4882a593Smuzhiyun snd_card_ro_proc_new(chip->card, "atiixp-modem", chip,
1153*4882a593Smuzhiyun snd_atiixp_proc_read);
1154*4882a593Smuzhiyun }
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun /*
1158*4882a593Smuzhiyun * destructor
1159*4882a593Smuzhiyun */
1160*4882a593Smuzhiyun
snd_atiixp_free(struct atiixp_modem * chip)1161*4882a593Smuzhiyun static int snd_atiixp_free(struct atiixp_modem *chip)
1162*4882a593Smuzhiyun {
1163*4882a593Smuzhiyun if (chip->irq < 0)
1164*4882a593Smuzhiyun goto __hw_end;
1165*4882a593Smuzhiyun snd_atiixp_chip_stop(chip);
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun __hw_end:
1168*4882a593Smuzhiyun if (chip->irq >= 0)
1169*4882a593Smuzhiyun free_irq(chip->irq, chip);
1170*4882a593Smuzhiyun iounmap(chip->remap_addr);
1171*4882a593Smuzhiyun pci_release_regions(chip->pci);
1172*4882a593Smuzhiyun pci_disable_device(chip->pci);
1173*4882a593Smuzhiyun kfree(chip);
1174*4882a593Smuzhiyun return 0;
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun
snd_atiixp_dev_free(struct snd_device * device)1177*4882a593Smuzhiyun static int snd_atiixp_dev_free(struct snd_device *device)
1178*4882a593Smuzhiyun {
1179*4882a593Smuzhiyun struct atiixp_modem *chip = device->device_data;
1180*4882a593Smuzhiyun return snd_atiixp_free(chip);
1181*4882a593Smuzhiyun }
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun /*
1184*4882a593Smuzhiyun * constructor for chip instance
1185*4882a593Smuzhiyun */
snd_atiixp_create(struct snd_card * card,struct pci_dev * pci,struct atiixp_modem ** r_chip)1186*4882a593Smuzhiyun static int snd_atiixp_create(struct snd_card *card,
1187*4882a593Smuzhiyun struct pci_dev *pci,
1188*4882a593Smuzhiyun struct atiixp_modem **r_chip)
1189*4882a593Smuzhiyun {
1190*4882a593Smuzhiyun static const struct snd_device_ops ops = {
1191*4882a593Smuzhiyun .dev_free = snd_atiixp_dev_free,
1192*4882a593Smuzhiyun };
1193*4882a593Smuzhiyun struct atiixp_modem *chip;
1194*4882a593Smuzhiyun int err;
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun if ((err = pci_enable_device(pci)) < 0)
1197*4882a593Smuzhiyun return err;
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1200*4882a593Smuzhiyun if (chip == NULL) {
1201*4882a593Smuzhiyun pci_disable_device(pci);
1202*4882a593Smuzhiyun return -ENOMEM;
1203*4882a593Smuzhiyun }
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun spin_lock_init(&chip->reg_lock);
1206*4882a593Smuzhiyun mutex_init(&chip->open_mutex);
1207*4882a593Smuzhiyun chip->card = card;
1208*4882a593Smuzhiyun chip->pci = pci;
1209*4882a593Smuzhiyun chip->irq = -1;
1210*4882a593Smuzhiyun if ((err = pci_request_regions(pci, "ATI IXP MC97")) < 0) {
1211*4882a593Smuzhiyun kfree(chip);
1212*4882a593Smuzhiyun pci_disable_device(pci);
1213*4882a593Smuzhiyun return err;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun chip->addr = pci_resource_start(pci, 0);
1216*4882a593Smuzhiyun chip->remap_addr = pci_ioremap_bar(pci, 0);
1217*4882a593Smuzhiyun if (chip->remap_addr == NULL) {
1218*4882a593Smuzhiyun dev_err(card->dev, "AC'97 space ioremap problem\n");
1219*4882a593Smuzhiyun snd_atiixp_free(chip);
1220*4882a593Smuzhiyun return -EIO;
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED,
1224*4882a593Smuzhiyun KBUILD_MODNAME, chip)) {
1225*4882a593Smuzhiyun dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1226*4882a593Smuzhiyun snd_atiixp_free(chip);
1227*4882a593Smuzhiyun return -EBUSY;
1228*4882a593Smuzhiyun }
1229*4882a593Smuzhiyun chip->irq = pci->irq;
1230*4882a593Smuzhiyun card->sync_irq = chip->irq;
1231*4882a593Smuzhiyun pci_set_master(pci);
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1234*4882a593Smuzhiyun snd_atiixp_free(chip);
1235*4882a593Smuzhiyun return err;
1236*4882a593Smuzhiyun }
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun *r_chip = chip;
1239*4882a593Smuzhiyun return 0;
1240*4882a593Smuzhiyun }
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun
snd_atiixp_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1243*4882a593Smuzhiyun static int snd_atiixp_probe(struct pci_dev *pci,
1244*4882a593Smuzhiyun const struct pci_device_id *pci_id)
1245*4882a593Smuzhiyun {
1246*4882a593Smuzhiyun struct snd_card *card;
1247*4882a593Smuzhiyun struct atiixp_modem *chip;
1248*4882a593Smuzhiyun int err;
1249*4882a593Smuzhiyun
1250*4882a593Smuzhiyun err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
1251*4882a593Smuzhiyun if (err < 0)
1252*4882a593Smuzhiyun return err;
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun strcpy(card->driver, "ATIIXP-MODEM");
1255*4882a593Smuzhiyun strcpy(card->shortname, "ATI IXP Modem");
1256*4882a593Smuzhiyun if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
1257*4882a593Smuzhiyun goto __error;
1258*4882a593Smuzhiyun card->private_data = chip;
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun if ((err = snd_atiixp_aclink_reset(chip)) < 0)
1261*4882a593Smuzhiyun goto __error;
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun if ((err = snd_atiixp_mixer_new(chip, ac97_clock)) < 0)
1264*4882a593Smuzhiyun goto __error;
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun if ((err = snd_atiixp_pcm_new(chip)) < 0)
1267*4882a593Smuzhiyun goto __error;
1268*4882a593Smuzhiyun
1269*4882a593Smuzhiyun snd_atiixp_proc_init(chip);
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun snd_atiixp_chip_start(chip);
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun sprintf(card->longname, "%s rev %x at 0x%lx, irq %i",
1274*4882a593Smuzhiyun card->shortname, pci->revision, chip->addr, chip->irq);
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun if ((err = snd_card_register(card)) < 0)
1277*4882a593Smuzhiyun goto __error;
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun pci_set_drvdata(pci, card);
1280*4882a593Smuzhiyun return 0;
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun __error:
1283*4882a593Smuzhiyun snd_card_free(card);
1284*4882a593Smuzhiyun return err;
1285*4882a593Smuzhiyun }
1286*4882a593Smuzhiyun
snd_atiixp_remove(struct pci_dev * pci)1287*4882a593Smuzhiyun static void snd_atiixp_remove(struct pci_dev *pci)
1288*4882a593Smuzhiyun {
1289*4882a593Smuzhiyun snd_card_free(pci_get_drvdata(pci));
1290*4882a593Smuzhiyun }
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun static struct pci_driver atiixp_modem_driver = {
1293*4882a593Smuzhiyun .name = KBUILD_MODNAME,
1294*4882a593Smuzhiyun .id_table = snd_atiixp_ids,
1295*4882a593Smuzhiyun .probe = snd_atiixp_probe,
1296*4882a593Smuzhiyun .remove = snd_atiixp_remove,
1297*4882a593Smuzhiyun .driver = {
1298*4882a593Smuzhiyun .pm = SND_ATIIXP_PM_OPS,
1299*4882a593Smuzhiyun },
1300*4882a593Smuzhiyun };
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun module_pci_driver(atiixp_modem_driver);
1303