1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Analog Devices 1889 audio driver 3*4882a593Smuzhiyun * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __AD1889_H__ 7*4882a593Smuzhiyun #define __AD1889_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */ 10*4882a593Smuzhiyun #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */ 11*4882a593Smuzhiyun #define AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */ 12*4882a593Smuzhiyun #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */ 13*4882a593Smuzhiyun #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */ 14*4882a593Smuzhiyun #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */ 15*4882a593Smuzhiyun #define AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */ 18*4882a593Smuzhiyun #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */ 19*4882a593Smuzhiyun #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */ 20*4882a593Smuzhiyun #define AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */ 21*4882a593Smuzhiyun #define AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo request point */ 22*4882a593Smuzhiyun #define AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */ 23*4882a593Smuzhiyun #define AD_DS_RAMC_RERQ 0x3000 /* res. fifo request point */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define AD_DS_WADA 0x04 /* wave channel mix attenuation */ 26*4882a593Smuzhiyun #define AD_DS_WADA_RWAM 0x0080 /* right wave mute */ 27*4882a593Smuzhiyun #define AD_DS_WADA_RWAA 0x001f /* right wave attenuation */ 28*4882a593Smuzhiyun #define AD_DS_WADA_LWAM 0x8000 /* left wave mute */ 29*4882a593Smuzhiyun #define AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define AD_DS_SYDA 0x06 /* synthesis channel mix attenuation */ 32*4882a593Smuzhiyun #define AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */ 33*4882a593Smuzhiyun #define AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */ 34*4882a593Smuzhiyun #define AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */ 35*4882a593Smuzhiyun #define AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AD_DS_WAS 0x08 /* wave channel sample rate */ 38*4882a593Smuzhiyun #define AD_DS_WAS_WAS 0xffff /* sample rate mask */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define AD_DS_RES 0x0a /* resampler channel sample rate */ 41*4882a593Smuzhiyun #define AD_DS_RES_RES 0xffff /* sample rate mask */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define AD_DS_CCS 0x0c /* chip control/status */ 44*4882a593Smuzhiyun #define AD_DS_CCS_ADO 0x0001 /* ADC channel overflow */ 45*4882a593Smuzhiyun #define AD_DS_CCS_REO 0x0002 /* resampler channel overflow */ 46*4882a593Smuzhiyun #define AD_DS_CCS_SYU 0x0004 /* synthesis channel underflow */ 47*4882a593Smuzhiyun #define AD_DS_CCS_WAU 0x0008 /* wave channel underflow */ 48*4882a593Smuzhiyun /* bits 4 -> 7, 9, 11 -> 14 reserved */ 49*4882a593Smuzhiyun #define AD_DS_CCS_XTD 0x0100 /* xtd delay control (4096 clock cycles) */ 50*4882a593Smuzhiyun #define AD_DS_CCS_PDALL 0x0400 /* power */ 51*4882a593Smuzhiyun #define AD_DS_CCS_CLKEN 0x8000 /* clock */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define AD_DMA_RESBA 0x40 /* RES base address */ 54*4882a593Smuzhiyun #define AD_DMA_RESCA 0x44 /* RES current address */ 55*4882a593Smuzhiyun #define AD_DMA_RESBC 0x48 /* RES base count */ 56*4882a593Smuzhiyun #define AD_DMA_RESCC 0x4c /* RES current count */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define AD_DMA_ADCBA 0x50 /* ADC base address */ 59*4882a593Smuzhiyun #define AD_DMA_ADCCA 0x54 /* ADC current address */ 60*4882a593Smuzhiyun #define AD_DMA_ADCBC 0x58 /* ADC base count */ 61*4882a593Smuzhiyun #define AD_DMA_ADCCC 0x5c /* ADC current count */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define AD_DMA_SYNBA 0x60 /* synth base address */ 64*4882a593Smuzhiyun #define AD_DMA_SYNCA 0x64 /* synth current address */ 65*4882a593Smuzhiyun #define AD_DMA_SYNBC 0x68 /* synth base count */ 66*4882a593Smuzhiyun #define AD_DMA_SYNCC 0x6c /* synth current count */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define AD_DMA_WAVBA 0x70 /* wave base address */ 69*4882a593Smuzhiyun #define AD_DMA_WAVCA 0x74 /* wave current address */ 70*4882a593Smuzhiyun #define AD_DMA_WAVBC 0x78 /* wave base count */ 71*4882a593Smuzhiyun #define AD_DMA_WAVCC 0x7c /* wave current count */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define AD_DMA_RESIC 0x80 /* RES dma interrupt current byte count */ 74*4882a593Smuzhiyun #define AD_DMA_RESIB 0x84 /* RES dma interrupt base byte count */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define AD_DMA_ADCIC 0x88 /* ADC dma interrupt current byte count */ 77*4882a593Smuzhiyun #define AD_DMA_ADCIB 0x8c /* ADC dma interrupt base byte count */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define AD_DMA_SYNIC 0x90 /* synth dma interrupt current byte count */ 80*4882a593Smuzhiyun #define AD_DMA_SYNIB 0x94 /* synth dma interrupt base byte count */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define AD_DMA_WAVIC 0x98 /* wave dma interrupt current byte count */ 83*4882a593Smuzhiyun #define AD_DMA_WAVIB 0x9c /* wave dma interrupt base byte count */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define AD_DMA_ICC 0xffffff /* current byte count mask */ 86*4882a593Smuzhiyun #define AD_DMA_IBC 0xffffff /* base byte count mask */ 87*4882a593Smuzhiyun /* bits 24 -> 31 reserved */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 4 bytes pad */ 90*4882a593Smuzhiyun #define AD_DMA_ADC 0xa8 /* ADC dma control and status */ 91*4882a593Smuzhiyun #define AD_DMA_SYNTH 0xb0 /* Synth dma control and status */ 92*4882a593Smuzhiyun #define AD_DMA_WAV 0xb8 /* wave dma control and status */ 93*4882a593Smuzhiyun #define AD_DMA_RES 0xa0 /* Resample dma control and status */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define AD_DMA_SGDE 0x0001 /* SGD mode enable */ 96*4882a593Smuzhiyun #define AD_DMA_LOOP 0x0002 /* loop enable */ 97*4882a593Smuzhiyun #define AD_DMA_IM 0x000c /* interrupt mode mask */ 98*4882a593Smuzhiyun #define AD_DMA_IM_DIS (~AD_DMA_IM) /* disable */ 99*4882a593Smuzhiyun #define AD_DMA_IM_CNT 0x0004 /* interrupt on count */ 100*4882a593Smuzhiyun #define AD_DMA_IM_SGD 0x0008 /* interrupt on SGD flag */ 101*4882a593Smuzhiyun #define AD_DMA_IM_EOL 0x000c /* interrupt on End of Linked List */ 102*4882a593Smuzhiyun #define AD_DMA_SGDS 0x0030 /* SGD status */ 103*4882a593Smuzhiyun #define AD_DMA_SFLG 0x0040 /* SGD flag */ 104*4882a593Smuzhiyun #define AD_DMA_EOL 0x0080 /* SGD end of list */ 105*4882a593Smuzhiyun /* bits 8 -> 15 reserved */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define AD_DMA_DISR 0xc0 /* dma interrupt status */ 108*4882a593Smuzhiyun #define AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */ 109*4882a593Smuzhiyun #define AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */ 110*4882a593Smuzhiyun #define AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */ 111*4882a593Smuzhiyun #define AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */ 112*4882a593Smuzhiyun /* bits 4, 5 reserved */ 113*4882a593Smuzhiyun #define AD_DMA_DISR_SEPS 0x000040 /* serial eeprom status */ 114*4882a593Smuzhiyun /* bits 7 -> 13 reserved */ 115*4882a593Smuzhiyun #define AD_DMA_DISR_PMAI 0x004000 /* pci master abort interrupt */ 116*4882a593Smuzhiyun #define AD_DMA_DISR_PTAI 0x008000 /* pci target abort interrupt */ 117*4882a593Smuzhiyun #define AD_DMA_DISR_PTAE 0x010000 /* pci target abort interrupt enable */ 118*4882a593Smuzhiyun #define AD_DMA_DISR_PMAE 0x020000 /* pci master abort interrupt enable */ 119*4882a593Smuzhiyun /* bits 19 -> 31 reserved */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* interrupt mask */ 122*4882a593Smuzhiyun #define AD_INTR_MASK (AD_DMA_DISR_RESI|AD_DMA_DISR_ADCI| \ 123*4882a593Smuzhiyun AD_DMA_DISR_WAVI|AD_DMA_DISR_SYNI| \ 124*4882a593Smuzhiyun AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define AD_DMA_CHSS 0xc4 /* dma channel stop status */ 127*4882a593Smuzhiyun #define AD_DMA_CHSS_RESS 0x000001 /* resampler channel stopped */ 128*4882a593Smuzhiyun #define AD_DMA_CHSS_ADCS 0x000002 /* ADC channel stopped */ 129*4882a593Smuzhiyun #define AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */ 130*4882a593Smuzhiyun #define AD_DMA_CHSS_WAVS 0x000008 /* wave channel stopped */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define AD_GPIO_IPC 0xc8 /* gpio port control */ 133*4882a593Smuzhiyun #define AD_GPIO_OP 0xca /* gpio output port status */ 134*4882a593Smuzhiyun #define AD_GPIO_IP 0xcc /* gpio input port status */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define AD_AC97_BASE 0x100 /* ac97 base register */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define AD_AC97_RESET 0x100 /* reset */ 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define AD_AC97_PWR_CTL 0x126 /* == AC97_POWERDOWN */ 141*4882a593Smuzhiyun #define AD_AC97_PWR_ADC 0x0001 /* ADC ready status */ 142*4882a593Smuzhiyun #define AD_AC97_PWR_DAC 0x0002 /* DAC ready status */ 143*4882a593Smuzhiyun #define AD_AC97_PWR_PR0 0x0100 /* PR0 (ADC) powerdown */ 144*4882a593Smuzhiyun #define AD_AC97_PWR_PR1 0x0200 /* PR1 (DAC) powerdown */ 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define AD_MISC_CTL 0x176 /* misc control */ 147*4882a593Smuzhiyun #define AD_MISC_CTL_DACZ 0x8000 /* set for zero fill, unset for repeat */ 148*4882a593Smuzhiyun #define AD_MISC_CTL_ARSR 0x0001 /* set for SR1, unset for SR0 */ 149*4882a593Smuzhiyun #define AD_MISC_CTL_ALSR 0x0100 150*4882a593Smuzhiyun #define AD_MISC_CTL_DLSR 0x0400 151*4882a593Smuzhiyun #define AD_MISC_CTL_DRSR 0x0004 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define AD_AC97_SR0 0x178 /* sample rate 0, 0xbb80 == 48K */ 154*4882a593Smuzhiyun #define AD_AC97_SR0_48K 0xbb80 /* 48KHz */ 155*4882a593Smuzhiyun #define AD_AC97_SR1 0x17a /* sample rate 1 */ 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define AD_AC97_ACIC 0x180 /* ac97 codec interface control */ 158*4882a593Smuzhiyun #define AD_AC97_ACIC_ACIE 0x0001 /* analog codec interface enable */ 159*4882a593Smuzhiyun #define AD_AC97_ACIC_ACRD 0x0002 /* analog codec reset disable */ 160*4882a593Smuzhiyun #define AD_AC97_ACIC_ASOE 0x0004 /* audio stream output enable */ 161*4882a593Smuzhiyun #define AD_AC97_ACIC_VSRM 0x0008 /* variable sample rate mode */ 162*4882a593Smuzhiyun #define AD_AC97_ACIC_FSDH 0x0100 /* force SDATA_OUT high */ 163*4882a593Smuzhiyun #define AD_AC97_ACIC_FSYH 0x0200 /* force sync high */ 164*4882a593Smuzhiyun #define AD_AC97_ACIC_ACRDY 0x8000 /* analog codec ready status */ 165*4882a593Smuzhiyun /* bits 10 -> 14 reserved */ 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #define AD_DS_MEMSIZE 512 169*4882a593Smuzhiyun #define AD_OPL_MEMSIZE 16 170*4882a593Smuzhiyun #define AD_MIDI_MEMSIZE 16 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define AD_WAV_STATE 0 173*4882a593Smuzhiyun #define AD_ADC_STATE 1 174*4882a593Smuzhiyun #define AD_MAX_STATES 2 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define AD_CHAN_WAV 0x0001 177*4882a593Smuzhiyun #define AD_CHAN_ADC 0x0002 178*4882a593Smuzhiyun #define AD_CHAN_RES 0x0004 179*4882a593Smuzhiyun #define AD_CHAN_SYN 0x0008 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* The chip would support 4 GB buffers and 16 MB periods, 183*4882a593Smuzhiyun * but let's not overdo it ... */ 184*4882a593Smuzhiyun #define BUFFER_BYTES_MAX (256 * 1024) 185*4882a593Smuzhiyun #define PERIOD_BYTES_MIN 32 186*4882a593Smuzhiyun #define PERIOD_BYTES_MAX (BUFFER_BYTES_MAX / 2) 187*4882a593Smuzhiyun #define PERIODS_MIN 2 188*4882a593Smuzhiyun #define PERIODS_MAX (BUFFER_BYTES_MAX / PERIOD_BYTES_MIN) 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #endif /* __AD1889_H__ */ 191