1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4*4882a593Smuzhiyun * Uros Bizjak <uros@kss-loka.si>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Routines for control of 8-bit SoundBlaster cards and clones
7*4882a593Smuzhiyun * Please note: I don't have access to old SB8 soundcards.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * --
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Thu Apr 29 20:36:17 BST 1999 George David Morrison <gdm@gedamo.demon.co.uk>
12*4882a593Smuzhiyun * DSP can't respond to commands whilst in "high speed" mode. Caused
13*4882a593Smuzhiyun * glitching during playback. Fixed.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * Wed Jul 12 22:02:55 CEST 2000 Uros Bizjak <uros@kss-loka.si>
16*4882a593Smuzhiyun * Cleaned up and rewrote lowlevel routines.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <asm/dma.h>
21*4882a593Smuzhiyun #include <linux/init.h>
22*4882a593Smuzhiyun #include <linux/time.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <sound/core.h>
25*4882a593Smuzhiyun #include <sound/sb.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Uros Bizjak <uros@kss-loka.si>");
28*4882a593Smuzhiyun MODULE_DESCRIPTION("Routines for control of 8-bit SoundBlaster cards and clones");
29*4882a593Smuzhiyun MODULE_LICENSE("GPL");
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define SB8_CLOCK 1000000
32*4882a593Smuzhiyun #define SB8_DEN(v) ((SB8_CLOCK + (v) / 2) / (v))
33*4882a593Smuzhiyun #define SB8_RATE(v) (SB8_CLOCK / SB8_DEN(v))
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct snd_ratnum clock = {
36*4882a593Smuzhiyun .num = SB8_CLOCK,
37*4882a593Smuzhiyun .den_min = 1,
38*4882a593Smuzhiyun .den_max = 256,
39*4882a593Smuzhiyun .den_step = 1,
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_ratnums hw_constraints_clock = {
43*4882a593Smuzhiyun .nrats = 1,
44*4882a593Smuzhiyun .rats = &clock,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const struct snd_ratnum stereo_clocks[] = {
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun .num = SB8_CLOCK,
50*4882a593Smuzhiyun .den_min = SB8_DEN(22050),
51*4882a593Smuzhiyun .den_max = SB8_DEN(22050),
52*4882a593Smuzhiyun .den_step = 1,
53*4882a593Smuzhiyun },
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun .num = SB8_CLOCK,
56*4882a593Smuzhiyun .den_min = SB8_DEN(11025),
57*4882a593Smuzhiyun .den_max = SB8_DEN(11025),
58*4882a593Smuzhiyun .den_step = 1,
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
snd_sb8_hw_constraint_rate_channels(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)62*4882a593Smuzhiyun static int snd_sb8_hw_constraint_rate_channels(struct snd_pcm_hw_params *params,
63*4882a593Smuzhiyun struct snd_pcm_hw_rule *rule)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
66*4882a593Smuzhiyun if (c->min > 1) {
67*4882a593Smuzhiyun unsigned int num = 0, den = 0;
68*4882a593Smuzhiyun int err = snd_interval_ratnum(hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE),
69*4882a593Smuzhiyun 2, stereo_clocks, &num, &den);
70*4882a593Smuzhiyun if (err >= 0 && den) {
71*4882a593Smuzhiyun params->rate_num = num;
72*4882a593Smuzhiyun params->rate_den = den;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun return err;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
snd_sb8_hw_constraint_channels_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)79*4882a593Smuzhiyun static int snd_sb8_hw_constraint_channels_rate(struct snd_pcm_hw_params *params,
80*4882a593Smuzhiyun struct snd_pcm_hw_rule *rule)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
83*4882a593Smuzhiyun if (r->min > SB8_RATE(22050) || r->max <= SB8_RATE(11025)) {
84*4882a593Smuzhiyun struct snd_interval t = { .min = 1, .max = 1 };
85*4882a593Smuzhiyun return snd_interval_refine(hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS), &t);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
snd_sb8_playback_prepare(struct snd_pcm_substream * substream)90*4882a593Smuzhiyun static int snd_sb8_playback_prepare(struct snd_pcm_substream *substream)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun unsigned long flags;
93*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
94*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
95*4882a593Smuzhiyun unsigned int mixreg, rate, size, count;
96*4882a593Smuzhiyun unsigned char format;
97*4882a593Smuzhiyun unsigned char stereo = runtime->channels > 1;
98*4882a593Smuzhiyun int dma;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun rate = runtime->rate;
101*4882a593Smuzhiyun switch (chip->hardware) {
102*4882a593Smuzhiyun case SB_HW_JAZZ16:
103*4882a593Smuzhiyun if (runtime->format == SNDRV_PCM_FORMAT_S16_LE) {
104*4882a593Smuzhiyun if (chip->mode & SB_MODE_CAPTURE_16)
105*4882a593Smuzhiyun return -EBUSY;
106*4882a593Smuzhiyun else
107*4882a593Smuzhiyun chip->mode |= SB_MODE_PLAYBACK_16;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun chip->playback_format = SB_DSP_LO_OUTPUT_AUTO;
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun case SB_HW_PRO:
112*4882a593Smuzhiyun if (runtime->channels > 1) {
113*4882a593Smuzhiyun if (snd_BUG_ON(rate != SB8_RATE(11025) &&
114*4882a593Smuzhiyun rate != SB8_RATE(22050)))
115*4882a593Smuzhiyun return -EINVAL;
116*4882a593Smuzhiyun chip->playback_format = SB_DSP_HI_OUTPUT_AUTO;
117*4882a593Smuzhiyun break;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun fallthrough;
120*4882a593Smuzhiyun case SB_HW_201:
121*4882a593Smuzhiyun if (rate > 23000) {
122*4882a593Smuzhiyun chip->playback_format = SB_DSP_HI_OUTPUT_AUTO;
123*4882a593Smuzhiyun break;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun fallthrough;
126*4882a593Smuzhiyun case SB_HW_20:
127*4882a593Smuzhiyun chip->playback_format = SB_DSP_LO_OUTPUT_AUTO;
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun case SB_HW_10:
130*4882a593Smuzhiyun chip->playback_format = SB_DSP_OUTPUT;
131*4882a593Smuzhiyun break;
132*4882a593Smuzhiyun default:
133*4882a593Smuzhiyun return -EINVAL;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK_16) {
136*4882a593Smuzhiyun format = stereo ? SB_DSP_STEREO_16BIT : SB_DSP_MONO_16BIT;
137*4882a593Smuzhiyun dma = chip->dma16;
138*4882a593Smuzhiyun } else {
139*4882a593Smuzhiyun format = stereo ? SB_DSP_STEREO_8BIT : SB_DSP_MONO_8BIT;
140*4882a593Smuzhiyun chip->mode |= SB_MODE_PLAYBACK_8;
141*4882a593Smuzhiyun dma = chip->dma8;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun size = chip->p_dma_size = snd_pcm_lib_buffer_bytes(substream);
144*4882a593Smuzhiyun count = chip->p_period_size = snd_pcm_lib_period_bytes(substream);
145*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
146*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_SPEAKER_ON);
147*4882a593Smuzhiyun if (chip->hardware == SB_HW_JAZZ16)
148*4882a593Smuzhiyun snd_sbdsp_command(chip, format);
149*4882a593Smuzhiyun else if (stereo) {
150*4882a593Smuzhiyun /* set playback stereo mode */
151*4882a593Smuzhiyun spin_lock(&chip->mixer_lock);
152*4882a593Smuzhiyun mixreg = snd_sbmixer_read(chip, SB_DSP_STEREO_SW);
153*4882a593Smuzhiyun snd_sbmixer_write(chip, SB_DSP_STEREO_SW, mixreg | 0x02);
154*4882a593Smuzhiyun spin_unlock(&chip->mixer_lock);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* Soundblaster hardware programming reference guide, 3-23 */
157*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA8_EXIT);
158*4882a593Smuzhiyun runtime->dma_area[0] = 0x80;
159*4882a593Smuzhiyun snd_dma_program(dma, runtime->dma_addr, 1, DMA_MODE_WRITE);
160*4882a593Smuzhiyun /* force interrupt */
161*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_OUTPUT);
162*4882a593Smuzhiyun snd_sbdsp_command(chip, 0);
163*4882a593Smuzhiyun snd_sbdsp_command(chip, 0);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_SAMPLE_RATE);
166*4882a593Smuzhiyun if (stereo) {
167*4882a593Smuzhiyun snd_sbdsp_command(chip, 256 - runtime->rate_den / 2);
168*4882a593Smuzhiyun spin_lock(&chip->mixer_lock);
169*4882a593Smuzhiyun /* save output filter status and turn it off */
170*4882a593Smuzhiyun mixreg = snd_sbmixer_read(chip, SB_DSP_PLAYBACK_FILT);
171*4882a593Smuzhiyun snd_sbmixer_write(chip, SB_DSP_PLAYBACK_FILT, mixreg | 0x20);
172*4882a593Smuzhiyun spin_unlock(&chip->mixer_lock);
173*4882a593Smuzhiyun /* just use force_mode16 for temporary storate... */
174*4882a593Smuzhiyun chip->force_mode16 = mixreg;
175*4882a593Smuzhiyun } else {
176*4882a593Smuzhiyun snd_sbdsp_command(chip, 256 - runtime->rate_den);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun if (chip->playback_format != SB_DSP_OUTPUT) {
179*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK_16)
180*4882a593Smuzhiyun count /= 2;
181*4882a593Smuzhiyun count--;
182*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_BLOCK_SIZE);
183*4882a593Smuzhiyun snd_sbdsp_command(chip, count & 0xff);
184*4882a593Smuzhiyun snd_sbdsp_command(chip, count >> 8);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
187*4882a593Smuzhiyun snd_dma_program(dma, runtime->dma_addr,
188*4882a593Smuzhiyun size, DMA_MODE_WRITE | DMA_AUTOINIT);
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
snd_sb8_playback_trigger(struct snd_pcm_substream * substream,int cmd)192*4882a593Smuzhiyun static int snd_sb8_playback_trigger(struct snd_pcm_substream *substream,
193*4882a593Smuzhiyun int cmd)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun unsigned long flags;
196*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
197*4882a593Smuzhiyun unsigned int count;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
200*4882a593Smuzhiyun switch (cmd) {
201*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
202*4882a593Smuzhiyun snd_sbdsp_command(chip, chip->playback_format);
203*4882a593Smuzhiyun if (chip->playback_format == SB_DSP_OUTPUT) {
204*4882a593Smuzhiyun count = chip->p_period_size - 1;
205*4882a593Smuzhiyun snd_sbdsp_command(chip, count & 0xff);
206*4882a593Smuzhiyun snd_sbdsp_command(chip, count >> 8);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun break;
209*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
210*4882a593Smuzhiyun if (chip->playback_format == SB_DSP_HI_OUTPUT_AUTO) {
211*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
212*4882a593Smuzhiyun snd_sbdsp_reset(chip);
213*4882a593Smuzhiyun if (runtime->channels > 1) {
214*4882a593Smuzhiyun spin_lock(&chip->mixer_lock);
215*4882a593Smuzhiyun /* restore output filter and set hardware to mono mode */
216*4882a593Smuzhiyun snd_sbmixer_write(chip, SB_DSP_STEREO_SW, chip->force_mode16 & ~0x02);
217*4882a593Smuzhiyun spin_unlock(&chip->mixer_lock);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun } else {
220*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA8_OFF);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_SPEAKER_OFF);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
225*4882a593Smuzhiyun return 0;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
snd_sb8_capture_prepare(struct snd_pcm_substream * substream)228*4882a593Smuzhiyun static int snd_sb8_capture_prepare(struct snd_pcm_substream *substream)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun unsigned long flags;
231*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
232*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
233*4882a593Smuzhiyun unsigned int mixreg, rate, size, count;
234*4882a593Smuzhiyun unsigned char format;
235*4882a593Smuzhiyun unsigned char stereo = runtime->channels > 1;
236*4882a593Smuzhiyun int dma;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun rate = runtime->rate;
239*4882a593Smuzhiyun switch (chip->hardware) {
240*4882a593Smuzhiyun case SB_HW_JAZZ16:
241*4882a593Smuzhiyun if (runtime->format == SNDRV_PCM_FORMAT_S16_LE) {
242*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK_16)
243*4882a593Smuzhiyun return -EBUSY;
244*4882a593Smuzhiyun else
245*4882a593Smuzhiyun chip->mode |= SB_MODE_CAPTURE_16;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun chip->capture_format = SB_DSP_LO_INPUT_AUTO;
248*4882a593Smuzhiyun break;
249*4882a593Smuzhiyun case SB_HW_PRO:
250*4882a593Smuzhiyun if (runtime->channels > 1) {
251*4882a593Smuzhiyun if (snd_BUG_ON(rate != SB8_RATE(11025) &&
252*4882a593Smuzhiyun rate != SB8_RATE(22050)))
253*4882a593Smuzhiyun return -EINVAL;
254*4882a593Smuzhiyun chip->capture_format = SB_DSP_HI_INPUT_AUTO;
255*4882a593Smuzhiyun break;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun chip->capture_format = (rate > 23000) ? SB_DSP_HI_INPUT_AUTO : SB_DSP_LO_INPUT_AUTO;
258*4882a593Smuzhiyun break;
259*4882a593Smuzhiyun case SB_HW_201:
260*4882a593Smuzhiyun if (rate > 13000) {
261*4882a593Smuzhiyun chip->capture_format = SB_DSP_HI_INPUT_AUTO;
262*4882a593Smuzhiyun break;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun fallthrough;
265*4882a593Smuzhiyun case SB_HW_20:
266*4882a593Smuzhiyun chip->capture_format = SB_DSP_LO_INPUT_AUTO;
267*4882a593Smuzhiyun break;
268*4882a593Smuzhiyun case SB_HW_10:
269*4882a593Smuzhiyun chip->capture_format = SB_DSP_INPUT;
270*4882a593Smuzhiyun break;
271*4882a593Smuzhiyun default:
272*4882a593Smuzhiyun return -EINVAL;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun if (chip->mode & SB_MODE_CAPTURE_16) {
275*4882a593Smuzhiyun format = stereo ? SB_DSP_STEREO_16BIT : SB_DSP_MONO_16BIT;
276*4882a593Smuzhiyun dma = chip->dma16;
277*4882a593Smuzhiyun } else {
278*4882a593Smuzhiyun format = stereo ? SB_DSP_STEREO_8BIT : SB_DSP_MONO_8BIT;
279*4882a593Smuzhiyun chip->mode |= SB_MODE_CAPTURE_8;
280*4882a593Smuzhiyun dma = chip->dma8;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun size = chip->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
283*4882a593Smuzhiyun count = chip->c_period_size = snd_pcm_lib_period_bytes(substream);
284*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
285*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_SPEAKER_OFF);
286*4882a593Smuzhiyun if (chip->hardware == SB_HW_JAZZ16)
287*4882a593Smuzhiyun snd_sbdsp_command(chip, format);
288*4882a593Smuzhiyun else if (stereo)
289*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_STEREO_8BIT);
290*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_SAMPLE_RATE);
291*4882a593Smuzhiyun if (stereo) {
292*4882a593Smuzhiyun snd_sbdsp_command(chip, 256 - runtime->rate_den / 2);
293*4882a593Smuzhiyun spin_lock(&chip->mixer_lock);
294*4882a593Smuzhiyun /* save input filter status and turn it off */
295*4882a593Smuzhiyun mixreg = snd_sbmixer_read(chip, SB_DSP_CAPTURE_FILT);
296*4882a593Smuzhiyun snd_sbmixer_write(chip, SB_DSP_CAPTURE_FILT, mixreg | 0x20);
297*4882a593Smuzhiyun spin_unlock(&chip->mixer_lock);
298*4882a593Smuzhiyun /* just use force_mode16 for temporary storate... */
299*4882a593Smuzhiyun chip->force_mode16 = mixreg;
300*4882a593Smuzhiyun } else {
301*4882a593Smuzhiyun snd_sbdsp_command(chip, 256 - runtime->rate_den);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun if (chip->capture_format != SB_DSP_INPUT) {
304*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK_16)
305*4882a593Smuzhiyun count /= 2;
306*4882a593Smuzhiyun count--;
307*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_BLOCK_SIZE);
308*4882a593Smuzhiyun snd_sbdsp_command(chip, count & 0xff);
309*4882a593Smuzhiyun snd_sbdsp_command(chip, count >> 8);
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
312*4882a593Smuzhiyun snd_dma_program(dma, runtime->dma_addr,
313*4882a593Smuzhiyun size, DMA_MODE_READ | DMA_AUTOINIT);
314*4882a593Smuzhiyun return 0;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
snd_sb8_capture_trigger(struct snd_pcm_substream * substream,int cmd)317*4882a593Smuzhiyun static int snd_sb8_capture_trigger(struct snd_pcm_substream *substream,
318*4882a593Smuzhiyun int cmd)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun unsigned long flags;
321*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
322*4882a593Smuzhiyun unsigned int count;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
325*4882a593Smuzhiyun switch (cmd) {
326*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
327*4882a593Smuzhiyun snd_sbdsp_command(chip, chip->capture_format);
328*4882a593Smuzhiyun if (chip->capture_format == SB_DSP_INPUT) {
329*4882a593Smuzhiyun count = chip->c_period_size - 1;
330*4882a593Smuzhiyun snd_sbdsp_command(chip, count & 0xff);
331*4882a593Smuzhiyun snd_sbdsp_command(chip, count >> 8);
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
335*4882a593Smuzhiyun if (chip->capture_format == SB_DSP_HI_INPUT_AUTO) {
336*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
337*4882a593Smuzhiyun snd_sbdsp_reset(chip);
338*4882a593Smuzhiyun if (runtime->channels > 1) {
339*4882a593Smuzhiyun /* restore input filter status */
340*4882a593Smuzhiyun spin_lock(&chip->mixer_lock);
341*4882a593Smuzhiyun snd_sbmixer_write(chip, SB_DSP_CAPTURE_FILT, chip->force_mode16);
342*4882a593Smuzhiyun spin_unlock(&chip->mixer_lock);
343*4882a593Smuzhiyun /* set hardware to mono mode */
344*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_MONO_8BIT);
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun } else {
347*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA8_OFF);
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_SPEAKER_OFF);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
352*4882a593Smuzhiyun return 0;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
snd_sb8dsp_interrupt(struct snd_sb * chip)355*4882a593Smuzhiyun irqreturn_t snd_sb8dsp_interrupt(struct snd_sb *chip)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun struct snd_pcm_substream *substream;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun snd_sb_ack_8bit(chip);
360*4882a593Smuzhiyun switch (chip->mode) {
361*4882a593Smuzhiyun case SB_MODE_PLAYBACK_16: /* ok.. playback is active */
362*4882a593Smuzhiyun if (chip->hardware != SB_HW_JAZZ16)
363*4882a593Smuzhiyun break;
364*4882a593Smuzhiyun fallthrough;
365*4882a593Smuzhiyun case SB_MODE_PLAYBACK_8:
366*4882a593Smuzhiyun substream = chip->playback_substream;
367*4882a593Smuzhiyun if (chip->playback_format == SB_DSP_OUTPUT)
368*4882a593Smuzhiyun snd_sb8_playback_trigger(substream, SNDRV_PCM_TRIGGER_START);
369*4882a593Smuzhiyun snd_pcm_period_elapsed(substream);
370*4882a593Smuzhiyun break;
371*4882a593Smuzhiyun case SB_MODE_CAPTURE_16:
372*4882a593Smuzhiyun if (chip->hardware != SB_HW_JAZZ16)
373*4882a593Smuzhiyun break;
374*4882a593Smuzhiyun fallthrough;
375*4882a593Smuzhiyun case SB_MODE_CAPTURE_8:
376*4882a593Smuzhiyun substream = chip->capture_substream;
377*4882a593Smuzhiyun if (chip->capture_format == SB_DSP_INPUT)
378*4882a593Smuzhiyun snd_sb8_capture_trigger(substream, SNDRV_PCM_TRIGGER_START);
379*4882a593Smuzhiyun snd_pcm_period_elapsed(substream);
380*4882a593Smuzhiyun break;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun return IRQ_HANDLED;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
snd_sb8_playback_pointer(struct snd_pcm_substream * substream)385*4882a593Smuzhiyun static snd_pcm_uframes_t snd_sb8_playback_pointer(struct snd_pcm_substream *substream)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
388*4882a593Smuzhiyun size_t ptr;
389*4882a593Smuzhiyun int dma;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK_8)
392*4882a593Smuzhiyun dma = chip->dma8;
393*4882a593Smuzhiyun else if (chip->mode & SB_MODE_PLAYBACK_16)
394*4882a593Smuzhiyun dma = chip->dma16;
395*4882a593Smuzhiyun else
396*4882a593Smuzhiyun return 0;
397*4882a593Smuzhiyun ptr = snd_dma_pointer(dma, chip->p_dma_size);
398*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, ptr);
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
snd_sb8_capture_pointer(struct snd_pcm_substream * substream)401*4882a593Smuzhiyun static snd_pcm_uframes_t snd_sb8_capture_pointer(struct snd_pcm_substream *substream)
402*4882a593Smuzhiyun {
403*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
404*4882a593Smuzhiyun size_t ptr;
405*4882a593Smuzhiyun int dma;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (chip->mode & SB_MODE_CAPTURE_8)
408*4882a593Smuzhiyun dma = chip->dma8;
409*4882a593Smuzhiyun else if (chip->mode & SB_MODE_CAPTURE_16)
410*4882a593Smuzhiyun dma = chip->dma16;
411*4882a593Smuzhiyun else
412*4882a593Smuzhiyun return 0;
413*4882a593Smuzhiyun ptr = snd_dma_pointer(dma, chip->c_dma_size);
414*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, ptr);
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /*
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun */
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_sb8_playback =
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
424*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
425*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_U8,
426*4882a593Smuzhiyun .rates = (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000 |
427*4882a593Smuzhiyun SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050),
428*4882a593Smuzhiyun .rate_min = 4000,
429*4882a593Smuzhiyun .rate_max = 23000,
430*4882a593Smuzhiyun .channels_min = 1,
431*4882a593Smuzhiyun .channels_max = 1,
432*4882a593Smuzhiyun .buffer_bytes_max = 65536,
433*4882a593Smuzhiyun .period_bytes_min = 64,
434*4882a593Smuzhiyun .period_bytes_max = 65536,
435*4882a593Smuzhiyun .periods_min = 1,
436*4882a593Smuzhiyun .periods_max = 1024,
437*4882a593Smuzhiyun .fifo_size = 0,
438*4882a593Smuzhiyun };
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_sb8_capture =
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
443*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
444*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_U8,
445*4882a593Smuzhiyun .rates = (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000 |
446*4882a593Smuzhiyun SNDRV_PCM_RATE_11025),
447*4882a593Smuzhiyun .rate_min = 4000,
448*4882a593Smuzhiyun .rate_max = 13000,
449*4882a593Smuzhiyun .channels_min = 1,
450*4882a593Smuzhiyun .channels_max = 1,
451*4882a593Smuzhiyun .buffer_bytes_max = 65536,
452*4882a593Smuzhiyun .period_bytes_min = 64,
453*4882a593Smuzhiyun .period_bytes_max = 65536,
454*4882a593Smuzhiyun .periods_min = 1,
455*4882a593Smuzhiyun .periods_max = 1024,
456*4882a593Smuzhiyun .fifo_size = 0,
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun /*
460*4882a593Smuzhiyun *
461*4882a593Smuzhiyun */
462*4882a593Smuzhiyun
snd_sb8_open(struct snd_pcm_substream * substream)463*4882a593Smuzhiyun static int snd_sb8_open(struct snd_pcm_substream *substream)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
466*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
467*4882a593Smuzhiyun unsigned long flags;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun spin_lock_irqsave(&chip->open_lock, flags);
470*4882a593Smuzhiyun if (chip->open) {
471*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
472*4882a593Smuzhiyun return -EAGAIN;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun chip->open |= SB_OPEN_PCM;
475*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
476*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
477*4882a593Smuzhiyun chip->playback_substream = substream;
478*4882a593Smuzhiyun runtime->hw = snd_sb8_playback;
479*4882a593Smuzhiyun } else {
480*4882a593Smuzhiyun chip->capture_substream = substream;
481*4882a593Smuzhiyun runtime->hw = snd_sb8_capture;
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun switch (chip->hardware) {
484*4882a593Smuzhiyun case SB_HW_JAZZ16:
485*4882a593Smuzhiyun if (chip->dma16 == 5 || chip->dma16 == 7)
486*4882a593Smuzhiyun runtime->hw.formats |= SNDRV_PCM_FMTBIT_S16_LE;
487*4882a593Smuzhiyun runtime->hw.rates |= SNDRV_PCM_RATE_8000_48000;
488*4882a593Smuzhiyun runtime->hw.rate_min = 4000;
489*4882a593Smuzhiyun runtime->hw.rate_max = 50000;
490*4882a593Smuzhiyun runtime->hw.channels_max = 2;
491*4882a593Smuzhiyun break;
492*4882a593Smuzhiyun case SB_HW_PRO:
493*4882a593Smuzhiyun runtime->hw.rate_max = 44100;
494*4882a593Smuzhiyun runtime->hw.channels_max = 2;
495*4882a593Smuzhiyun snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
496*4882a593Smuzhiyun snd_sb8_hw_constraint_rate_channels, NULL,
497*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_CHANNELS,
498*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE, -1);
499*4882a593Smuzhiyun snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
500*4882a593Smuzhiyun snd_sb8_hw_constraint_channels_rate, NULL,
501*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE, -1);
502*4882a593Smuzhiyun break;
503*4882a593Smuzhiyun case SB_HW_201:
504*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
505*4882a593Smuzhiyun runtime->hw.rate_max = 44100;
506*4882a593Smuzhiyun } else {
507*4882a593Smuzhiyun runtime->hw.rate_max = 15000;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun default:
510*4882a593Smuzhiyun break;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
513*4882a593Smuzhiyun &hw_constraints_clock);
514*4882a593Smuzhiyun if (chip->dma8 > 3 || chip->dma16 >= 0) {
515*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0,
516*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 2);
517*4882a593Smuzhiyun snd_pcm_hw_constraint_step(runtime, 0,
518*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 2);
519*4882a593Smuzhiyun runtime->hw.buffer_bytes_max = 128 * 1024 * 1024;
520*4882a593Smuzhiyun runtime->hw.period_bytes_max = 128 * 1024 * 1024;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
snd_sb8_close(struct snd_pcm_substream * substream)525*4882a593Smuzhiyun static int snd_sb8_close(struct snd_pcm_substream *substream)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun unsigned long flags;
528*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun chip->playback_substream = NULL;
531*4882a593Smuzhiyun chip->capture_substream = NULL;
532*4882a593Smuzhiyun spin_lock_irqsave(&chip->open_lock, flags);
533*4882a593Smuzhiyun chip->open &= ~SB_OPEN_PCM;
534*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
535*4882a593Smuzhiyun chip->mode &= ~SB_MODE_PLAYBACK;
536*4882a593Smuzhiyun else
537*4882a593Smuzhiyun chip->mode &= ~SB_MODE_CAPTURE;
538*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
539*4882a593Smuzhiyun return 0;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun /*
543*4882a593Smuzhiyun * Initialization part
544*4882a593Smuzhiyun */
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun static const struct snd_pcm_ops snd_sb8_playback_ops = {
547*4882a593Smuzhiyun .open = snd_sb8_open,
548*4882a593Smuzhiyun .close = snd_sb8_close,
549*4882a593Smuzhiyun .prepare = snd_sb8_playback_prepare,
550*4882a593Smuzhiyun .trigger = snd_sb8_playback_trigger,
551*4882a593Smuzhiyun .pointer = snd_sb8_playback_pointer,
552*4882a593Smuzhiyun };
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun static const struct snd_pcm_ops snd_sb8_capture_ops = {
555*4882a593Smuzhiyun .open = snd_sb8_open,
556*4882a593Smuzhiyun .close = snd_sb8_close,
557*4882a593Smuzhiyun .prepare = snd_sb8_capture_prepare,
558*4882a593Smuzhiyun .trigger = snd_sb8_capture_trigger,
559*4882a593Smuzhiyun .pointer = snd_sb8_capture_pointer,
560*4882a593Smuzhiyun };
561*4882a593Smuzhiyun
snd_sb8dsp_pcm(struct snd_sb * chip,int device)562*4882a593Smuzhiyun int snd_sb8dsp_pcm(struct snd_sb *chip, int device)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun struct snd_card *card = chip->card;
565*4882a593Smuzhiyun struct snd_pcm *pcm;
566*4882a593Smuzhiyun int err;
567*4882a593Smuzhiyun size_t max_prealloc = 64 * 1024;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun if ((err = snd_pcm_new(card, "SB8 DSP", device, 1, 1, &pcm)) < 0)
570*4882a593Smuzhiyun return err;
571*4882a593Smuzhiyun sprintf(pcm->name, "DSP v%i.%i", chip->version >> 8, chip->version & 0xff);
572*4882a593Smuzhiyun pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
573*4882a593Smuzhiyun pcm->private_data = chip;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_sb8_playback_ops);
576*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_sb8_capture_ops);
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun if (chip->dma8 > 3 || chip->dma16 >= 0)
579*4882a593Smuzhiyun max_prealloc = 128 * 1024;
580*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
581*4882a593Smuzhiyun card->dev, 64*1024, max_prealloc);
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun return 0;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun EXPORT_SYMBOL(snd_sb8dsp_pcm);
587*4882a593Smuzhiyun EXPORT_SYMBOL(snd_sb8dsp_interrupt);
588*4882a593Smuzhiyun /* sb8_midi.c */
589*4882a593Smuzhiyun EXPORT_SYMBOL(snd_sb8dsp_midi_interrupt);
590*4882a593Smuzhiyun EXPORT_SYMBOL(snd_sb8dsp_midi);
591