1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4*4882a593Smuzhiyun * Routines for control of 16-bit SoundBlaster cards and clones
5*4882a593Smuzhiyun * Note: This is very ugly hardware which uses one 8-bit DMA channel and
6*4882a593Smuzhiyun * second 16-bit DMA channel. Unfortunately 8-bit DMA channel can't
7*4882a593Smuzhiyun * transfer 16-bit samples and 16-bit DMA channels can't transfer
8*4882a593Smuzhiyun * 8-bit samples. This make full duplex more complicated than
9*4882a593Smuzhiyun * can be... People, don't buy these soundcards for full 16-bit
10*4882a593Smuzhiyun * duplex!!!
11*4882a593Smuzhiyun * Note: 16-bit wide is assigned to first direction which made request.
12*4882a593Smuzhiyun * With full duplex - playback is preferred with abstract layer.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * Note: Some chip revisions have hardware bug. Changing capture
15*4882a593Smuzhiyun * channel from full-duplex 8bit DMA to 16bit DMA will block
16*4882a593Smuzhiyun * 16bit DMA transfers from DSP chip (capture) until 8bit transfer
17*4882a593Smuzhiyun * to DSP chip (playback) starts. This bug can be avoided with
18*4882a593Smuzhiyun * "16bit DMA Allocation" setting set to Playback or Capture.
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/io.h>
22*4882a593Smuzhiyun #include <asm/dma.h>
23*4882a593Smuzhiyun #include <linux/init.h>
24*4882a593Smuzhiyun #include <linux/time.h>
25*4882a593Smuzhiyun #include <linux/module.h>
26*4882a593Smuzhiyun #include <sound/core.h>
27*4882a593Smuzhiyun #include <sound/sb.h>
28*4882a593Smuzhiyun #include <sound/sb16_csp.h>
29*4882a593Smuzhiyun #include <sound/mpu401.h>
30*4882a593Smuzhiyun #include <sound/control.h>
31*4882a593Smuzhiyun #include <sound/info.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
34*4882a593Smuzhiyun MODULE_DESCRIPTION("Routines for control of 16-bit SoundBlaster cards and clones");
35*4882a593Smuzhiyun MODULE_LICENSE("GPL");
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define runtime_format_bits(runtime) \
38*4882a593Smuzhiyun ((unsigned int)pcm_format_to_bits((runtime)->format))
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #ifdef CONFIG_SND_SB16_CSP
snd_sb16_csp_playback_prepare(struct snd_sb * chip,struct snd_pcm_runtime * runtime)41*4882a593Smuzhiyun static void snd_sb16_csp_playback_prepare(struct snd_sb *chip, struct snd_pcm_runtime *runtime)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun if (chip->hardware == SB_HW_16CSP) {
44*4882a593Smuzhiyun struct snd_sb_csp *csp = chip->csp;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (csp->running & SNDRV_SB_CSP_ST_LOADED) {
47*4882a593Smuzhiyun /* manually loaded codec */
48*4882a593Smuzhiyun if ((csp->mode & SNDRV_SB_CSP_MODE_DSP_WRITE) &&
49*4882a593Smuzhiyun (runtime_format_bits(runtime) == csp->acc_format)) {
50*4882a593Smuzhiyun /* Supported runtime PCM format for playback */
51*4882a593Smuzhiyun if (csp->ops.csp_use(csp) == 0) {
52*4882a593Smuzhiyun /* If CSP was successfully acquired */
53*4882a593Smuzhiyun goto __start_CSP;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun } else if ((csp->mode & SNDRV_SB_CSP_MODE_QSOUND) && (csp->q_enabled)) {
56*4882a593Smuzhiyun /* QSound decoder is loaded and enabled */
57*4882a593Smuzhiyun if (runtime_format_bits(runtime) & (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
58*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE)) {
59*4882a593Smuzhiyun /* Only for simple PCM formats */
60*4882a593Smuzhiyun if (csp->ops.csp_use(csp) == 0) {
61*4882a593Smuzhiyun /* If CSP was successfully acquired */
62*4882a593Smuzhiyun goto __start_CSP;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun } else if (csp->ops.csp_use(csp) == 0) {
67*4882a593Smuzhiyun /* Acquire CSP and try to autoload hardware codec */
68*4882a593Smuzhiyun if (csp->ops.csp_autoload(csp, runtime->format, SNDRV_SB_CSP_MODE_DSP_WRITE)) {
69*4882a593Smuzhiyun /* Unsupported format, release CSP */
70*4882a593Smuzhiyun csp->ops.csp_unuse(csp);
71*4882a593Smuzhiyun } else {
72*4882a593Smuzhiyun __start_CSP:
73*4882a593Smuzhiyun /* Try to start CSP */
74*4882a593Smuzhiyun if (csp->ops.csp_start(csp, (chip->mode & SB_MODE_PLAYBACK_16) ?
75*4882a593Smuzhiyun SNDRV_SB_CSP_SAMPLE_16BIT : SNDRV_SB_CSP_SAMPLE_8BIT,
76*4882a593Smuzhiyun (runtime->channels > 1) ?
77*4882a593Smuzhiyun SNDRV_SB_CSP_STEREO : SNDRV_SB_CSP_MONO)) {
78*4882a593Smuzhiyun /* Failed, release CSP */
79*4882a593Smuzhiyun csp->ops.csp_unuse(csp);
80*4882a593Smuzhiyun } else {
81*4882a593Smuzhiyun /* Success, CSP acquired and running */
82*4882a593Smuzhiyun chip->open = SNDRV_SB_CSP_MODE_DSP_WRITE;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
snd_sb16_csp_capture_prepare(struct snd_sb * chip,struct snd_pcm_runtime * runtime)89*4882a593Smuzhiyun static void snd_sb16_csp_capture_prepare(struct snd_sb *chip, struct snd_pcm_runtime *runtime)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun if (chip->hardware == SB_HW_16CSP) {
92*4882a593Smuzhiyun struct snd_sb_csp *csp = chip->csp;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (csp->running & SNDRV_SB_CSP_ST_LOADED) {
95*4882a593Smuzhiyun /* manually loaded codec */
96*4882a593Smuzhiyun if ((csp->mode & SNDRV_SB_CSP_MODE_DSP_READ) &&
97*4882a593Smuzhiyun (runtime_format_bits(runtime) == csp->acc_format)) {
98*4882a593Smuzhiyun /* Supported runtime PCM format for capture */
99*4882a593Smuzhiyun if (csp->ops.csp_use(csp) == 0) {
100*4882a593Smuzhiyun /* If CSP was successfully acquired */
101*4882a593Smuzhiyun goto __start_CSP;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun } else if (csp->ops.csp_use(csp) == 0) {
105*4882a593Smuzhiyun /* Acquire CSP and try to autoload hardware codec */
106*4882a593Smuzhiyun if (csp->ops.csp_autoload(csp, runtime->format, SNDRV_SB_CSP_MODE_DSP_READ)) {
107*4882a593Smuzhiyun /* Unsupported format, release CSP */
108*4882a593Smuzhiyun csp->ops.csp_unuse(csp);
109*4882a593Smuzhiyun } else {
110*4882a593Smuzhiyun __start_CSP:
111*4882a593Smuzhiyun /* Try to start CSP */
112*4882a593Smuzhiyun if (csp->ops.csp_start(csp, (chip->mode & SB_MODE_CAPTURE_16) ?
113*4882a593Smuzhiyun SNDRV_SB_CSP_SAMPLE_16BIT : SNDRV_SB_CSP_SAMPLE_8BIT,
114*4882a593Smuzhiyun (runtime->channels > 1) ?
115*4882a593Smuzhiyun SNDRV_SB_CSP_STEREO : SNDRV_SB_CSP_MONO)) {
116*4882a593Smuzhiyun /* Failed, release CSP */
117*4882a593Smuzhiyun csp->ops.csp_unuse(csp);
118*4882a593Smuzhiyun } else {
119*4882a593Smuzhiyun /* Success, CSP acquired and running */
120*4882a593Smuzhiyun chip->open = SNDRV_SB_CSP_MODE_DSP_READ;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
snd_sb16_csp_update(struct snd_sb * chip)127*4882a593Smuzhiyun static void snd_sb16_csp_update(struct snd_sb *chip)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun if (chip->hardware == SB_HW_16CSP) {
130*4882a593Smuzhiyun struct snd_sb_csp *csp = chip->csp;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if (csp->qpos_changed) {
133*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
134*4882a593Smuzhiyun csp->ops.csp_qsound_transfer (csp);
135*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
snd_sb16_csp_playback_open(struct snd_sb * chip,struct snd_pcm_runtime * runtime)140*4882a593Smuzhiyun static void snd_sb16_csp_playback_open(struct snd_sb *chip, struct snd_pcm_runtime *runtime)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun /* CSP decoders (QSound excluded) support only 16bit transfers */
143*4882a593Smuzhiyun if (chip->hardware == SB_HW_16CSP) {
144*4882a593Smuzhiyun struct snd_sb_csp *csp = chip->csp;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (csp->running & SNDRV_SB_CSP_ST_LOADED) {
147*4882a593Smuzhiyun /* manually loaded codec */
148*4882a593Smuzhiyun if (csp->mode & SNDRV_SB_CSP_MODE_DSP_WRITE) {
149*4882a593Smuzhiyun runtime->hw.formats |= csp->acc_format;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun } else {
152*4882a593Smuzhiyun /* autoloaded codecs */
153*4882a593Smuzhiyun runtime->hw.formats |= SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
154*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_IMA_ADPCM;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
snd_sb16_csp_playback_close(struct snd_sb * chip)159*4882a593Smuzhiyun static void snd_sb16_csp_playback_close(struct snd_sb *chip)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun if ((chip->hardware == SB_HW_16CSP) && (chip->open == SNDRV_SB_CSP_MODE_DSP_WRITE)) {
162*4882a593Smuzhiyun struct snd_sb_csp *csp = chip->csp;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if (csp->ops.csp_stop(csp) == 0) {
165*4882a593Smuzhiyun csp->ops.csp_unuse(csp);
166*4882a593Smuzhiyun chip->open = 0;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
snd_sb16_csp_capture_open(struct snd_sb * chip,struct snd_pcm_runtime * runtime)171*4882a593Smuzhiyun static void snd_sb16_csp_capture_open(struct snd_sb *chip, struct snd_pcm_runtime *runtime)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun /* CSP coders support only 16bit transfers */
174*4882a593Smuzhiyun if (chip->hardware == SB_HW_16CSP) {
175*4882a593Smuzhiyun struct snd_sb_csp *csp = chip->csp;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (csp->running & SNDRV_SB_CSP_ST_LOADED) {
178*4882a593Smuzhiyun /* manually loaded codec */
179*4882a593Smuzhiyun if (csp->mode & SNDRV_SB_CSP_MODE_DSP_READ) {
180*4882a593Smuzhiyun runtime->hw.formats |= csp->acc_format;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun } else {
183*4882a593Smuzhiyun /* autoloaded codecs */
184*4882a593Smuzhiyun runtime->hw.formats |= SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
185*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_IMA_ADPCM;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
snd_sb16_csp_capture_close(struct snd_sb * chip)190*4882a593Smuzhiyun static void snd_sb16_csp_capture_close(struct snd_sb *chip)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun if ((chip->hardware == SB_HW_16CSP) && (chip->open == SNDRV_SB_CSP_MODE_DSP_READ)) {
193*4882a593Smuzhiyun struct snd_sb_csp *csp = chip->csp;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun if (csp->ops.csp_stop(csp) == 0) {
196*4882a593Smuzhiyun csp->ops.csp_unuse(csp);
197*4882a593Smuzhiyun chip->open = 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun #else
202*4882a593Smuzhiyun #define snd_sb16_csp_playback_prepare(chip, runtime) /*nop*/
203*4882a593Smuzhiyun #define snd_sb16_csp_capture_prepare(chip, runtime) /*nop*/
204*4882a593Smuzhiyun #define snd_sb16_csp_update(chip) /*nop*/
205*4882a593Smuzhiyun #define snd_sb16_csp_playback_open(chip, runtime) /*nop*/
206*4882a593Smuzhiyun #define snd_sb16_csp_playback_close(chip) /*nop*/
207*4882a593Smuzhiyun #define snd_sb16_csp_capture_open(chip, runtime) /*nop*/
208*4882a593Smuzhiyun #define snd_sb16_csp_capture_close(chip) /*nop*/
209*4882a593Smuzhiyun #endif
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun
snd_sb16_setup_rate(struct snd_sb * chip,unsigned short rate,int channel)212*4882a593Smuzhiyun static void snd_sb16_setup_rate(struct snd_sb *chip,
213*4882a593Smuzhiyun unsigned short rate,
214*4882a593Smuzhiyun int channel)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun unsigned long flags;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
219*4882a593Smuzhiyun if (chip->mode & (channel == SNDRV_PCM_STREAM_PLAYBACK ? SB_MODE_PLAYBACK_16 : SB_MODE_CAPTURE_16))
220*4882a593Smuzhiyun snd_sb_ack_16bit(chip);
221*4882a593Smuzhiyun else
222*4882a593Smuzhiyun snd_sb_ack_8bit(chip);
223*4882a593Smuzhiyun if (!(chip->mode & SB_RATE_LOCK)) {
224*4882a593Smuzhiyun chip->locked_rate = rate;
225*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_SAMPLE_RATE_IN);
226*4882a593Smuzhiyun snd_sbdsp_command(chip, rate >> 8);
227*4882a593Smuzhiyun snd_sbdsp_command(chip, rate & 0xff);
228*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_SAMPLE_RATE_OUT);
229*4882a593Smuzhiyun snd_sbdsp_command(chip, rate >> 8);
230*4882a593Smuzhiyun snd_sbdsp_command(chip, rate & 0xff);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
snd_sb16_playback_prepare(struct snd_pcm_substream * substream)235*4882a593Smuzhiyun static int snd_sb16_playback_prepare(struct snd_pcm_substream *substream)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun unsigned long flags;
238*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
239*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
240*4882a593Smuzhiyun unsigned char format;
241*4882a593Smuzhiyun unsigned int size, count, dma;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun snd_sb16_csp_playback_prepare(chip, runtime);
244*4882a593Smuzhiyun if (snd_pcm_format_unsigned(runtime->format) > 0) {
245*4882a593Smuzhiyun format = runtime->channels > 1 ? SB_DSP4_MODE_UNS_STEREO : SB_DSP4_MODE_UNS_MONO;
246*4882a593Smuzhiyun } else {
247*4882a593Smuzhiyun format = runtime->channels > 1 ? SB_DSP4_MODE_SIGN_STEREO : SB_DSP4_MODE_SIGN_MONO;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun snd_sb16_setup_rate(chip, runtime->rate, SNDRV_PCM_STREAM_PLAYBACK);
251*4882a593Smuzhiyun size = chip->p_dma_size = snd_pcm_lib_buffer_bytes(substream);
252*4882a593Smuzhiyun dma = (chip->mode & SB_MODE_PLAYBACK_8) ? chip->dma8 : chip->dma16;
253*4882a593Smuzhiyun snd_dma_program(dma, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun count = snd_pcm_lib_period_bytes(substream);
256*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
257*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK_16) {
258*4882a593Smuzhiyun count >>= 1;
259*4882a593Smuzhiyun count--;
260*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP4_OUT16_AI);
261*4882a593Smuzhiyun snd_sbdsp_command(chip, format);
262*4882a593Smuzhiyun snd_sbdsp_command(chip, count & 0xff);
263*4882a593Smuzhiyun snd_sbdsp_command(chip, count >> 8);
264*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA16_OFF);
265*4882a593Smuzhiyun } else {
266*4882a593Smuzhiyun count--;
267*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP4_OUT8_AI);
268*4882a593Smuzhiyun snd_sbdsp_command(chip, format);
269*4882a593Smuzhiyun snd_sbdsp_command(chip, count & 0xff);
270*4882a593Smuzhiyun snd_sbdsp_command(chip, count >> 8);
271*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA8_OFF);
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
274*4882a593Smuzhiyun return 0;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
snd_sb16_playback_trigger(struct snd_pcm_substream * substream,int cmd)277*4882a593Smuzhiyun static int snd_sb16_playback_trigger(struct snd_pcm_substream *substream,
278*4882a593Smuzhiyun int cmd)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
281*4882a593Smuzhiyun int result = 0;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
284*4882a593Smuzhiyun switch (cmd) {
285*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
286*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
287*4882a593Smuzhiyun chip->mode |= SB_RATE_LOCK_PLAYBACK;
288*4882a593Smuzhiyun snd_sbdsp_command(chip, chip->mode & SB_MODE_PLAYBACK_16 ? SB_DSP_DMA16_ON : SB_DSP_DMA8_ON);
289*4882a593Smuzhiyun break;
290*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
291*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
292*4882a593Smuzhiyun snd_sbdsp_command(chip, chip->mode & SB_MODE_PLAYBACK_16 ? SB_DSP_DMA16_OFF : SB_DSP_DMA8_OFF);
293*4882a593Smuzhiyun /* next two lines are needed for some types of DSP4 (SB AWE 32 - 4.13) */
294*4882a593Smuzhiyun if (chip->mode & SB_RATE_LOCK_CAPTURE)
295*4882a593Smuzhiyun snd_sbdsp_command(chip, chip->mode & SB_MODE_CAPTURE_16 ? SB_DSP_DMA16_ON : SB_DSP_DMA8_ON);
296*4882a593Smuzhiyun chip->mode &= ~SB_RATE_LOCK_PLAYBACK;
297*4882a593Smuzhiyun break;
298*4882a593Smuzhiyun default:
299*4882a593Smuzhiyun result = -EINVAL;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
302*4882a593Smuzhiyun return result;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
snd_sb16_capture_prepare(struct snd_pcm_substream * substream)305*4882a593Smuzhiyun static int snd_sb16_capture_prepare(struct snd_pcm_substream *substream)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun unsigned long flags;
308*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
309*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
310*4882a593Smuzhiyun unsigned char format;
311*4882a593Smuzhiyun unsigned int size, count, dma;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun snd_sb16_csp_capture_prepare(chip, runtime);
314*4882a593Smuzhiyun if (snd_pcm_format_unsigned(runtime->format) > 0) {
315*4882a593Smuzhiyun format = runtime->channels > 1 ? SB_DSP4_MODE_UNS_STEREO : SB_DSP4_MODE_UNS_MONO;
316*4882a593Smuzhiyun } else {
317*4882a593Smuzhiyun format = runtime->channels > 1 ? SB_DSP4_MODE_SIGN_STEREO : SB_DSP4_MODE_SIGN_MONO;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun snd_sb16_setup_rate(chip, runtime->rate, SNDRV_PCM_STREAM_CAPTURE);
320*4882a593Smuzhiyun size = chip->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
321*4882a593Smuzhiyun dma = (chip->mode & SB_MODE_CAPTURE_8) ? chip->dma8 : chip->dma16;
322*4882a593Smuzhiyun snd_dma_program(dma, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun count = snd_pcm_lib_period_bytes(substream);
325*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
326*4882a593Smuzhiyun if (chip->mode & SB_MODE_CAPTURE_16) {
327*4882a593Smuzhiyun count >>= 1;
328*4882a593Smuzhiyun count--;
329*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP4_IN16_AI);
330*4882a593Smuzhiyun snd_sbdsp_command(chip, format);
331*4882a593Smuzhiyun snd_sbdsp_command(chip, count & 0xff);
332*4882a593Smuzhiyun snd_sbdsp_command(chip, count >> 8);
333*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA16_OFF);
334*4882a593Smuzhiyun } else {
335*4882a593Smuzhiyun count--;
336*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP4_IN8_AI);
337*4882a593Smuzhiyun snd_sbdsp_command(chip, format);
338*4882a593Smuzhiyun snd_sbdsp_command(chip, count & 0xff);
339*4882a593Smuzhiyun snd_sbdsp_command(chip, count >> 8);
340*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA8_OFF);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
343*4882a593Smuzhiyun return 0;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
snd_sb16_capture_trigger(struct snd_pcm_substream * substream,int cmd)346*4882a593Smuzhiyun static int snd_sb16_capture_trigger(struct snd_pcm_substream *substream,
347*4882a593Smuzhiyun int cmd)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
350*4882a593Smuzhiyun int result = 0;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
353*4882a593Smuzhiyun switch (cmd) {
354*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
355*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
356*4882a593Smuzhiyun chip->mode |= SB_RATE_LOCK_CAPTURE;
357*4882a593Smuzhiyun snd_sbdsp_command(chip, chip->mode & SB_MODE_CAPTURE_16 ? SB_DSP_DMA16_ON : SB_DSP_DMA8_ON);
358*4882a593Smuzhiyun break;
359*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
360*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
361*4882a593Smuzhiyun snd_sbdsp_command(chip, chip->mode & SB_MODE_CAPTURE_16 ? SB_DSP_DMA16_OFF : SB_DSP_DMA8_OFF);
362*4882a593Smuzhiyun /* next two lines are needed for some types of DSP4 (SB AWE 32 - 4.13) */
363*4882a593Smuzhiyun if (chip->mode & SB_RATE_LOCK_PLAYBACK)
364*4882a593Smuzhiyun snd_sbdsp_command(chip, chip->mode & SB_MODE_PLAYBACK_16 ? SB_DSP_DMA16_ON : SB_DSP_DMA8_ON);
365*4882a593Smuzhiyun chip->mode &= ~SB_RATE_LOCK_CAPTURE;
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun default:
368*4882a593Smuzhiyun result = -EINVAL;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
371*4882a593Smuzhiyun return result;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
snd_sb16dsp_interrupt(int irq,void * dev_id)374*4882a593Smuzhiyun irqreturn_t snd_sb16dsp_interrupt(int irq, void *dev_id)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun struct snd_sb *chip = dev_id;
377*4882a593Smuzhiyun unsigned char status;
378*4882a593Smuzhiyun int ok;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun spin_lock(&chip->mixer_lock);
381*4882a593Smuzhiyun status = snd_sbmixer_read(chip, SB_DSP4_IRQSTATUS);
382*4882a593Smuzhiyun spin_unlock(&chip->mixer_lock);
383*4882a593Smuzhiyun if ((status & SB_IRQTYPE_MPUIN) && chip->rmidi_callback)
384*4882a593Smuzhiyun chip->rmidi_callback(irq, chip->rmidi->private_data);
385*4882a593Smuzhiyun if (status & SB_IRQTYPE_8BIT) {
386*4882a593Smuzhiyun ok = 0;
387*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK_8) {
388*4882a593Smuzhiyun snd_pcm_period_elapsed(chip->playback_substream);
389*4882a593Smuzhiyun snd_sb16_csp_update(chip);
390*4882a593Smuzhiyun ok++;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun if (chip->mode & SB_MODE_CAPTURE_8) {
393*4882a593Smuzhiyun snd_pcm_period_elapsed(chip->capture_substream);
394*4882a593Smuzhiyun ok++;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
397*4882a593Smuzhiyun if (!ok)
398*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA8_OFF);
399*4882a593Smuzhiyun snd_sb_ack_8bit(chip);
400*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun if (status & SB_IRQTYPE_16BIT) {
403*4882a593Smuzhiyun ok = 0;
404*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK_16) {
405*4882a593Smuzhiyun snd_pcm_period_elapsed(chip->playback_substream);
406*4882a593Smuzhiyun snd_sb16_csp_update(chip);
407*4882a593Smuzhiyun ok++;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun if (chip->mode & SB_MODE_CAPTURE_16) {
410*4882a593Smuzhiyun snd_pcm_period_elapsed(chip->capture_substream);
411*4882a593Smuzhiyun ok++;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun spin_lock(&chip->reg_lock);
414*4882a593Smuzhiyun if (!ok)
415*4882a593Smuzhiyun snd_sbdsp_command(chip, SB_DSP_DMA16_OFF);
416*4882a593Smuzhiyun snd_sb_ack_16bit(chip);
417*4882a593Smuzhiyun spin_unlock(&chip->reg_lock);
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun return IRQ_HANDLED;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun /*
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun */
425*4882a593Smuzhiyun
snd_sb16_playback_pointer(struct snd_pcm_substream * substream)426*4882a593Smuzhiyun static snd_pcm_uframes_t snd_sb16_playback_pointer(struct snd_pcm_substream *substream)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
429*4882a593Smuzhiyun unsigned int dma;
430*4882a593Smuzhiyun size_t ptr;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun dma = (chip->mode & SB_MODE_PLAYBACK_8) ? chip->dma8 : chip->dma16;
433*4882a593Smuzhiyun ptr = snd_dma_pointer(dma, chip->p_dma_size);
434*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, ptr);
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
snd_sb16_capture_pointer(struct snd_pcm_substream * substream)437*4882a593Smuzhiyun static snd_pcm_uframes_t snd_sb16_capture_pointer(struct snd_pcm_substream *substream)
438*4882a593Smuzhiyun {
439*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
440*4882a593Smuzhiyun unsigned int dma;
441*4882a593Smuzhiyun size_t ptr;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun dma = (chip->mode & SB_MODE_CAPTURE_8) ? chip->dma8 : chip->dma16;
444*4882a593Smuzhiyun ptr = snd_dma_pointer(dma, chip->c_dma_size);
445*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, ptr);
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun /*
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun */
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_sb16_playback =
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
455*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
456*4882a593Smuzhiyun .formats = 0,
457*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_44100,
458*4882a593Smuzhiyun .rate_min = 4000,
459*4882a593Smuzhiyun .rate_max = 44100,
460*4882a593Smuzhiyun .channels_min = 1,
461*4882a593Smuzhiyun .channels_max = 2,
462*4882a593Smuzhiyun .buffer_bytes_max = (128*1024),
463*4882a593Smuzhiyun .period_bytes_min = 64,
464*4882a593Smuzhiyun .period_bytes_max = (128*1024),
465*4882a593Smuzhiyun .periods_min = 1,
466*4882a593Smuzhiyun .periods_max = 1024,
467*4882a593Smuzhiyun .fifo_size = 0,
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_sb16_capture =
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
473*4882a593Smuzhiyun SNDRV_PCM_INFO_MMAP_VALID),
474*4882a593Smuzhiyun .formats = 0,
475*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_44100,
476*4882a593Smuzhiyun .rate_min = 4000,
477*4882a593Smuzhiyun .rate_max = 44100,
478*4882a593Smuzhiyun .channels_min = 1,
479*4882a593Smuzhiyun .channels_max = 2,
480*4882a593Smuzhiyun .buffer_bytes_max = (128*1024),
481*4882a593Smuzhiyun .period_bytes_min = 64,
482*4882a593Smuzhiyun .period_bytes_max = (128*1024),
483*4882a593Smuzhiyun .periods_min = 1,
484*4882a593Smuzhiyun .periods_max = 1024,
485*4882a593Smuzhiyun .fifo_size = 0,
486*4882a593Smuzhiyun };
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun /*
489*4882a593Smuzhiyun * open/close
490*4882a593Smuzhiyun */
491*4882a593Smuzhiyun
snd_sb16_playback_open(struct snd_pcm_substream * substream)492*4882a593Smuzhiyun static int snd_sb16_playback_open(struct snd_pcm_substream *substream)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun unsigned long flags;
495*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
496*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun spin_lock_irqsave(&chip->open_lock, flags);
499*4882a593Smuzhiyun if (chip->mode & SB_MODE_PLAYBACK) {
500*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
501*4882a593Smuzhiyun return -EAGAIN;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun runtime->hw = snd_sb16_playback;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun /* skip if 16 bit DMA was reserved for capture */
506*4882a593Smuzhiyun if (chip->force_mode16 & SB_MODE_CAPTURE_16)
507*4882a593Smuzhiyun goto __skip_16bit;
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun if (chip->dma16 >= 0 && !(chip->mode & SB_MODE_CAPTURE_16)) {
510*4882a593Smuzhiyun chip->mode |= SB_MODE_PLAYBACK_16;
511*4882a593Smuzhiyun runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE;
512*4882a593Smuzhiyun /* Vibra16X hack */
513*4882a593Smuzhiyun if (chip->dma16 <= 3) {
514*4882a593Smuzhiyun runtime->hw.buffer_bytes_max =
515*4882a593Smuzhiyun runtime->hw.period_bytes_max = 64 * 1024;
516*4882a593Smuzhiyun } else {
517*4882a593Smuzhiyun snd_sb16_csp_playback_open(chip, runtime);
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun goto __open_ok;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun __skip_16bit:
523*4882a593Smuzhiyun if (chip->dma8 >= 0 && !(chip->mode & SB_MODE_CAPTURE_8)) {
524*4882a593Smuzhiyun chip->mode |= SB_MODE_PLAYBACK_8;
525*4882a593Smuzhiyun /* DSP v 4.xx can transfer 16bit data through 8bit DMA channel, SBHWPG 2-7 */
526*4882a593Smuzhiyun if (chip->dma16 < 0) {
527*4882a593Smuzhiyun runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE;
528*4882a593Smuzhiyun chip->mode |= SB_MODE_PLAYBACK_16;
529*4882a593Smuzhiyun } else {
530*4882a593Smuzhiyun runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8;
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun runtime->hw.buffer_bytes_max =
533*4882a593Smuzhiyun runtime->hw.period_bytes_max = 64 * 1024;
534*4882a593Smuzhiyun goto __open_ok;
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
537*4882a593Smuzhiyun return -EAGAIN;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun __open_ok:
540*4882a593Smuzhiyun if (chip->hardware == SB_HW_ALS100)
541*4882a593Smuzhiyun runtime->hw.rate_max = 48000;
542*4882a593Smuzhiyun if (chip->hardware == SB_HW_CS5530) {
543*4882a593Smuzhiyun runtime->hw.buffer_bytes_max = 32 * 1024;
544*4882a593Smuzhiyun runtime->hw.periods_min = 2;
545*4882a593Smuzhiyun runtime->hw.rate_min = 44100;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun if (chip->mode & SB_RATE_LOCK)
548*4882a593Smuzhiyun runtime->hw.rate_min = runtime->hw.rate_max = chip->locked_rate;
549*4882a593Smuzhiyun chip->playback_substream = substream;
550*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
551*4882a593Smuzhiyun return 0;
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun
snd_sb16_playback_close(struct snd_pcm_substream * substream)554*4882a593Smuzhiyun static int snd_sb16_playback_close(struct snd_pcm_substream *substream)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun unsigned long flags;
557*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun snd_sb16_csp_playback_close(chip);
560*4882a593Smuzhiyun spin_lock_irqsave(&chip->open_lock, flags);
561*4882a593Smuzhiyun chip->playback_substream = NULL;
562*4882a593Smuzhiyun chip->mode &= ~SB_MODE_PLAYBACK;
563*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
564*4882a593Smuzhiyun return 0;
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
snd_sb16_capture_open(struct snd_pcm_substream * substream)567*4882a593Smuzhiyun static int snd_sb16_capture_open(struct snd_pcm_substream *substream)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun unsigned long flags;
570*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
571*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun spin_lock_irqsave(&chip->open_lock, flags);
574*4882a593Smuzhiyun if (chip->mode & SB_MODE_CAPTURE) {
575*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
576*4882a593Smuzhiyun return -EAGAIN;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun runtime->hw = snd_sb16_capture;
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun /* skip if 16 bit DMA was reserved for playback */
581*4882a593Smuzhiyun if (chip->force_mode16 & SB_MODE_PLAYBACK_16)
582*4882a593Smuzhiyun goto __skip_16bit;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun if (chip->dma16 >= 0 && !(chip->mode & SB_MODE_PLAYBACK_16)) {
585*4882a593Smuzhiyun chip->mode |= SB_MODE_CAPTURE_16;
586*4882a593Smuzhiyun runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE;
587*4882a593Smuzhiyun /* Vibra16X hack */
588*4882a593Smuzhiyun if (chip->dma16 <= 3) {
589*4882a593Smuzhiyun runtime->hw.buffer_bytes_max =
590*4882a593Smuzhiyun runtime->hw.period_bytes_max = 64 * 1024;
591*4882a593Smuzhiyun } else {
592*4882a593Smuzhiyun snd_sb16_csp_capture_open(chip, runtime);
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun goto __open_ok;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun __skip_16bit:
598*4882a593Smuzhiyun if (chip->dma8 >= 0 && !(chip->mode & SB_MODE_PLAYBACK_8)) {
599*4882a593Smuzhiyun chip->mode |= SB_MODE_CAPTURE_8;
600*4882a593Smuzhiyun /* DSP v 4.xx can transfer 16bit data through 8bit DMA channel, SBHWPG 2-7 */
601*4882a593Smuzhiyun if (chip->dma16 < 0) {
602*4882a593Smuzhiyun runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE;
603*4882a593Smuzhiyun chip->mode |= SB_MODE_CAPTURE_16;
604*4882a593Smuzhiyun } else {
605*4882a593Smuzhiyun runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun runtime->hw.buffer_bytes_max =
608*4882a593Smuzhiyun runtime->hw.period_bytes_max = 64 * 1024;
609*4882a593Smuzhiyun goto __open_ok;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
612*4882a593Smuzhiyun return -EAGAIN;
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun __open_ok:
615*4882a593Smuzhiyun if (chip->hardware == SB_HW_ALS100)
616*4882a593Smuzhiyun runtime->hw.rate_max = 48000;
617*4882a593Smuzhiyun if (chip->hardware == SB_HW_CS5530) {
618*4882a593Smuzhiyun runtime->hw.buffer_bytes_max = 32 * 1024;
619*4882a593Smuzhiyun runtime->hw.periods_min = 2;
620*4882a593Smuzhiyun runtime->hw.rate_min = 44100;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun if (chip->mode & SB_RATE_LOCK)
623*4882a593Smuzhiyun runtime->hw.rate_min = runtime->hw.rate_max = chip->locked_rate;
624*4882a593Smuzhiyun chip->capture_substream = substream;
625*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
626*4882a593Smuzhiyun return 0;
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun
snd_sb16_capture_close(struct snd_pcm_substream * substream)629*4882a593Smuzhiyun static int snd_sb16_capture_close(struct snd_pcm_substream *substream)
630*4882a593Smuzhiyun {
631*4882a593Smuzhiyun unsigned long flags;
632*4882a593Smuzhiyun struct snd_sb *chip = snd_pcm_substream_chip(substream);
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun snd_sb16_csp_capture_close(chip);
635*4882a593Smuzhiyun spin_lock_irqsave(&chip->open_lock, flags);
636*4882a593Smuzhiyun chip->capture_substream = NULL;
637*4882a593Smuzhiyun chip->mode &= ~SB_MODE_CAPTURE;
638*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->open_lock, flags);
639*4882a593Smuzhiyun return 0;
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun /*
643*4882a593Smuzhiyun * DMA control interface
644*4882a593Smuzhiyun */
645*4882a593Smuzhiyun
snd_sb16_set_dma_mode(struct snd_sb * chip,int what)646*4882a593Smuzhiyun static int snd_sb16_set_dma_mode(struct snd_sb *chip, int what)
647*4882a593Smuzhiyun {
648*4882a593Smuzhiyun if (chip->dma8 < 0 || chip->dma16 < 0) {
649*4882a593Smuzhiyun if (snd_BUG_ON(what))
650*4882a593Smuzhiyun return -EINVAL;
651*4882a593Smuzhiyun return 0;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun if (what == 0) {
654*4882a593Smuzhiyun chip->force_mode16 = 0;
655*4882a593Smuzhiyun } else if (what == 1) {
656*4882a593Smuzhiyun chip->force_mode16 = SB_MODE_PLAYBACK_16;
657*4882a593Smuzhiyun } else if (what == 2) {
658*4882a593Smuzhiyun chip->force_mode16 = SB_MODE_CAPTURE_16;
659*4882a593Smuzhiyun } else {
660*4882a593Smuzhiyun return -EINVAL;
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun return 0;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
snd_sb16_get_dma_mode(struct snd_sb * chip)665*4882a593Smuzhiyun static int snd_sb16_get_dma_mode(struct snd_sb *chip)
666*4882a593Smuzhiyun {
667*4882a593Smuzhiyun if (chip->dma8 < 0 || chip->dma16 < 0)
668*4882a593Smuzhiyun return 0;
669*4882a593Smuzhiyun switch (chip->force_mode16) {
670*4882a593Smuzhiyun case SB_MODE_PLAYBACK_16:
671*4882a593Smuzhiyun return 1;
672*4882a593Smuzhiyun case SB_MODE_CAPTURE_16:
673*4882a593Smuzhiyun return 2;
674*4882a593Smuzhiyun default:
675*4882a593Smuzhiyun return 0;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
snd_sb16_dma_control_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)679*4882a593Smuzhiyun static int snd_sb16_dma_control_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun static const char * const texts[3] = {
682*4882a593Smuzhiyun "Auto", "Playback", "Capture"
683*4882a593Smuzhiyun };
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun return snd_ctl_enum_info(uinfo, 1, 3, texts);
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
snd_sb16_dma_control_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)688*4882a593Smuzhiyun static int snd_sb16_dma_control_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
689*4882a593Smuzhiyun {
690*4882a593Smuzhiyun struct snd_sb *chip = snd_kcontrol_chip(kcontrol);
691*4882a593Smuzhiyun unsigned long flags;
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
694*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = snd_sb16_get_dma_mode(chip);
695*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
696*4882a593Smuzhiyun return 0;
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
snd_sb16_dma_control_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)699*4882a593Smuzhiyun static int snd_sb16_dma_control_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
700*4882a593Smuzhiyun {
701*4882a593Smuzhiyun struct snd_sb *chip = snd_kcontrol_chip(kcontrol);
702*4882a593Smuzhiyun unsigned long flags;
703*4882a593Smuzhiyun unsigned char nval, oval;
704*4882a593Smuzhiyun int change;
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun if ((nval = ucontrol->value.enumerated.item[0]) > 2)
707*4882a593Smuzhiyun return -EINVAL;
708*4882a593Smuzhiyun spin_lock_irqsave(&chip->reg_lock, flags);
709*4882a593Smuzhiyun oval = snd_sb16_get_dma_mode(chip);
710*4882a593Smuzhiyun change = nval != oval;
711*4882a593Smuzhiyun snd_sb16_set_dma_mode(chip, nval);
712*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->reg_lock, flags);
713*4882a593Smuzhiyun return change;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_sb16_dma_control = {
717*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_CARD,
718*4882a593Smuzhiyun .name = "16-bit DMA Allocation",
719*4882a593Smuzhiyun .info = snd_sb16_dma_control_info,
720*4882a593Smuzhiyun .get = snd_sb16_dma_control_get,
721*4882a593Smuzhiyun .put = snd_sb16_dma_control_put
722*4882a593Smuzhiyun };
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun /*
725*4882a593Smuzhiyun * Initialization part
726*4882a593Smuzhiyun */
727*4882a593Smuzhiyun
snd_sb16dsp_configure(struct snd_sb * chip)728*4882a593Smuzhiyun int snd_sb16dsp_configure(struct snd_sb * chip)
729*4882a593Smuzhiyun {
730*4882a593Smuzhiyun unsigned long flags;
731*4882a593Smuzhiyun unsigned char irqreg = 0, dmareg = 0, mpureg;
732*4882a593Smuzhiyun unsigned char realirq, realdma, realmpureg;
733*4882a593Smuzhiyun /* note: mpu register should be present only on SB16 Vibra soundcards */
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun // printk(KERN_DEBUG "codec->irq=%i, codec->dma8=%i, codec->dma16=%i\n", chip->irq, chip->dma8, chip->dma16);
736*4882a593Smuzhiyun spin_lock_irqsave(&chip->mixer_lock, flags);
737*4882a593Smuzhiyun mpureg = snd_sbmixer_read(chip, SB_DSP4_MPUSETUP) & ~0x06;
738*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->mixer_lock, flags);
739*4882a593Smuzhiyun switch (chip->irq) {
740*4882a593Smuzhiyun case 2:
741*4882a593Smuzhiyun case 9:
742*4882a593Smuzhiyun irqreg |= SB_IRQSETUP_IRQ9;
743*4882a593Smuzhiyun break;
744*4882a593Smuzhiyun case 5:
745*4882a593Smuzhiyun irqreg |= SB_IRQSETUP_IRQ5;
746*4882a593Smuzhiyun break;
747*4882a593Smuzhiyun case 7:
748*4882a593Smuzhiyun irqreg |= SB_IRQSETUP_IRQ7;
749*4882a593Smuzhiyun break;
750*4882a593Smuzhiyun case 10:
751*4882a593Smuzhiyun irqreg |= SB_IRQSETUP_IRQ10;
752*4882a593Smuzhiyun break;
753*4882a593Smuzhiyun default:
754*4882a593Smuzhiyun return -EINVAL;
755*4882a593Smuzhiyun }
756*4882a593Smuzhiyun if (chip->dma8 >= 0) {
757*4882a593Smuzhiyun switch (chip->dma8) {
758*4882a593Smuzhiyun case 0:
759*4882a593Smuzhiyun dmareg |= SB_DMASETUP_DMA0;
760*4882a593Smuzhiyun break;
761*4882a593Smuzhiyun case 1:
762*4882a593Smuzhiyun dmareg |= SB_DMASETUP_DMA1;
763*4882a593Smuzhiyun break;
764*4882a593Smuzhiyun case 3:
765*4882a593Smuzhiyun dmareg |= SB_DMASETUP_DMA3;
766*4882a593Smuzhiyun break;
767*4882a593Smuzhiyun default:
768*4882a593Smuzhiyun return -EINVAL;
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun if (chip->dma16 >= 0 && chip->dma16 != chip->dma8) {
772*4882a593Smuzhiyun switch (chip->dma16) {
773*4882a593Smuzhiyun case 5:
774*4882a593Smuzhiyun dmareg |= SB_DMASETUP_DMA5;
775*4882a593Smuzhiyun break;
776*4882a593Smuzhiyun case 6:
777*4882a593Smuzhiyun dmareg |= SB_DMASETUP_DMA6;
778*4882a593Smuzhiyun break;
779*4882a593Smuzhiyun case 7:
780*4882a593Smuzhiyun dmareg |= SB_DMASETUP_DMA7;
781*4882a593Smuzhiyun break;
782*4882a593Smuzhiyun default:
783*4882a593Smuzhiyun return -EINVAL;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun switch (chip->mpu_port) {
787*4882a593Smuzhiyun case 0x300:
788*4882a593Smuzhiyun mpureg |= 0x04;
789*4882a593Smuzhiyun break;
790*4882a593Smuzhiyun case 0x330:
791*4882a593Smuzhiyun mpureg |= 0x00;
792*4882a593Smuzhiyun break;
793*4882a593Smuzhiyun default:
794*4882a593Smuzhiyun mpureg |= 0x02; /* disable MPU */
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun spin_lock_irqsave(&chip->mixer_lock, flags);
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun snd_sbmixer_write(chip, SB_DSP4_IRQSETUP, irqreg);
799*4882a593Smuzhiyun realirq = snd_sbmixer_read(chip, SB_DSP4_IRQSETUP);
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun snd_sbmixer_write(chip, SB_DSP4_DMASETUP, dmareg);
802*4882a593Smuzhiyun realdma = snd_sbmixer_read(chip, SB_DSP4_DMASETUP);
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun snd_sbmixer_write(chip, SB_DSP4_MPUSETUP, mpureg);
805*4882a593Smuzhiyun realmpureg = snd_sbmixer_read(chip, SB_DSP4_MPUSETUP);
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun spin_unlock_irqrestore(&chip->mixer_lock, flags);
808*4882a593Smuzhiyun if ((~realirq) & irqreg || (~realdma) & dmareg) {
809*4882a593Smuzhiyun snd_printk(KERN_ERR "SB16 [0x%lx]: unable to set DMA & IRQ (PnP device?)\n", chip->port);
810*4882a593Smuzhiyun snd_printk(KERN_ERR "SB16 [0x%lx]: wanted: irqreg=0x%x, dmareg=0x%x, mpureg = 0x%x\n", chip->port, realirq, realdma, realmpureg);
811*4882a593Smuzhiyun snd_printk(KERN_ERR "SB16 [0x%lx]: got: irqreg=0x%x, dmareg=0x%x, mpureg = 0x%x\n", chip->port, irqreg, dmareg, mpureg);
812*4882a593Smuzhiyun return -ENODEV;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun return 0;
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun static const struct snd_pcm_ops snd_sb16_playback_ops = {
818*4882a593Smuzhiyun .open = snd_sb16_playback_open,
819*4882a593Smuzhiyun .close = snd_sb16_playback_close,
820*4882a593Smuzhiyun .prepare = snd_sb16_playback_prepare,
821*4882a593Smuzhiyun .trigger = snd_sb16_playback_trigger,
822*4882a593Smuzhiyun .pointer = snd_sb16_playback_pointer,
823*4882a593Smuzhiyun };
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun static const struct snd_pcm_ops snd_sb16_capture_ops = {
826*4882a593Smuzhiyun .open = snd_sb16_capture_open,
827*4882a593Smuzhiyun .close = snd_sb16_capture_close,
828*4882a593Smuzhiyun .prepare = snd_sb16_capture_prepare,
829*4882a593Smuzhiyun .trigger = snd_sb16_capture_trigger,
830*4882a593Smuzhiyun .pointer = snd_sb16_capture_pointer,
831*4882a593Smuzhiyun };
832*4882a593Smuzhiyun
snd_sb16dsp_pcm(struct snd_sb * chip,int device)833*4882a593Smuzhiyun int snd_sb16dsp_pcm(struct snd_sb *chip, int device)
834*4882a593Smuzhiyun {
835*4882a593Smuzhiyun struct snd_card *card = chip->card;
836*4882a593Smuzhiyun struct snd_pcm *pcm;
837*4882a593Smuzhiyun int err;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun if ((err = snd_pcm_new(card, "SB16 DSP", device, 1, 1, &pcm)) < 0)
840*4882a593Smuzhiyun return err;
841*4882a593Smuzhiyun sprintf(pcm->name, "DSP v%i.%i", chip->version >> 8, chip->version & 0xff);
842*4882a593Smuzhiyun pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
843*4882a593Smuzhiyun pcm->private_data = chip;
844*4882a593Smuzhiyun chip->pcm = pcm;
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_sb16_playback_ops);
847*4882a593Smuzhiyun snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_sb16_capture_ops);
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun if (chip->dma16 >= 0 && chip->dma8 != chip->dma16)
850*4882a593Smuzhiyun snd_ctl_add(card, snd_ctl_new1(&snd_sb16_dma_control, chip));
851*4882a593Smuzhiyun else
852*4882a593Smuzhiyun pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
855*4882a593Smuzhiyun card->dev, 64*1024, 128*1024);
856*4882a593Smuzhiyun return 0;
857*4882a593Smuzhiyun }
858*4882a593Smuzhiyun
snd_sb16dsp_get_pcm_ops(int direction)859*4882a593Smuzhiyun const struct snd_pcm_ops *snd_sb16dsp_get_pcm_ops(int direction)
860*4882a593Smuzhiyun {
861*4882a593Smuzhiyun return direction == SNDRV_PCM_STREAM_PLAYBACK ?
862*4882a593Smuzhiyun &snd_sb16_playback_ops : &snd_sb16_capture_ops;
863*4882a593Smuzhiyun }
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun EXPORT_SYMBOL(snd_sb16dsp_pcm);
866*4882a593Smuzhiyun EXPORT_SYMBOL(snd_sb16dsp_get_pcm_ops);
867*4882a593Smuzhiyun EXPORT_SYMBOL(snd_sb16dsp_configure);
868*4882a593Smuzhiyun EXPORT_SYMBOL(snd_sb16dsp_interrupt);
869