1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /********************************************************************* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * msnd.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Turtle Beach MultiSound Sound Card Driver for Linux 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Some parts of this header file were derived from the Turtle Beach 9*4882a593Smuzhiyun * MultiSound Driver Development Kit. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Copyright (C) 1998 Andrew Veliath 12*4882a593Smuzhiyun * Copyright (C) 1993 Turtle Beach Systems, Inc. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun ********************************************************************/ 15*4882a593Smuzhiyun #ifndef __MSND_H 16*4882a593Smuzhiyun #define __MSND_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define DEFSAMPLERATE 44100 19*4882a593Smuzhiyun #define DEFSAMPLESIZE SNDRV_PCM_FORMAT_S16 20*4882a593Smuzhiyun #define DEFCHANNELS 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define SRAM_BANK_SIZE 0x8000 23*4882a593Smuzhiyun #define SRAM_CNTL_START 0x7F00 24*4882a593Smuzhiyun #define SMA_STRUCT_START 0x7F40 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define DSP_BASE_ADDR 0x4000 27*4882a593Smuzhiyun #define DSP_BANK_BASE 0x4000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define AGND 0x01 30*4882a593Smuzhiyun #define SIGNAL 0x02 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define EXT_DSP_BIT_DCAL 0x0001 33*4882a593Smuzhiyun #define EXT_DSP_BIT_MIDI_CON 0x0002 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define BUFFSIZE 0x8000 36*4882a593Smuzhiyun #define HOSTQ_SIZE 0x40 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define DAP_BUFF_SIZE 0x2400 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define DAPQ_STRUCT_SIZE 0x10 41*4882a593Smuzhiyun #define DARQ_STRUCT_SIZE 0x10 42*4882a593Smuzhiyun #define DAPQ_BUFF_SIZE (3 * 0x10) 43*4882a593Smuzhiyun #define DARQ_BUFF_SIZE (3 * 0x10) 44*4882a593Smuzhiyun #define MODQ_BUFF_SIZE 0x400 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define DAPQ_DATA_BUFF 0x6C00 47*4882a593Smuzhiyun #define DARQ_DATA_BUFF 0x6C30 48*4882a593Smuzhiyun #define MODQ_DATA_BUFF 0x6C60 49*4882a593Smuzhiyun #define MIDQ_DATA_BUFF 0x7060 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define DAPQ_OFFSET SRAM_CNTL_START 52*4882a593Smuzhiyun #define DARQ_OFFSET (SRAM_CNTL_START + 0x08) 53*4882a593Smuzhiyun #define MODQ_OFFSET (SRAM_CNTL_START + 0x10) 54*4882a593Smuzhiyun #define MIDQ_OFFSET (SRAM_CNTL_START + 0x18) 55*4882a593Smuzhiyun #define DSPQ_OFFSET (SRAM_CNTL_START + 0x20) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define HP_ICR 0x00 58*4882a593Smuzhiyun #define HP_CVR 0x01 59*4882a593Smuzhiyun #define HP_ISR 0x02 60*4882a593Smuzhiyun #define HP_IVR 0x03 61*4882a593Smuzhiyun #define HP_NU 0x04 62*4882a593Smuzhiyun #define HP_INFO 0x04 63*4882a593Smuzhiyun #define HP_TXH 0x05 64*4882a593Smuzhiyun #define HP_RXH 0x05 65*4882a593Smuzhiyun #define HP_TXM 0x06 66*4882a593Smuzhiyun #define HP_RXM 0x06 67*4882a593Smuzhiyun #define HP_TXL 0x07 68*4882a593Smuzhiyun #define HP_RXL 0x07 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define HP_ICR_DEF 0x00 71*4882a593Smuzhiyun #define HP_CVR_DEF 0x12 72*4882a593Smuzhiyun #define HP_ISR_DEF 0x06 73*4882a593Smuzhiyun #define HP_IVR_DEF 0x0f 74*4882a593Smuzhiyun #define HP_NU_DEF 0x00 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define HP_IRQM 0x09 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define HPR_BLRC 0x08 79*4882a593Smuzhiyun #define HPR_SPR1 0x09 80*4882a593Smuzhiyun #define HPR_SPR2 0x0A 81*4882a593Smuzhiyun #define HPR_TCL0 0x0B 82*4882a593Smuzhiyun #define HPR_TCL1 0x0C 83*4882a593Smuzhiyun #define HPR_TCL2 0x0D 84*4882a593Smuzhiyun #define HPR_TCL3 0x0E 85*4882a593Smuzhiyun #define HPR_TCL4 0x0F 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define HPICR_INIT 0x80 88*4882a593Smuzhiyun #define HPICR_HM1 0x40 89*4882a593Smuzhiyun #define HPICR_HM0 0x20 90*4882a593Smuzhiyun #define HPICR_HF1 0x10 91*4882a593Smuzhiyun #define HPICR_HF0 0x08 92*4882a593Smuzhiyun #define HPICR_TREQ 0x02 93*4882a593Smuzhiyun #define HPICR_RREQ 0x01 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define HPCVR_HC 0x80 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define HPISR_HREQ 0x80 98*4882a593Smuzhiyun #define HPISR_DMA 0x40 99*4882a593Smuzhiyun #define HPISR_HF3 0x10 100*4882a593Smuzhiyun #define HPISR_HF2 0x08 101*4882a593Smuzhiyun #define HPISR_TRDY 0x04 102*4882a593Smuzhiyun #define HPISR_TXDE 0x02 103*4882a593Smuzhiyun #define HPISR_RXDF 0x01 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define HPIO_290 0 106*4882a593Smuzhiyun #define HPIO_260 1 107*4882a593Smuzhiyun #define HPIO_250 2 108*4882a593Smuzhiyun #define HPIO_240 3 109*4882a593Smuzhiyun #define HPIO_230 4 110*4882a593Smuzhiyun #define HPIO_220 5 111*4882a593Smuzhiyun #define HPIO_210 6 112*4882a593Smuzhiyun #define HPIO_3E0 7 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define HPMEM_NONE 0 115*4882a593Smuzhiyun #define HPMEM_B000 1 116*4882a593Smuzhiyun #define HPMEM_C800 2 117*4882a593Smuzhiyun #define HPMEM_D000 3 118*4882a593Smuzhiyun #define HPMEM_D400 4 119*4882a593Smuzhiyun #define HPMEM_D800 5 120*4882a593Smuzhiyun #define HPMEM_E000 6 121*4882a593Smuzhiyun #define HPMEM_E800 7 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define HPIRQ_NONE 0 124*4882a593Smuzhiyun #define HPIRQ_5 1 125*4882a593Smuzhiyun #define HPIRQ_7 2 126*4882a593Smuzhiyun #define HPIRQ_9 3 127*4882a593Smuzhiyun #define HPIRQ_10 4 128*4882a593Smuzhiyun #define HPIRQ_11 5 129*4882a593Smuzhiyun #define HPIRQ_12 6 130*4882a593Smuzhiyun #define HPIRQ_15 7 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define HIMT_PLAY_DONE 0x00 133*4882a593Smuzhiyun #define HIMT_RECORD_DONE 0x01 134*4882a593Smuzhiyun #define HIMT_MIDI_EOS 0x02 135*4882a593Smuzhiyun #define HIMT_MIDI_OUT 0x03 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define HIMT_MIDI_IN_UCHAR 0x0E 138*4882a593Smuzhiyun #define HIMT_DSP 0x0F 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define HDEX_BASE 0x92 141*4882a593Smuzhiyun #define HDEX_PLAY_START (0 + HDEX_BASE) 142*4882a593Smuzhiyun #define HDEX_PLAY_STOP (1 + HDEX_BASE) 143*4882a593Smuzhiyun #define HDEX_PLAY_PAUSE (2 + HDEX_BASE) 144*4882a593Smuzhiyun #define HDEX_PLAY_RESUME (3 + HDEX_BASE) 145*4882a593Smuzhiyun #define HDEX_RECORD_START (4 + HDEX_BASE) 146*4882a593Smuzhiyun #define HDEX_RECORD_STOP (5 + HDEX_BASE) 147*4882a593Smuzhiyun #define HDEX_MIDI_IN_START (6 + HDEX_BASE) 148*4882a593Smuzhiyun #define HDEX_MIDI_IN_STOP (7 + HDEX_BASE) 149*4882a593Smuzhiyun #define HDEX_MIDI_OUT_START (8 + HDEX_BASE) 150*4882a593Smuzhiyun #define HDEX_MIDI_OUT_STOP (9 + HDEX_BASE) 151*4882a593Smuzhiyun #define HDEX_AUX_REQ (10 + HDEX_BASE) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define HDEXAR_CLEAR_PEAKS 1 154*4882a593Smuzhiyun #define HDEXAR_IN_SET_POTS 2 155*4882a593Smuzhiyun #define HDEXAR_AUX_SET_POTS 3 156*4882a593Smuzhiyun #define HDEXAR_CAL_A_TO_D 4 157*4882a593Smuzhiyun #define HDEXAR_RD_EXT_DSP_BITS 5 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* Pinnacle only HDEXAR defs */ 160*4882a593Smuzhiyun #define HDEXAR_SET_ANA_IN 0 161*4882a593Smuzhiyun #define HDEXAR_SET_SYNTH_IN 4 162*4882a593Smuzhiyun #define HDEXAR_READ_DAT_IN 5 163*4882a593Smuzhiyun #define HDEXAR_MIC_SET_POTS 6 164*4882a593Smuzhiyun #define HDEXAR_SET_DAT_IN 7 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define HDEXAR_SET_SYNTH_48 8 167*4882a593Smuzhiyun #define HDEXAR_SET_SYNTH_44 9 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define HIWORD(l) ((u16)((((u32)(l)) >> 16) & 0xFFFF)) 170*4882a593Smuzhiyun #define LOWORD(l) ((u16)(u32)(l)) 171*4882a593Smuzhiyun #define HIBYTE(w) ((u8)(((u16)(w) >> 8) & 0xFF)) 172*4882a593Smuzhiyun #define LOBYTE(w) ((u8)(w)) 173*4882a593Smuzhiyun #define MAKELONG(low, hi) ((long)(((u16)(low))|(((u32)((u16)(hi)))<<16))) 174*4882a593Smuzhiyun #define MAKEWORD(low, hi) ((u16)(((u8)(low))|(((u16)((u8)(hi)))<<8))) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define PCTODSP_OFFSET(w) (u16)((w)/2) 177*4882a593Smuzhiyun #define PCTODSP_BASED(w) (u16)(((w)/2) + DSP_BASE_ADDR) 178*4882a593Smuzhiyun #define DSPTOPC_BASED(w) (((w) - DSP_BASE_ADDR) * 2) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #ifdef SLOWIO 181*4882a593Smuzhiyun # undef outb 182*4882a593Smuzhiyun # undef inb 183*4882a593Smuzhiyun # define outb outb_p 184*4882a593Smuzhiyun # define inb inb_p 185*4882a593Smuzhiyun #endif 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* JobQueueStruct */ 188*4882a593Smuzhiyun #define JQS_wStart 0x00 189*4882a593Smuzhiyun #define JQS_wSize 0x02 190*4882a593Smuzhiyun #define JQS_wHead 0x04 191*4882a593Smuzhiyun #define JQS_wTail 0x06 192*4882a593Smuzhiyun #define JQS__size 0x08 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* DAQueueDataStruct */ 195*4882a593Smuzhiyun #define DAQDS_wStart 0x00 196*4882a593Smuzhiyun #define DAQDS_wSize 0x02 197*4882a593Smuzhiyun #define DAQDS_wFormat 0x04 198*4882a593Smuzhiyun #define DAQDS_wSampleSize 0x06 199*4882a593Smuzhiyun #define DAQDS_wChannels 0x08 200*4882a593Smuzhiyun #define DAQDS_wSampleRate 0x0A 201*4882a593Smuzhiyun #define DAQDS_wIntMsg 0x0C 202*4882a593Smuzhiyun #define DAQDS_wFlags 0x0E 203*4882a593Smuzhiyun #define DAQDS__size 0x10 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #include <sound/pcm.h> 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun struct snd_msnd { 208*4882a593Smuzhiyun void __iomem *mappedbase; 209*4882a593Smuzhiyun int play_period_bytes; 210*4882a593Smuzhiyun int playLimit; 211*4882a593Smuzhiyun int playPeriods; 212*4882a593Smuzhiyun int playDMAPos; 213*4882a593Smuzhiyun int banksPlayed; 214*4882a593Smuzhiyun int captureDMAPos; 215*4882a593Smuzhiyun int capturePeriodBytes; 216*4882a593Smuzhiyun int captureLimit; 217*4882a593Smuzhiyun int capturePeriods; 218*4882a593Smuzhiyun struct snd_card *card; 219*4882a593Smuzhiyun void *msndmidi_mpu; 220*4882a593Smuzhiyun struct snd_rawmidi *rmidi; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* Hardware resources */ 223*4882a593Smuzhiyun long io; 224*4882a593Smuzhiyun int memid, irqid; 225*4882a593Smuzhiyun int irq, irq_ref; 226*4882a593Smuzhiyun unsigned long base; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* Motorola 56k DSP SMA */ 229*4882a593Smuzhiyun void __iomem *SMA; 230*4882a593Smuzhiyun void __iomem *DAPQ; 231*4882a593Smuzhiyun void __iomem *DARQ; 232*4882a593Smuzhiyun void __iomem *MODQ; 233*4882a593Smuzhiyun void __iomem *MIDQ; 234*4882a593Smuzhiyun void __iomem *DSPQ; 235*4882a593Smuzhiyun int dspq_data_buff, dspq_buff_size; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* State variables */ 238*4882a593Smuzhiyun enum { msndClassic, msndPinnacle } type; 239*4882a593Smuzhiyun fmode_t mode; 240*4882a593Smuzhiyun unsigned long flags; 241*4882a593Smuzhiyun #define F_RESETTING 0 242*4882a593Smuzhiyun #define F_HAVEDIGITAL 1 243*4882a593Smuzhiyun #define F_AUDIO_WRITE_INUSE 2 244*4882a593Smuzhiyun #define F_WRITING 3 245*4882a593Smuzhiyun #define F_WRITEBLOCK 4 246*4882a593Smuzhiyun #define F_WRITEFLUSH 5 247*4882a593Smuzhiyun #define F_AUDIO_READ_INUSE 6 248*4882a593Smuzhiyun #define F_READING 7 249*4882a593Smuzhiyun #define F_READBLOCK 8 250*4882a593Smuzhiyun #define F_EXT_MIDI_INUSE 9 251*4882a593Smuzhiyun #define F_HDR_MIDI_INUSE 10 252*4882a593Smuzhiyun #define F_DISABLE_WRITE_NDELAY 11 253*4882a593Smuzhiyun spinlock_t lock; 254*4882a593Smuzhiyun spinlock_t mixer_lock; 255*4882a593Smuzhiyun int nresets; 256*4882a593Smuzhiyun unsigned recsrc; 257*4882a593Smuzhiyun #define LEVEL_ENTRIES 32 258*4882a593Smuzhiyun int left_levels[LEVEL_ENTRIES]; 259*4882a593Smuzhiyun int right_levels[LEVEL_ENTRIES]; 260*4882a593Smuzhiyun int calibrate_signal; 261*4882a593Smuzhiyun int play_sample_size, play_sample_rate, play_channels; 262*4882a593Smuzhiyun int play_ndelay; 263*4882a593Smuzhiyun int capture_sample_size, capture_sample_rate, capture_channels; 264*4882a593Smuzhiyun int capture_ndelay; 265*4882a593Smuzhiyun u8 bCurrentMidiPatch; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun int last_playbank, last_recbank; 268*4882a593Smuzhiyun struct snd_pcm_substream *playback_substream; 269*4882a593Smuzhiyun struct snd_pcm_substream *capture_substream; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun void snd_msnd_init_queue(void __iomem *base, int start, int size); 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun int snd_msnd_send_dsp_cmd(struct snd_msnd *chip, u8 cmd); 276*4882a593Smuzhiyun int snd_msnd_send_word(struct snd_msnd *chip, 277*4882a593Smuzhiyun unsigned char high, 278*4882a593Smuzhiyun unsigned char mid, 279*4882a593Smuzhiyun unsigned char low); 280*4882a593Smuzhiyun int snd_msnd_upload_host(struct snd_msnd *chip, 281*4882a593Smuzhiyun const u8 *bin, int len); 282*4882a593Smuzhiyun int snd_msnd_enable_irq(struct snd_msnd *chip); 283*4882a593Smuzhiyun int snd_msnd_disable_irq(struct snd_msnd *chip); 284*4882a593Smuzhiyun void snd_msnd_dsp_halt(struct snd_msnd *chip, struct file *file); 285*4882a593Smuzhiyun int snd_msnd_DAPQ(struct snd_msnd *chip, int start); 286*4882a593Smuzhiyun int snd_msnd_DARQ(struct snd_msnd *chip, int start); 287*4882a593Smuzhiyun int snd_msnd_pcm(struct snd_card *card, int device); 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun int snd_msndmidi_new(struct snd_card *card, int device); 290*4882a593Smuzhiyun void snd_msndmidi_input_read(void *mpu); 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun void snd_msndmix_setup(struct snd_msnd *chip); 293*4882a593Smuzhiyun int snd_msndmix_new(struct snd_card *card); 294*4882a593Smuzhiyun int snd_msndmix_force_recsrc(struct snd_msnd *chip, int recsrc); 295*4882a593Smuzhiyun #endif /* __MSND_H */ 296