xref: /OK3568_Linux_fs/kernel/sound/isa/gus/gus_io.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4*4882a593Smuzhiyun  *  I/O routines for GF1/InterWave synthesizer chips
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/time.h>
9*4882a593Smuzhiyun #include <sound/core.h>
10*4882a593Smuzhiyun #include <sound/gus.h>
11*4882a593Smuzhiyun 
snd_gf1_delay(struct snd_gus_card * gus)12*4882a593Smuzhiyun void snd_gf1_delay(struct snd_gus_card * gus)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun 	int i;
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun 	for (i = 0; i < 6; i++) {
17*4882a593Smuzhiyun 		mb();
18*4882a593Smuzhiyun 		inb(GUSP(gus, DRAM));
19*4882a593Smuzhiyun 	}
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun  *  =======================================================================
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun  *  ok.. stop of control registers (wave & ramp) need some special things..
28*4882a593Smuzhiyun  *       big UltraClick (tm) elimination...
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun 
__snd_gf1_ctrl_stop(struct snd_gus_card * gus,unsigned char reg)31*4882a593Smuzhiyun static inline void __snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun 	unsigned char value;
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	outb(reg | 0x80, gus->gf1.reg_regsel);
36*4882a593Smuzhiyun 	mb();
37*4882a593Smuzhiyun 	value = inb(gus->gf1.reg_data8);
38*4882a593Smuzhiyun 	mb();
39*4882a593Smuzhiyun 	outb(reg, gus->gf1.reg_regsel);
40*4882a593Smuzhiyun 	mb();
41*4882a593Smuzhiyun 	outb((value | 0x03) & ~(0x80 | 0x20), gus->gf1.reg_data8);
42*4882a593Smuzhiyun 	mb();
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
__snd_gf1_write8(struct snd_gus_card * gus,unsigned char reg,unsigned char data)45*4882a593Smuzhiyun static inline void __snd_gf1_write8(struct snd_gus_card * gus,
46*4882a593Smuzhiyun 				    unsigned char reg,
47*4882a593Smuzhiyun 				    unsigned char data)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	outb(reg, gus->gf1.reg_regsel);
50*4882a593Smuzhiyun 	mb();
51*4882a593Smuzhiyun 	outb(data, gus->gf1.reg_data8);
52*4882a593Smuzhiyun 	mb();
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
__snd_gf1_look8(struct snd_gus_card * gus,unsigned char reg)55*4882a593Smuzhiyun static inline unsigned char __snd_gf1_look8(struct snd_gus_card * gus,
56*4882a593Smuzhiyun 					    unsigned char reg)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	outb(reg, gus->gf1.reg_regsel);
59*4882a593Smuzhiyun 	mb();
60*4882a593Smuzhiyun 	return inb(gus->gf1.reg_data8);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
__snd_gf1_write16(struct snd_gus_card * gus,unsigned char reg,unsigned int data)63*4882a593Smuzhiyun static inline void __snd_gf1_write16(struct snd_gus_card * gus,
64*4882a593Smuzhiyun 				     unsigned char reg, unsigned int data)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	outb(reg, gus->gf1.reg_regsel);
67*4882a593Smuzhiyun 	mb();
68*4882a593Smuzhiyun 	outw((unsigned short) data, gus->gf1.reg_data16);
69*4882a593Smuzhiyun 	mb();
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun 
__snd_gf1_look16(struct snd_gus_card * gus,unsigned char reg)72*4882a593Smuzhiyun static inline unsigned short __snd_gf1_look16(struct snd_gus_card * gus,
73*4882a593Smuzhiyun 					      unsigned char reg)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	outb(reg, gus->gf1.reg_regsel);
76*4882a593Smuzhiyun 	mb();
77*4882a593Smuzhiyun 	return inw(gus->gf1.reg_data16);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun 
__snd_gf1_adlib_write(struct snd_gus_card * gus,unsigned char reg,unsigned char data)80*4882a593Smuzhiyun static inline void __snd_gf1_adlib_write(struct snd_gus_card * gus,
81*4882a593Smuzhiyun 					 unsigned char reg, unsigned char data)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	outb(reg, gus->gf1.reg_timerctrl);
84*4882a593Smuzhiyun 	inb(gus->gf1.reg_timerctrl);
85*4882a593Smuzhiyun 	inb(gus->gf1.reg_timerctrl);
86*4882a593Smuzhiyun 	outb(data, gus->gf1.reg_timerdata);
87*4882a593Smuzhiyun 	inb(gus->gf1.reg_timerctrl);
88*4882a593Smuzhiyun 	inb(gus->gf1.reg_timerctrl);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
__snd_gf1_write_addr(struct snd_gus_card * gus,unsigned char reg,unsigned int addr,int w_16bit)91*4882a593Smuzhiyun static inline void __snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg,
92*4882a593Smuzhiyun                                         unsigned int addr, int w_16bit)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	if (gus->gf1.enh_mode) {
95*4882a593Smuzhiyun 		if (w_16bit)
96*4882a593Smuzhiyun 			addr = ((addr >> 1) & ~0x0000000f) | (addr & 0x0000000f);
97*4882a593Smuzhiyun 		__snd_gf1_write8(gus, SNDRV_GF1_VB_UPPER_ADDRESS, (unsigned char) ((addr >> 26) & 0x03));
98*4882a593Smuzhiyun 	} else if (w_16bit)
99*4882a593Smuzhiyun 		addr = (addr & 0x00c0000f) | ((addr & 0x003ffff0) >> 1);
100*4882a593Smuzhiyun 	__snd_gf1_write16(gus, reg, (unsigned short) (addr >> 11));
101*4882a593Smuzhiyun 	__snd_gf1_write16(gus, reg + 1, (unsigned short) (addr << 5));
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
__snd_gf1_read_addr(struct snd_gus_card * gus,unsigned char reg,short w_16bit)104*4882a593Smuzhiyun static inline unsigned int __snd_gf1_read_addr(struct snd_gus_card * gus,
105*4882a593Smuzhiyun 					       unsigned char reg, short w_16bit)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	unsigned int res;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	res = ((unsigned int) __snd_gf1_look16(gus, reg | 0x80) << 11) & 0xfff800;
110*4882a593Smuzhiyun 	res |= ((unsigned int) __snd_gf1_look16(gus, (reg + 1) | 0x80) >> 5) & 0x0007ff;
111*4882a593Smuzhiyun 	if (gus->gf1.enh_mode) {
112*4882a593Smuzhiyun 		res |= (unsigned int) __snd_gf1_look8(gus, SNDRV_GF1_VB_UPPER_ADDRESS | 0x80) << 26;
113*4882a593Smuzhiyun 		if (w_16bit)
114*4882a593Smuzhiyun 			res = ((res << 1) & 0xffffffe0) | (res & 0x0000000f);
115*4882a593Smuzhiyun 	} else if (w_16bit)
116*4882a593Smuzhiyun 		res = ((res & 0x001ffff0) << 1) | (res & 0x00c0000f);
117*4882a593Smuzhiyun 	return res;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /*
122*4882a593Smuzhiyun  *  =======================================================================
123*4882a593Smuzhiyun  */
124*4882a593Smuzhiyun 
snd_gf1_ctrl_stop(struct snd_gus_card * gus,unsigned char reg)125*4882a593Smuzhiyun void snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	__snd_gf1_ctrl_stop(gus, reg);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun 
snd_gf1_write8(struct snd_gus_card * gus,unsigned char reg,unsigned char data)130*4882a593Smuzhiyun void snd_gf1_write8(struct snd_gus_card * gus,
131*4882a593Smuzhiyun 		    unsigned char reg,
132*4882a593Smuzhiyun 		    unsigned char data)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	__snd_gf1_write8(gus, reg, data);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
snd_gf1_look8(struct snd_gus_card * gus,unsigned char reg)137*4882a593Smuzhiyun unsigned char snd_gf1_look8(struct snd_gus_card * gus, unsigned char reg)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	return __snd_gf1_look8(gus, reg);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
snd_gf1_write16(struct snd_gus_card * gus,unsigned char reg,unsigned int data)142*4882a593Smuzhiyun void snd_gf1_write16(struct snd_gus_card * gus,
143*4882a593Smuzhiyun 		     unsigned char reg,
144*4882a593Smuzhiyun 		     unsigned int data)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	__snd_gf1_write16(gus, reg, data);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
snd_gf1_look16(struct snd_gus_card * gus,unsigned char reg)149*4882a593Smuzhiyun unsigned short snd_gf1_look16(struct snd_gus_card * gus, unsigned char reg)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	return __snd_gf1_look16(gus, reg);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
snd_gf1_adlib_write(struct snd_gus_card * gus,unsigned char reg,unsigned char data)154*4882a593Smuzhiyun void snd_gf1_adlib_write(struct snd_gus_card * gus,
155*4882a593Smuzhiyun                          unsigned char reg,
156*4882a593Smuzhiyun                          unsigned char data)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	__snd_gf1_adlib_write(gus, reg, data);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
snd_gf1_write_addr(struct snd_gus_card * gus,unsigned char reg,unsigned int addr,short w_16bit)161*4882a593Smuzhiyun void snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg,
162*4882a593Smuzhiyun                         unsigned int addr, short w_16bit)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	__snd_gf1_write_addr(gus, reg, addr, w_16bit);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
snd_gf1_read_addr(struct snd_gus_card * gus,unsigned char reg,short w_16bit)167*4882a593Smuzhiyun unsigned int snd_gf1_read_addr(struct snd_gus_card * gus,
168*4882a593Smuzhiyun                                unsigned char reg,
169*4882a593Smuzhiyun                                short w_16bit)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun 	return __snd_gf1_read_addr(gus, reg, w_16bit);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun /*
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun  */
177*4882a593Smuzhiyun 
snd_gf1_i_ctrl_stop(struct snd_gus_card * gus,unsigned char reg)178*4882a593Smuzhiyun void snd_gf1_i_ctrl_stop(struct snd_gus_card * gus, unsigned char reg)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	unsigned long flags;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
183*4882a593Smuzhiyun 	__snd_gf1_ctrl_stop(gus, reg);
184*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
snd_gf1_i_write8(struct snd_gus_card * gus,unsigned char reg,unsigned char data)187*4882a593Smuzhiyun void snd_gf1_i_write8(struct snd_gus_card * gus,
188*4882a593Smuzhiyun 		      unsigned char reg,
189*4882a593Smuzhiyun                       unsigned char data)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	unsigned long flags;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
194*4882a593Smuzhiyun 	__snd_gf1_write8(gus, reg, data);
195*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
snd_gf1_i_look8(struct snd_gus_card * gus,unsigned char reg)198*4882a593Smuzhiyun unsigned char snd_gf1_i_look8(struct snd_gus_card * gus, unsigned char reg)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	unsigned long flags;
201*4882a593Smuzhiyun 	unsigned char res;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
204*4882a593Smuzhiyun 	res = __snd_gf1_look8(gus, reg);
205*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
206*4882a593Smuzhiyun 	return res;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
snd_gf1_i_write16(struct snd_gus_card * gus,unsigned char reg,unsigned int data)209*4882a593Smuzhiyun void snd_gf1_i_write16(struct snd_gus_card * gus,
210*4882a593Smuzhiyun 		       unsigned char reg,
211*4882a593Smuzhiyun 		       unsigned int data)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	unsigned long flags;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
216*4882a593Smuzhiyun 	__snd_gf1_write16(gus, reg, data);
217*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
snd_gf1_i_look16(struct snd_gus_card * gus,unsigned char reg)220*4882a593Smuzhiyun unsigned short snd_gf1_i_look16(struct snd_gus_card * gus, unsigned char reg)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	unsigned long flags;
223*4882a593Smuzhiyun 	unsigned short res;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
226*4882a593Smuzhiyun 	res = __snd_gf1_look16(gus, reg);
227*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
228*4882a593Smuzhiyun 	return res;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun #if 0
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun void snd_gf1_i_adlib_write(struct snd_gus_card * gus,
234*4882a593Smuzhiyun 		           unsigned char reg,
235*4882a593Smuzhiyun 		           unsigned char data)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	unsigned long flags;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
240*4882a593Smuzhiyun 	__snd_gf1_adlib_write(gus, reg, data);
241*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun void snd_gf1_i_write_addr(struct snd_gus_card * gus, unsigned char reg,
245*4882a593Smuzhiyun 			  unsigned int addr, short w_16bit)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun 	unsigned long flags;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
250*4882a593Smuzhiyun 	__snd_gf1_write_addr(gus, reg, addr, w_16bit);
251*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun #endif  /*  0  */
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun #ifdef CONFIG_SND_DEBUG
snd_gf1_i_read_addr(struct snd_gus_card * gus,unsigned char reg,short w_16bit)257*4882a593Smuzhiyun static unsigned int snd_gf1_i_read_addr(struct snd_gus_card * gus,
258*4882a593Smuzhiyun 					unsigned char reg, short w_16bit)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	unsigned int res;
261*4882a593Smuzhiyun 	unsigned long flags;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
264*4882a593Smuzhiyun 	res = __snd_gf1_read_addr(gus, reg, w_16bit);
265*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
266*4882a593Smuzhiyun 	return res;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun #endif
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun /*
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun  */
273*4882a593Smuzhiyun 
snd_gf1_dram_addr(struct snd_gus_card * gus,unsigned int addr)274*4882a593Smuzhiyun void snd_gf1_dram_addr(struct snd_gus_card * gus, unsigned int addr)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun 	outb(0x43, gus->gf1.reg_regsel);
277*4882a593Smuzhiyun 	mb();
278*4882a593Smuzhiyun 	outw((unsigned short) addr, gus->gf1.reg_data16);
279*4882a593Smuzhiyun 	mb();
280*4882a593Smuzhiyun 	outb(0x44, gus->gf1.reg_regsel);
281*4882a593Smuzhiyun 	mb();
282*4882a593Smuzhiyun 	outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
283*4882a593Smuzhiyun 	mb();
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun 
snd_gf1_poke(struct snd_gus_card * gus,unsigned int addr,unsigned char data)286*4882a593Smuzhiyun void snd_gf1_poke(struct snd_gus_card * gus, unsigned int addr, unsigned char data)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun 	unsigned long flags;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
291*4882a593Smuzhiyun 	outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
292*4882a593Smuzhiyun 	mb();
293*4882a593Smuzhiyun 	outw((unsigned short) addr, gus->gf1.reg_data16);
294*4882a593Smuzhiyun 	mb();
295*4882a593Smuzhiyun 	outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
296*4882a593Smuzhiyun 	mb();
297*4882a593Smuzhiyun 	outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
298*4882a593Smuzhiyun 	mb();
299*4882a593Smuzhiyun 	outb(data, gus->gf1.reg_dram);
300*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
snd_gf1_peek(struct snd_gus_card * gus,unsigned int addr)303*4882a593Smuzhiyun unsigned char snd_gf1_peek(struct snd_gus_card * gus, unsigned int addr)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun 	unsigned long flags;
306*4882a593Smuzhiyun 	unsigned char res;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
309*4882a593Smuzhiyun 	outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
310*4882a593Smuzhiyun 	mb();
311*4882a593Smuzhiyun 	outw((unsigned short) addr, gus->gf1.reg_data16);
312*4882a593Smuzhiyun 	mb();
313*4882a593Smuzhiyun 	outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
314*4882a593Smuzhiyun 	mb();
315*4882a593Smuzhiyun 	outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
316*4882a593Smuzhiyun 	mb();
317*4882a593Smuzhiyun 	res = inb(gus->gf1.reg_dram);
318*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
319*4882a593Smuzhiyun 	return res;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun #if 0
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun void snd_gf1_pokew(struct snd_gus_card * gus, unsigned int addr, unsigned short data)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	unsigned long flags;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun #ifdef CONFIG_SND_DEBUG
329*4882a593Smuzhiyun 	if (!gus->interwave)
330*4882a593Smuzhiyun 		snd_printk(KERN_DEBUG "snd_gf1_pokew - GF1!!!\n");
331*4882a593Smuzhiyun #endif
332*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
333*4882a593Smuzhiyun 	outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
334*4882a593Smuzhiyun 	mb();
335*4882a593Smuzhiyun 	outw((unsigned short) addr, gus->gf1.reg_data16);
336*4882a593Smuzhiyun 	mb();
337*4882a593Smuzhiyun 	outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
338*4882a593Smuzhiyun 	mb();
339*4882a593Smuzhiyun 	outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
340*4882a593Smuzhiyun 	mb();
341*4882a593Smuzhiyun 	outb(SNDRV_GF1_GW_DRAM_IO16, gus->gf1.reg_regsel);
342*4882a593Smuzhiyun 	mb();
343*4882a593Smuzhiyun 	outw(data, gus->gf1.reg_data16);
344*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun unsigned short snd_gf1_peekw(struct snd_gus_card * gus, unsigned int addr)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun 	unsigned long flags;
350*4882a593Smuzhiyun 	unsigned short res;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun #ifdef CONFIG_SND_DEBUG
353*4882a593Smuzhiyun 	if (!gus->interwave)
354*4882a593Smuzhiyun 		snd_printk(KERN_DEBUG "snd_gf1_peekw - GF1!!!\n");
355*4882a593Smuzhiyun #endif
356*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
357*4882a593Smuzhiyun 	outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
358*4882a593Smuzhiyun 	mb();
359*4882a593Smuzhiyun 	outw((unsigned short) addr, gus->gf1.reg_data16);
360*4882a593Smuzhiyun 	mb();
361*4882a593Smuzhiyun 	outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
362*4882a593Smuzhiyun 	mb();
363*4882a593Smuzhiyun 	outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
364*4882a593Smuzhiyun 	mb();
365*4882a593Smuzhiyun 	outb(SNDRV_GF1_GW_DRAM_IO16, gus->gf1.reg_regsel);
366*4882a593Smuzhiyun 	mb();
367*4882a593Smuzhiyun 	res = inw(gus->gf1.reg_data16);
368*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
369*4882a593Smuzhiyun 	return res;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun void snd_gf1_dram_setmem(struct snd_gus_card * gus, unsigned int addr,
373*4882a593Smuzhiyun 			 unsigned short value, unsigned int count)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun 	unsigned long port;
376*4882a593Smuzhiyun 	unsigned long flags;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun #ifdef CONFIG_SND_DEBUG
379*4882a593Smuzhiyun 	if (!gus->interwave)
380*4882a593Smuzhiyun 		snd_printk(KERN_DEBUG "snd_gf1_dram_setmem - GF1!!!\n");
381*4882a593Smuzhiyun #endif
382*4882a593Smuzhiyun 	addr &= ~1;
383*4882a593Smuzhiyun 	count >>= 1;
384*4882a593Smuzhiyun 	port = GUSP(gus, GF1DATALOW);
385*4882a593Smuzhiyun 	spin_lock_irqsave(&gus->reg_lock, flags);
386*4882a593Smuzhiyun 	outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
387*4882a593Smuzhiyun 	mb();
388*4882a593Smuzhiyun 	outw((unsigned short) addr, gus->gf1.reg_data16);
389*4882a593Smuzhiyun 	mb();
390*4882a593Smuzhiyun 	outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
391*4882a593Smuzhiyun 	mb();
392*4882a593Smuzhiyun 	outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
393*4882a593Smuzhiyun 	mb();
394*4882a593Smuzhiyun 	outb(SNDRV_GF1_GW_DRAM_IO16, gus->gf1.reg_regsel);
395*4882a593Smuzhiyun 	while (count--)
396*4882a593Smuzhiyun 		outw(value, port);
397*4882a593Smuzhiyun 	spin_unlock_irqrestore(&gus->reg_lock, flags);
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun #endif  /*  0  */
401*4882a593Smuzhiyun 
snd_gf1_select_active_voices(struct snd_gus_card * gus)402*4882a593Smuzhiyun void snd_gf1_select_active_voices(struct snd_gus_card * gus)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun 	unsigned short voices;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	static const unsigned short voices_tbl[32 - 14 + 1] =
407*4882a593Smuzhiyun 	{
408*4882a593Smuzhiyun 	    44100, 41160, 38587, 36317, 34300, 32494, 30870, 29400, 28063, 26843,
409*4882a593Smuzhiyun 	    25725, 24696, 23746, 22866, 22050, 21289, 20580, 19916, 19293
410*4882a593Smuzhiyun 	};
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	voices = gus->gf1.active_voices;
413*4882a593Smuzhiyun 	if (voices > 32)
414*4882a593Smuzhiyun 		voices = 32;
415*4882a593Smuzhiyun 	if (voices < 14)
416*4882a593Smuzhiyun 		voices = 14;
417*4882a593Smuzhiyun 	if (gus->gf1.enh_mode)
418*4882a593Smuzhiyun 		voices = 32;
419*4882a593Smuzhiyun 	gus->gf1.active_voices = voices;
420*4882a593Smuzhiyun 	gus->gf1.playback_freq =
421*4882a593Smuzhiyun 	    gus->gf1.enh_mode ? 44100 : voices_tbl[voices - 14];
422*4882a593Smuzhiyun 	if (!gus->gf1.enh_mode) {
423*4882a593Smuzhiyun 		snd_gf1_i_write8(gus, SNDRV_GF1_GB_ACTIVE_VOICES, 0xc0 | (voices - 1));
424*4882a593Smuzhiyun 		udelay(100);
425*4882a593Smuzhiyun 	}
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun #ifdef CONFIG_SND_DEBUG
429*4882a593Smuzhiyun 
snd_gf1_print_voice_registers(struct snd_gus_card * gus)430*4882a593Smuzhiyun void snd_gf1_print_voice_registers(struct snd_gus_card * gus)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun 	unsigned char mode;
433*4882a593Smuzhiyun 	int voice, ctrl;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	voice = gus->gf1.active_voice;
436*4882a593Smuzhiyun 	printk(KERN_INFO " -%i- GF1  voice ctrl, ramp ctrl  = 0x%x, 0x%x\n", voice, ctrl = snd_gf1_i_read8(gus, 0), snd_gf1_i_read8(gus, 0x0d));
437*4882a593Smuzhiyun 	printk(KERN_INFO " -%i- GF1  frequency              = 0x%x\n", voice, snd_gf1_i_read16(gus, 1));
438*4882a593Smuzhiyun 	printk(KERN_INFO " -%i- GF1  loop start, end        = 0x%x (0x%x), 0x%x (0x%x)\n", voice, snd_gf1_i_read_addr(gus, 2, ctrl & 4), snd_gf1_i_read_addr(gus, 2, (ctrl & 4) ^ 4), snd_gf1_i_read_addr(gus, 4, ctrl & 4), snd_gf1_i_read_addr(gus, 4, (ctrl & 4) ^ 4));
439*4882a593Smuzhiyun 	printk(KERN_INFO " -%i- GF1  ramp start, end, rate  = 0x%x, 0x%x, 0x%x\n", voice, snd_gf1_i_read8(gus, 7), snd_gf1_i_read8(gus, 8), snd_gf1_i_read8(gus, 6));
440*4882a593Smuzhiyun 	printk(KERN_INFO" -%i- GF1  volume                 = 0x%x\n", voice, snd_gf1_i_read16(gus, 9));
441*4882a593Smuzhiyun 	printk(KERN_INFO " -%i- GF1  position               = 0x%x (0x%x)\n", voice, snd_gf1_i_read_addr(gus, 0x0a, ctrl & 4), snd_gf1_i_read_addr(gus, 0x0a, (ctrl & 4) ^ 4));
442*4882a593Smuzhiyun 	if (gus->interwave && snd_gf1_i_read8(gus, 0x19) & 0x01) {	/* enhanced mode */
443*4882a593Smuzhiyun 		mode = snd_gf1_i_read8(gus, 0x15);
444*4882a593Smuzhiyun 		printk(KERN_INFO " -%i- GFA1 mode                   = 0x%x\n", voice, mode);
445*4882a593Smuzhiyun 		if (mode & 0x01) {	/* Effect processor */
446*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GFA1 effect address         = 0x%x\n", voice, snd_gf1_i_read_addr(gus, 0x11, ctrl & 4));
447*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GFA1 effect volume          = 0x%x\n", voice, snd_gf1_i_read16(gus, 0x16));
448*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GFA1 effect volume final    = 0x%x\n", voice, snd_gf1_i_read16(gus, 0x1d));
449*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GFA1 effect accumulator     = 0x%x\n", voice, snd_gf1_i_read8(gus, 0x14));
450*4882a593Smuzhiyun 		}
451*4882a593Smuzhiyun 		if (mode & 0x20) {
452*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GFA1 left offset            = 0x%x (%i)\n", voice, snd_gf1_i_read16(gus, 0x13), snd_gf1_i_read16(gus, 0x13) >> 4);
453*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GFA1 left offset final      = 0x%x (%i)\n", voice, snd_gf1_i_read16(gus, 0x1c), snd_gf1_i_read16(gus, 0x1c) >> 4);
454*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GFA1 right offset           = 0x%x (%i)\n", voice, snd_gf1_i_read16(gus, 0x0c), snd_gf1_i_read16(gus, 0x0c) >> 4);
455*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GFA1 right offset final     = 0x%x (%i)\n", voice, snd_gf1_i_read16(gus, 0x1b), snd_gf1_i_read16(gus, 0x1b) >> 4);
456*4882a593Smuzhiyun 		} else
457*4882a593Smuzhiyun 			printk(KERN_INFO " -%i- GF1  pan                    = 0x%x\n", voice, snd_gf1_i_read8(gus, 0x0c));
458*4882a593Smuzhiyun 	} else
459*4882a593Smuzhiyun 		printk(KERN_INFO " -%i- GF1  pan                    = 0x%x\n", voice, snd_gf1_i_read8(gus, 0x0c));
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun #if 0
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun void snd_gf1_print_global_registers(struct snd_gus_card * gus)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun 	unsigned char global_mode = 0x00;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	printk(KERN_INFO " -G- GF1 active voices            = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_ACTIVE_VOICES));
469*4882a593Smuzhiyun 	if (gus->interwave) {
470*4882a593Smuzhiyun 		global_mode = snd_gf1_i_read8(gus, SNDRV_GF1_GB_GLOBAL_MODE);
471*4882a593Smuzhiyun 		printk(KERN_INFO " -G- GF1 global mode              = 0x%x\n", global_mode);
472*4882a593Smuzhiyun 	}
473*4882a593Smuzhiyun 	if (global_mode & 0x02)	/* LFO enabled? */
474*4882a593Smuzhiyun 		printk(KERN_INFO " -G- GF1 LFO base                 = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_LFO_BASE));
475*4882a593Smuzhiyun 	printk(KERN_INFO " -G- GF1 voices IRQ read          = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_VOICES_IRQ_READ));
476*4882a593Smuzhiyun 	printk(KERN_INFO " -G- GF1 DRAM DMA control         = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL));
477*4882a593Smuzhiyun 	printk(KERN_INFO " -G- GF1 DRAM DMA high/low        = 0x%x/0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH), snd_gf1_i_read16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW));
478*4882a593Smuzhiyun 	printk(KERN_INFO " -G- GF1 DRAM IO high/low         = 0x%x/0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_DRAM_IO_HIGH), snd_gf1_i_read16(gus, SNDRV_GF1_GW_DRAM_IO_LOW));
479*4882a593Smuzhiyun 	if (!gus->interwave)
480*4882a593Smuzhiyun 		printk(KERN_INFO " -G- GF1 record DMA control       = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_REC_DMA_CONTROL));
481*4882a593Smuzhiyun 	printk(KERN_INFO " -G- GF1 DRAM IO 16               = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_DRAM_IO16));
482*4882a593Smuzhiyun 	if (gus->gf1.enh_mode) {
483*4882a593Smuzhiyun 		printk(KERN_INFO " -G- GFA1 memory config           = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_MEMORY_CONFIG));
484*4882a593Smuzhiyun 		printk(KERN_INFO " -G- GFA1 memory control          = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_MEMORY_CONTROL));
485*4882a593Smuzhiyun 		printk(KERN_INFO " -G- GFA1 FIFO record base        = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_FIFO_RECORD_BASE_ADDR));
486*4882a593Smuzhiyun 		printk(KERN_INFO " -G- GFA1 FIFO playback base      = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_FIFO_PLAY_BASE_ADDR));
487*4882a593Smuzhiyun 		printk(KERN_INFO " -G- GFA1 interleave control      = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_INTERLEAVE));
488*4882a593Smuzhiyun 	}
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun void snd_gf1_print_setup_registers(struct snd_gus_card * gus)
492*4882a593Smuzhiyun {
493*4882a593Smuzhiyun 	printk(KERN_INFO " -S- mix control                  = 0x%x\n", inb(GUSP(gus, MIXCNTRLREG)));
494*4882a593Smuzhiyun 	printk(KERN_INFO " -S- IRQ status                   = 0x%x\n", inb(GUSP(gus, IRQSTAT)));
495*4882a593Smuzhiyun 	printk(KERN_INFO " -S- timer control                = 0x%x\n", inb(GUSP(gus, TIMERCNTRL)));
496*4882a593Smuzhiyun 	printk(KERN_INFO " -S- timer data                   = 0x%x\n", inb(GUSP(gus, TIMERDATA)));
497*4882a593Smuzhiyun 	printk(KERN_INFO " -S- status read                  = 0x%x\n", inb(GUSP(gus, REGCNTRLS)));
498*4882a593Smuzhiyun 	printk(KERN_INFO " -S- Sound Blaster control        = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_SOUND_BLASTER_CONTROL));
499*4882a593Smuzhiyun 	printk(KERN_INFO " -S- AdLib timer 1/2              = 0x%x/0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_ADLIB_TIMER_1), snd_gf1_i_look8(gus, SNDRV_GF1_GB_ADLIB_TIMER_2));
500*4882a593Smuzhiyun 	printk(KERN_INFO " -S- reset                        = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_RESET));
501*4882a593Smuzhiyun 	if (gus->interwave) {
502*4882a593Smuzhiyun 		printk(KERN_INFO " -S- compatibility                = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_COMPATIBILITY));
503*4882a593Smuzhiyun 		printk(KERN_INFO " -S- decode control               = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_DECODE_CONTROL));
504*4882a593Smuzhiyun 		printk(KERN_INFO " -S- version number               = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_VERSION_NUMBER));
505*4882a593Smuzhiyun 		printk(KERN_INFO " -S- MPU-401 emul. control A/B    = 0x%x/0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_MPU401_CONTROL_A), snd_gf1_i_look8(gus, SNDRV_GF1_GB_MPU401_CONTROL_B));
506*4882a593Smuzhiyun 		printk(KERN_INFO " -S- emulation IRQ                = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_EMULATION_IRQ));
507*4882a593Smuzhiyun 	}
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun void snd_gf1_peek_print_block(struct snd_gus_card * gus, unsigned int addr, int count, int w_16bit)
511*4882a593Smuzhiyun {
512*4882a593Smuzhiyun 	if (!w_16bit) {
513*4882a593Smuzhiyun 		while (count-- > 0)
514*4882a593Smuzhiyun 			printk(count > 0 ? "%02x:" : "%02x", snd_gf1_peek(gus, addr++));
515*4882a593Smuzhiyun 	} else {
516*4882a593Smuzhiyun 		while (count-- > 0) {
517*4882a593Smuzhiyun 			printk(count > 0 ? "%04x:" : "%04x", snd_gf1_peek(gus, addr) | (snd_gf1_peek(gus, addr + 1) << 8));
518*4882a593Smuzhiyun 			addr += 2;
519*4882a593Smuzhiyun 		}
520*4882a593Smuzhiyun 	}
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun #endif  /*  0  */
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun #endif
526