xref: /OK3568_Linux_fs/kernel/sound/isa/cs423x/cs4236_lib.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4*4882a593Smuzhiyun  *  Routines for control of CS4235/4236B/4237B/4238B/4239 chips
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  *  Note:
7*4882a593Smuzhiyun  *     -----
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  *  Bugs:
10*4882a593Smuzhiyun  *     -----
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun  *  Indirect control registers (CS4236B+)
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  *  C0
17*4882a593Smuzhiyun  *     D8: WSS reset (all chips)
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  *  C1 (all chips except CS4236)
20*4882a593Smuzhiyun  *     D7-D5: version
21*4882a593Smuzhiyun  *     D4-D0: chip id
22*4882a593Smuzhiyun  *             11101 - CS4235
23*4882a593Smuzhiyun  *             01011 - CS4236B
24*4882a593Smuzhiyun  *             01000 - CS4237B
25*4882a593Smuzhiyun  *             01001 - CS4238B
26*4882a593Smuzhiyun  *             11110 - CS4239
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  *  C2
29*4882a593Smuzhiyun  *     D7-D4: 3D Space (CS4235,CS4237B,CS4238B,CS4239)
30*4882a593Smuzhiyun  *     D3-D0: 3D Center (CS4237B); 3D Volume (CS4238B)
31*4882a593Smuzhiyun  *
32*4882a593Smuzhiyun  *  C3
33*4882a593Smuzhiyun  *     D7: 3D Enable (CS4237B)
34*4882a593Smuzhiyun  *     D6: 3D Mono Enable (CS4237B)
35*4882a593Smuzhiyun  *     D5: 3D Serial Output (CS4237B,CS4238B)
36*4882a593Smuzhiyun  *     D4: 3D Enable (CS4235,CS4238B,CS4239)
37*4882a593Smuzhiyun  *
38*4882a593Smuzhiyun  *  C4
39*4882a593Smuzhiyun  *     D7: consumer serial port enable (CS4237B,CS4238B)
40*4882a593Smuzhiyun  *     D6: channels status block reset (CS4237B,CS4238B)
41*4882a593Smuzhiyun  *     D5: user bit in sub-frame of digital audio data (CS4237B,CS4238B)
42*4882a593Smuzhiyun  *     D4: validity bit in sub-frame of digital audio data (CS4237B,CS4238B)
43*4882a593Smuzhiyun  *
44*4882a593Smuzhiyun  *  C5  lower channel status (digital serial data description) (CS4237B,CS4238B)
45*4882a593Smuzhiyun  *     D7-D6: first two bits of category code
46*4882a593Smuzhiyun  *     D5: lock
47*4882a593Smuzhiyun  *     D4-D3: pre-emphasis (0 = none, 1 = 50/15us)
48*4882a593Smuzhiyun  *     D2: copy/copyright (0 = copy inhibited)
49*4882a593Smuzhiyun  *     D1: 0 = digital audio / 1 = non-digital audio
50*4882a593Smuzhiyun  *
51*4882a593Smuzhiyun  *  C6  upper channel status (digital serial data description) (CS4237B,CS4238B)
52*4882a593Smuzhiyun  *     D7-D6: sample frequency (0 = 44.1kHz)
53*4882a593Smuzhiyun  *     D5: generation status (0 = no indication, 1 = original/commercially precaptureed data)
54*4882a593Smuzhiyun  *     D4-D0: category code (upper bits)
55*4882a593Smuzhiyun  *
56*4882a593Smuzhiyun  *  C7  reserved (must write 0)
57*4882a593Smuzhiyun  *
58*4882a593Smuzhiyun  *  C8  wavetable control
59*4882a593Smuzhiyun  *     D7: volume control interrupt enable (CS4235,CS4239)
60*4882a593Smuzhiyun  *     D6: hardware volume control format (CS4235,CS4239)
61*4882a593Smuzhiyun  *     D3: wavetable serial port enable (all chips)
62*4882a593Smuzhiyun  *     D2: DSP serial port switch (all chips)
63*4882a593Smuzhiyun  *     D1: disable MCLK (all chips)
64*4882a593Smuzhiyun  *     D0: force BRESET low (all chips)
65*4882a593Smuzhiyun  *
66*4882a593Smuzhiyun  */
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #include <linux/io.h>
69*4882a593Smuzhiyun #include <linux/delay.h>
70*4882a593Smuzhiyun #include <linux/init.h>
71*4882a593Smuzhiyun #include <linux/time.h>
72*4882a593Smuzhiyun #include <linux/wait.h>
73*4882a593Smuzhiyun #include <sound/core.h>
74*4882a593Smuzhiyun #include <sound/wss.h>
75*4882a593Smuzhiyun #include <sound/asoundef.h>
76*4882a593Smuzhiyun #include <sound/initval.h>
77*4882a593Smuzhiyun #include <sound/tlv.h>
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun  *
81*4882a593Smuzhiyun  */
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun static const unsigned char snd_cs4236_ext_map[18] = {
84*4882a593Smuzhiyun 	/* CS4236_LEFT_LINE */		0xff,
85*4882a593Smuzhiyun 	/* CS4236_RIGHT_LINE */		0xff,
86*4882a593Smuzhiyun 	/* CS4236_LEFT_MIC */		0xdf,
87*4882a593Smuzhiyun 	/* CS4236_RIGHT_MIC */		0xdf,
88*4882a593Smuzhiyun 	/* CS4236_LEFT_MIX_CTRL */	0xe0 | 0x18,
89*4882a593Smuzhiyun 	/* CS4236_RIGHT_MIX_CTRL */	0xe0,
90*4882a593Smuzhiyun 	/* CS4236_LEFT_FM */		0xbf,
91*4882a593Smuzhiyun 	/* CS4236_RIGHT_FM */		0xbf,
92*4882a593Smuzhiyun 	/* CS4236_LEFT_DSP */		0xbf,
93*4882a593Smuzhiyun 	/* CS4236_RIGHT_DSP */		0xbf,
94*4882a593Smuzhiyun 	/* CS4236_RIGHT_LOOPBACK */	0xbf,
95*4882a593Smuzhiyun 	/* CS4236_DAC_MUTE */		0xe0,
96*4882a593Smuzhiyun 	/* CS4236_ADC_RATE */		0x01,	/* 48kHz */
97*4882a593Smuzhiyun 	/* CS4236_DAC_RATE */		0x01,	/* 48kHz */
98*4882a593Smuzhiyun 	/* CS4236_LEFT_MASTER */	0xbf,
99*4882a593Smuzhiyun 	/* CS4236_RIGHT_MASTER */	0xbf,
100*4882a593Smuzhiyun 	/* CS4236_LEFT_WAVE */		0xbf,
101*4882a593Smuzhiyun 	/* CS4236_RIGHT_WAVE */		0xbf
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /*
105*4882a593Smuzhiyun  *
106*4882a593Smuzhiyun  */
107*4882a593Smuzhiyun 
snd_cs4236_ctrl_out(struct snd_wss * chip,unsigned char reg,unsigned char val)108*4882a593Smuzhiyun static void snd_cs4236_ctrl_out(struct snd_wss *chip,
109*4882a593Smuzhiyun 				unsigned char reg, unsigned char val)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	outb(reg, chip->cport + 3);
112*4882a593Smuzhiyun 	outb(chip->cimage[reg] = val, chip->cport + 4);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
snd_cs4236_ctrl_in(struct snd_wss * chip,unsigned char reg)115*4882a593Smuzhiyun static unsigned char snd_cs4236_ctrl_in(struct snd_wss *chip, unsigned char reg)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	outb(reg, chip->cport + 3);
118*4882a593Smuzhiyun 	return inb(chip->cport + 4);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /*
122*4882a593Smuzhiyun  *  PCM
123*4882a593Smuzhiyun  */
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun #define CLOCKS 8
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun static const struct snd_ratnum clocks[CLOCKS] = {
128*4882a593Smuzhiyun 	{ .num = 16934400, .den_min = 353, .den_max = 353, .den_step = 1 },
129*4882a593Smuzhiyun 	{ .num = 16934400, .den_min = 529, .den_max = 529, .den_step = 1 },
130*4882a593Smuzhiyun 	{ .num = 16934400, .den_min = 617, .den_max = 617, .den_step = 1 },
131*4882a593Smuzhiyun 	{ .num = 16934400, .den_min = 1058, .den_max = 1058, .den_step = 1 },
132*4882a593Smuzhiyun 	{ .num = 16934400, .den_min = 1764, .den_max = 1764, .den_step = 1 },
133*4882a593Smuzhiyun 	{ .num = 16934400, .den_min = 2117, .den_max = 2117, .den_step = 1 },
134*4882a593Smuzhiyun 	{ .num = 16934400, .den_min = 2558, .den_max = 2558, .den_step = 1 },
135*4882a593Smuzhiyun 	{ .num = 16934400/16, .den_min = 21, .den_max = 192, .den_step = 1 }
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_ratnums hw_constraints_clocks = {
139*4882a593Smuzhiyun 	.nrats = CLOCKS,
140*4882a593Smuzhiyun 	.rats = clocks,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
snd_cs4236_xrate(struct snd_pcm_runtime * runtime)143*4882a593Smuzhiyun static int snd_cs4236_xrate(struct snd_pcm_runtime *runtime)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	return snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
146*4882a593Smuzhiyun 					     &hw_constraints_clocks);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
divisor_to_rate_register(unsigned int divisor)149*4882a593Smuzhiyun static unsigned char divisor_to_rate_register(unsigned int divisor)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	switch (divisor) {
152*4882a593Smuzhiyun 	case 353:	return 1;
153*4882a593Smuzhiyun 	case 529:	return 2;
154*4882a593Smuzhiyun 	case 617:	return 3;
155*4882a593Smuzhiyun 	case 1058:	return 4;
156*4882a593Smuzhiyun 	case 1764:	return 5;
157*4882a593Smuzhiyun 	case 2117:	return 6;
158*4882a593Smuzhiyun 	case 2558:	return 7;
159*4882a593Smuzhiyun 	default:
160*4882a593Smuzhiyun 		if (divisor < 21 || divisor > 192) {
161*4882a593Smuzhiyun 			snd_BUG();
162*4882a593Smuzhiyun 			return 192;
163*4882a593Smuzhiyun 		}
164*4882a593Smuzhiyun 		return divisor;
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
snd_cs4236_playback_format(struct snd_wss * chip,struct snd_pcm_hw_params * params,unsigned char pdfr)168*4882a593Smuzhiyun static void snd_cs4236_playback_format(struct snd_wss *chip,
169*4882a593Smuzhiyun 				       struct snd_pcm_hw_params *params,
170*4882a593Smuzhiyun 				       unsigned char pdfr)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	unsigned long flags;
173*4882a593Smuzhiyun 	unsigned char rate = divisor_to_rate_register(params->rate_den);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
176*4882a593Smuzhiyun 	/* set fast playback format change and clean playback FIFO */
177*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_ALT_FEATURE_1,
178*4882a593Smuzhiyun 		    chip->image[CS4231_ALT_FEATURE_1] | 0x10);
179*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr & 0xf0);
180*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_ALT_FEATURE_1,
181*4882a593Smuzhiyun 		    chip->image[CS4231_ALT_FEATURE_1] & ~0x10);
182*4882a593Smuzhiyun 	snd_cs4236_ext_out(chip, CS4236_DAC_RATE, rate);
183*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
snd_cs4236_capture_format(struct snd_wss * chip,struct snd_pcm_hw_params * params,unsigned char cdfr)186*4882a593Smuzhiyun static void snd_cs4236_capture_format(struct snd_wss *chip,
187*4882a593Smuzhiyun 				      struct snd_pcm_hw_params *params,
188*4882a593Smuzhiyun 				      unsigned char cdfr)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	unsigned long flags;
191*4882a593Smuzhiyun 	unsigned char rate = divisor_to_rate_register(params->rate_den);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
194*4882a593Smuzhiyun 	/* set fast capture format change and clean capture FIFO */
195*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_ALT_FEATURE_1,
196*4882a593Smuzhiyun 		    chip->image[CS4231_ALT_FEATURE_1] | 0x20);
197*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_REC_FORMAT, cdfr & 0xf0);
198*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_ALT_FEATURE_1,
199*4882a593Smuzhiyun 		    chip->image[CS4231_ALT_FEATURE_1] & ~0x20);
200*4882a593Smuzhiyun 	snd_cs4236_ext_out(chip, CS4236_ADC_RATE, rate);
201*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun #ifdef CONFIG_PM
205*4882a593Smuzhiyun 
snd_cs4236_suspend(struct snd_wss * chip)206*4882a593Smuzhiyun static void snd_cs4236_suspend(struct snd_wss *chip)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun 	int reg;
209*4882a593Smuzhiyun 	unsigned long flags;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
212*4882a593Smuzhiyun 	for (reg = 0; reg < 32; reg++)
213*4882a593Smuzhiyun 		chip->image[reg] = snd_wss_in(chip, reg);
214*4882a593Smuzhiyun 	for (reg = 0; reg < 18; reg++)
215*4882a593Smuzhiyun 		chip->eimage[reg] = snd_cs4236_ext_in(chip, CS4236_I23VAL(reg));
216*4882a593Smuzhiyun 	for (reg = 2; reg < 9; reg++)
217*4882a593Smuzhiyun 		chip->cimage[reg] = snd_cs4236_ctrl_in(chip, reg);
218*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
snd_cs4236_resume(struct snd_wss * chip)221*4882a593Smuzhiyun static void snd_cs4236_resume(struct snd_wss *chip)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun 	int reg;
224*4882a593Smuzhiyun 	unsigned long flags;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	snd_wss_mce_up(chip);
227*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
228*4882a593Smuzhiyun 	for (reg = 0; reg < 32; reg++) {
229*4882a593Smuzhiyun 		switch (reg) {
230*4882a593Smuzhiyun 		case CS4236_EXT_REG:
231*4882a593Smuzhiyun 		case CS4231_VERSION:
232*4882a593Smuzhiyun 		case 27:	/* why? CS4235 - master left */
233*4882a593Smuzhiyun 		case 29:	/* why? CS4235 - master right */
234*4882a593Smuzhiyun 			break;
235*4882a593Smuzhiyun 		default:
236*4882a593Smuzhiyun 			snd_wss_out(chip, reg, chip->image[reg]);
237*4882a593Smuzhiyun 			break;
238*4882a593Smuzhiyun 		}
239*4882a593Smuzhiyun 	}
240*4882a593Smuzhiyun 	for (reg = 0; reg < 18; reg++)
241*4882a593Smuzhiyun 		snd_cs4236_ext_out(chip, CS4236_I23VAL(reg), chip->eimage[reg]);
242*4882a593Smuzhiyun 	for (reg = 2; reg < 9; reg++) {
243*4882a593Smuzhiyun 		switch (reg) {
244*4882a593Smuzhiyun 		case 7:
245*4882a593Smuzhiyun 			break;
246*4882a593Smuzhiyun 		default:
247*4882a593Smuzhiyun 			snd_cs4236_ctrl_out(chip, reg, chip->cimage[reg]);
248*4882a593Smuzhiyun 		}
249*4882a593Smuzhiyun 	}
250*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
251*4882a593Smuzhiyun 	snd_wss_mce_down(chip);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun #endif /* CONFIG_PM */
255*4882a593Smuzhiyun /*
256*4882a593Smuzhiyun  * This function does no fail if the chip is not CS4236B or compatible.
257*4882a593Smuzhiyun  * It just an equivalent to the snd_wss_create() then.
258*4882a593Smuzhiyun  */
snd_cs4236_create(struct snd_card * card,unsigned long port,unsigned long cport,int irq,int dma1,int dma2,unsigned short hardware,unsigned short hwshare,struct snd_wss ** rchip)259*4882a593Smuzhiyun int snd_cs4236_create(struct snd_card *card,
260*4882a593Smuzhiyun 		      unsigned long port,
261*4882a593Smuzhiyun 		      unsigned long cport,
262*4882a593Smuzhiyun 		      int irq, int dma1, int dma2,
263*4882a593Smuzhiyun 		      unsigned short hardware,
264*4882a593Smuzhiyun 		      unsigned short hwshare,
265*4882a593Smuzhiyun 		      struct snd_wss **rchip)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	struct snd_wss *chip;
268*4882a593Smuzhiyun 	unsigned char ver1, ver2;
269*4882a593Smuzhiyun 	unsigned int reg;
270*4882a593Smuzhiyun 	int err;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	*rchip = NULL;
273*4882a593Smuzhiyun 	if (hardware == WSS_HW_DETECT)
274*4882a593Smuzhiyun 		hardware = WSS_HW_DETECT3;
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	err = snd_wss_create(card, port, cport,
277*4882a593Smuzhiyun 			     irq, dma1, dma2, hardware, hwshare, &chip);
278*4882a593Smuzhiyun 	if (err < 0)
279*4882a593Smuzhiyun 		return err;
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	if ((chip->hardware & WSS_HW_CS4236B_MASK) == 0) {
282*4882a593Smuzhiyun 		snd_printd("chip is not CS4236+, hardware=0x%x\n",
283*4882a593Smuzhiyun 			   chip->hardware);
284*4882a593Smuzhiyun 		*rchip = chip;
285*4882a593Smuzhiyun 		return 0;
286*4882a593Smuzhiyun 	}
287*4882a593Smuzhiyun #if 0
288*4882a593Smuzhiyun 	{
289*4882a593Smuzhiyun 		int idx;
290*4882a593Smuzhiyun 		for (idx = 0; idx < 8; idx++)
291*4882a593Smuzhiyun 			snd_printk(KERN_DEBUG "CD%i = 0x%x\n",
292*4882a593Smuzhiyun 				   idx, inb(chip->cport + idx));
293*4882a593Smuzhiyun 		for (idx = 0; idx < 9; idx++)
294*4882a593Smuzhiyun 			snd_printk(KERN_DEBUG "C%i = 0x%x\n",
295*4882a593Smuzhiyun 				   idx, snd_cs4236_ctrl_in(chip, idx));
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun #endif
298*4882a593Smuzhiyun 	if (cport < 0x100 || cport == SNDRV_AUTO_PORT) {
299*4882a593Smuzhiyun 		snd_printk(KERN_ERR "please, specify control port "
300*4882a593Smuzhiyun 			   "for CS4236+ chips\n");
301*4882a593Smuzhiyun 		snd_device_free(card, chip);
302*4882a593Smuzhiyun 		return -ENODEV;
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 	ver1 = snd_cs4236_ctrl_in(chip, 1);
305*4882a593Smuzhiyun 	ver2 = snd_cs4236_ext_in(chip, CS4236_VERSION);
306*4882a593Smuzhiyun 	snd_printdd("CS4236: [0x%lx] C1 (version) = 0x%x, ext = 0x%x\n",
307*4882a593Smuzhiyun 			cport, ver1, ver2);
308*4882a593Smuzhiyun 	if (ver1 != ver2) {
309*4882a593Smuzhiyun 		snd_printk(KERN_ERR "CS4236+ chip detected, but "
310*4882a593Smuzhiyun 			   "control port 0x%lx is not valid\n", cport);
311*4882a593Smuzhiyun 		snd_device_free(card, chip);
312*4882a593Smuzhiyun 		return -ENODEV;
313*4882a593Smuzhiyun 	}
314*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 0, 0x00);
315*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 2, 0xff);
316*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 3, 0x00);
317*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 4, 0x80);
318*4882a593Smuzhiyun 	reg = ((IEC958_AES1_CON_PCM_CODER & 3) << 6) |
319*4882a593Smuzhiyun 	      IEC958_AES0_CON_EMPHASIS_NONE;
320*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 5, reg);
321*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 6, IEC958_AES1_CON_PCM_CODER >> 2);
322*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 7, 0x00);
323*4882a593Smuzhiyun 	/*
324*4882a593Smuzhiyun 	 * 0x8c for C8 is valid for Turtle Beach Malibu - the IEC-958
325*4882a593Smuzhiyun 	 * output is working with this setup, other hardware should
326*4882a593Smuzhiyun 	 * have different signal paths and this value should be
327*4882a593Smuzhiyun 	 * selectable in the future
328*4882a593Smuzhiyun 	 */
329*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 8, 0x8c);
330*4882a593Smuzhiyun 	chip->rate_constraint = snd_cs4236_xrate;
331*4882a593Smuzhiyun 	chip->set_playback_format = snd_cs4236_playback_format;
332*4882a593Smuzhiyun 	chip->set_capture_format = snd_cs4236_capture_format;
333*4882a593Smuzhiyun #ifdef CONFIG_PM
334*4882a593Smuzhiyun 	chip->suspend = snd_cs4236_suspend;
335*4882a593Smuzhiyun 	chip->resume = snd_cs4236_resume;
336*4882a593Smuzhiyun #endif
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	/* initialize extended registers */
339*4882a593Smuzhiyun 	for (reg = 0; reg < sizeof(snd_cs4236_ext_map); reg++)
340*4882a593Smuzhiyun 		snd_cs4236_ext_out(chip, CS4236_I23VAL(reg),
341*4882a593Smuzhiyun 				   snd_cs4236_ext_map[reg]);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	/* initialize compatible but more featured registers */
344*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_LEFT_INPUT, 0x40);
345*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_RIGHT_INPUT, 0x40);
346*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_AUX1_LEFT_INPUT, 0xff);
347*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_AUX1_RIGHT_INPUT, 0xff);
348*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_AUX2_LEFT_INPUT, 0xdf);
349*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_AUX2_RIGHT_INPUT, 0xdf);
350*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_RIGHT_LINE_IN, 0xff);
351*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_LEFT_LINE_IN, 0xff);
352*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_RIGHT_LINE_IN, 0xff);
353*4882a593Smuzhiyun 	switch (chip->hardware) {
354*4882a593Smuzhiyun 	case WSS_HW_CS4235:
355*4882a593Smuzhiyun 	case WSS_HW_CS4239:
356*4882a593Smuzhiyun 		snd_wss_out(chip, CS4235_LEFT_MASTER, 0xff);
357*4882a593Smuzhiyun 		snd_wss_out(chip, CS4235_RIGHT_MASTER, 0xff);
358*4882a593Smuzhiyun 		break;
359*4882a593Smuzhiyun 	}
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	*rchip = chip;
362*4882a593Smuzhiyun 	return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun 
snd_cs4236_pcm(struct snd_wss * chip,int device)365*4882a593Smuzhiyun int snd_cs4236_pcm(struct snd_wss *chip, int device)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	int err;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	err = snd_wss_pcm(chip, device);
370*4882a593Smuzhiyun 	if (err < 0)
371*4882a593Smuzhiyun 		return err;
372*4882a593Smuzhiyun 	chip->pcm->info_flags &= ~SNDRV_PCM_INFO_JOINT_DUPLEX;
373*4882a593Smuzhiyun 	return 0;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun /*
377*4882a593Smuzhiyun  *  MIXER
378*4882a593Smuzhiyun  */
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun #define CS4236_SINGLE(xname, xindex, reg, shift, mask, invert) \
381*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
382*4882a593Smuzhiyun   .info = snd_cs4236_info_single, \
383*4882a593Smuzhiyun   .get = snd_cs4236_get_single, .put = snd_cs4236_put_single, \
384*4882a593Smuzhiyun   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun #define CS4236_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
387*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
388*4882a593Smuzhiyun   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
389*4882a593Smuzhiyun   .info = snd_cs4236_info_single, \
390*4882a593Smuzhiyun   .get = snd_cs4236_get_single, .put = snd_cs4236_put_single, \
391*4882a593Smuzhiyun   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
392*4882a593Smuzhiyun   .tlv = { .p = (xtlv) } }
393*4882a593Smuzhiyun 
snd_cs4236_info_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)394*4882a593Smuzhiyun static int snd_cs4236_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
399*4882a593Smuzhiyun 	uinfo->count = 1;
400*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
401*4882a593Smuzhiyun 	uinfo->value.integer.max = mask;
402*4882a593Smuzhiyun 	return 0;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun 
snd_cs4236_get_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)405*4882a593Smuzhiyun static int snd_cs4236_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
408*4882a593Smuzhiyun 	unsigned long flags;
409*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
410*4882a593Smuzhiyun 	int shift = (kcontrol->private_value >> 8) & 0xff;
411*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
412*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
415*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (chip->eimage[CS4236_REG(reg)] >> shift) & mask;
416*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
417*4882a593Smuzhiyun 	if (invert)
418*4882a593Smuzhiyun 		ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
419*4882a593Smuzhiyun 	return 0;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun 
snd_cs4236_put_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)422*4882a593Smuzhiyun static int snd_cs4236_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
425*4882a593Smuzhiyun 	unsigned long flags;
426*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
427*4882a593Smuzhiyun 	int shift = (kcontrol->private_value >> 8) & 0xff;
428*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
429*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
430*4882a593Smuzhiyun 	int change;
431*4882a593Smuzhiyun 	unsigned short val;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	val = (ucontrol->value.integer.value[0] & mask);
434*4882a593Smuzhiyun 	if (invert)
435*4882a593Smuzhiyun 		val = mask - val;
436*4882a593Smuzhiyun 	val <<= shift;
437*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
438*4882a593Smuzhiyun 	val = (chip->eimage[CS4236_REG(reg)] & ~(mask << shift)) | val;
439*4882a593Smuzhiyun 	change = val != chip->eimage[CS4236_REG(reg)];
440*4882a593Smuzhiyun 	snd_cs4236_ext_out(chip, reg, val);
441*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
442*4882a593Smuzhiyun 	return change;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun #define CS4236_SINGLEC(xname, xindex, reg, shift, mask, invert) \
446*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
447*4882a593Smuzhiyun   .info = snd_cs4236_info_single, \
448*4882a593Smuzhiyun   .get = snd_cs4236_get_singlec, .put = snd_cs4236_put_singlec, \
449*4882a593Smuzhiyun   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
450*4882a593Smuzhiyun 
snd_cs4236_get_singlec(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)451*4882a593Smuzhiyun static int snd_cs4236_get_singlec(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
454*4882a593Smuzhiyun 	unsigned long flags;
455*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
456*4882a593Smuzhiyun 	int shift = (kcontrol->private_value >> 8) & 0xff;
457*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
458*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
461*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (chip->cimage[reg] >> shift) & mask;
462*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
463*4882a593Smuzhiyun 	if (invert)
464*4882a593Smuzhiyun 		ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
465*4882a593Smuzhiyun 	return 0;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun 
snd_cs4236_put_singlec(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)468*4882a593Smuzhiyun static int snd_cs4236_put_singlec(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
471*4882a593Smuzhiyun 	unsigned long flags;
472*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
473*4882a593Smuzhiyun 	int shift = (kcontrol->private_value >> 8) & 0xff;
474*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
475*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
476*4882a593Smuzhiyun 	int change;
477*4882a593Smuzhiyun 	unsigned short val;
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	val = (ucontrol->value.integer.value[0] & mask);
480*4882a593Smuzhiyun 	if (invert)
481*4882a593Smuzhiyun 		val = mask - val;
482*4882a593Smuzhiyun 	val <<= shift;
483*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
484*4882a593Smuzhiyun 	val = (chip->cimage[reg] & ~(mask << shift)) | val;
485*4882a593Smuzhiyun 	change = val != chip->cimage[reg];
486*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, reg, val);
487*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
488*4882a593Smuzhiyun 	return change;
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun #define CS4236_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
492*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
493*4882a593Smuzhiyun   .info = snd_cs4236_info_double, \
494*4882a593Smuzhiyun   .get = snd_cs4236_get_double, .put = snd_cs4236_put_double, \
495*4882a593Smuzhiyun   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun #define CS4236_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, \
498*4882a593Smuzhiyun 			  shift_right, mask, invert, xtlv) \
499*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
500*4882a593Smuzhiyun   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
501*4882a593Smuzhiyun   .info = snd_cs4236_info_double, \
502*4882a593Smuzhiyun   .get = snd_cs4236_get_double, .put = snd_cs4236_put_double, \
503*4882a593Smuzhiyun   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \
504*4882a593Smuzhiyun 		   (shift_right << 19) | (mask << 24) | (invert << 22), \
505*4882a593Smuzhiyun   .tlv = { .p = (xtlv) } }
506*4882a593Smuzhiyun 
snd_cs4236_info_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)507*4882a593Smuzhiyun static int snd_cs4236_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 24) & 0xff;
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
512*4882a593Smuzhiyun 	uinfo->count = 2;
513*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
514*4882a593Smuzhiyun 	uinfo->value.integer.max = mask;
515*4882a593Smuzhiyun 	return 0;
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun 
snd_cs4236_get_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)518*4882a593Smuzhiyun static int snd_cs4236_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
521*4882a593Smuzhiyun 	unsigned long flags;
522*4882a593Smuzhiyun 	int left_reg = kcontrol->private_value & 0xff;
523*4882a593Smuzhiyun 	int right_reg = (kcontrol->private_value >> 8) & 0xff;
524*4882a593Smuzhiyun 	int shift_left = (kcontrol->private_value >> 16) & 0x07;
525*4882a593Smuzhiyun 	int shift_right = (kcontrol->private_value >> 19) & 0x07;
526*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 24) & 0xff;
527*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 22) & 1;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
530*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (chip->eimage[CS4236_REG(left_reg)] >> shift_left) & mask;
531*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] = (chip->eimage[CS4236_REG(right_reg)] >> shift_right) & mask;
532*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
533*4882a593Smuzhiyun 	if (invert) {
534*4882a593Smuzhiyun 		ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
535*4882a593Smuzhiyun 		ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
536*4882a593Smuzhiyun 	}
537*4882a593Smuzhiyun 	return 0;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun 
snd_cs4236_put_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)540*4882a593Smuzhiyun static int snd_cs4236_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
543*4882a593Smuzhiyun 	unsigned long flags;
544*4882a593Smuzhiyun 	int left_reg = kcontrol->private_value & 0xff;
545*4882a593Smuzhiyun 	int right_reg = (kcontrol->private_value >> 8) & 0xff;
546*4882a593Smuzhiyun 	int shift_left = (kcontrol->private_value >> 16) & 0x07;
547*4882a593Smuzhiyun 	int shift_right = (kcontrol->private_value >> 19) & 0x07;
548*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 24) & 0xff;
549*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 22) & 1;
550*4882a593Smuzhiyun 	int change;
551*4882a593Smuzhiyun 	unsigned short val1, val2;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	val1 = ucontrol->value.integer.value[0] & mask;
554*4882a593Smuzhiyun 	val2 = ucontrol->value.integer.value[1] & mask;
555*4882a593Smuzhiyun 	if (invert) {
556*4882a593Smuzhiyun 		val1 = mask - val1;
557*4882a593Smuzhiyun 		val2 = mask - val2;
558*4882a593Smuzhiyun 	}
559*4882a593Smuzhiyun 	val1 <<= shift_left;
560*4882a593Smuzhiyun 	val2 <<= shift_right;
561*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
562*4882a593Smuzhiyun 	if (left_reg != right_reg) {
563*4882a593Smuzhiyun 		val1 = (chip->eimage[CS4236_REG(left_reg)] & ~(mask << shift_left)) | val1;
564*4882a593Smuzhiyun 		val2 = (chip->eimage[CS4236_REG(right_reg)] & ~(mask << shift_right)) | val2;
565*4882a593Smuzhiyun 		change = val1 != chip->eimage[CS4236_REG(left_reg)] || val2 != chip->eimage[CS4236_REG(right_reg)];
566*4882a593Smuzhiyun 		snd_cs4236_ext_out(chip, left_reg, val1);
567*4882a593Smuzhiyun 		snd_cs4236_ext_out(chip, right_reg, val2);
568*4882a593Smuzhiyun 	} else {
569*4882a593Smuzhiyun 		val1 = (chip->eimage[CS4236_REG(left_reg)] & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
570*4882a593Smuzhiyun 		change = val1 != chip->eimage[CS4236_REG(left_reg)];
571*4882a593Smuzhiyun 		snd_cs4236_ext_out(chip, left_reg, val1);
572*4882a593Smuzhiyun 	}
573*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
574*4882a593Smuzhiyun 	return change;
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun #define CS4236_DOUBLE1(xname, xindex, left_reg, right_reg, shift_left, \
578*4882a593Smuzhiyun 			shift_right, mask, invert) \
579*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
580*4882a593Smuzhiyun   .info = snd_cs4236_info_double, \
581*4882a593Smuzhiyun   .get = snd_cs4236_get_double1, .put = snd_cs4236_put_double1, \
582*4882a593Smuzhiyun   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun #define CS4236_DOUBLE1_TLV(xname, xindex, left_reg, right_reg, shift_left, \
585*4882a593Smuzhiyun 			   shift_right, mask, invert, xtlv) \
586*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
587*4882a593Smuzhiyun   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
588*4882a593Smuzhiyun   .info = snd_cs4236_info_double, \
589*4882a593Smuzhiyun   .get = snd_cs4236_get_double1, .put = snd_cs4236_put_double1, \
590*4882a593Smuzhiyun   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \
591*4882a593Smuzhiyun 		   (shift_right << 19) | (mask << 24) | (invert << 22), \
592*4882a593Smuzhiyun   .tlv = { .p = (xtlv) } }
593*4882a593Smuzhiyun 
snd_cs4236_get_double1(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)594*4882a593Smuzhiyun static int snd_cs4236_get_double1(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
597*4882a593Smuzhiyun 	unsigned long flags;
598*4882a593Smuzhiyun 	int left_reg = kcontrol->private_value & 0xff;
599*4882a593Smuzhiyun 	int right_reg = (kcontrol->private_value >> 8) & 0xff;
600*4882a593Smuzhiyun 	int shift_left = (kcontrol->private_value >> 16) & 0x07;
601*4882a593Smuzhiyun 	int shift_right = (kcontrol->private_value >> 19) & 0x07;
602*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 24) & 0xff;
603*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 22) & 1;
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
606*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
607*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] = (chip->eimage[CS4236_REG(right_reg)] >> shift_right) & mask;
608*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
609*4882a593Smuzhiyun 	if (invert) {
610*4882a593Smuzhiyun 		ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
611*4882a593Smuzhiyun 		ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
612*4882a593Smuzhiyun 	}
613*4882a593Smuzhiyun 	return 0;
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun 
snd_cs4236_put_double1(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)616*4882a593Smuzhiyun static int snd_cs4236_put_double1(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
617*4882a593Smuzhiyun {
618*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
619*4882a593Smuzhiyun 	unsigned long flags;
620*4882a593Smuzhiyun 	int left_reg = kcontrol->private_value & 0xff;
621*4882a593Smuzhiyun 	int right_reg = (kcontrol->private_value >> 8) & 0xff;
622*4882a593Smuzhiyun 	int shift_left = (kcontrol->private_value >> 16) & 0x07;
623*4882a593Smuzhiyun 	int shift_right = (kcontrol->private_value >> 19) & 0x07;
624*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 24) & 0xff;
625*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 22) & 1;
626*4882a593Smuzhiyun 	int change;
627*4882a593Smuzhiyun 	unsigned short val1, val2;
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	val1 = ucontrol->value.integer.value[0] & mask;
630*4882a593Smuzhiyun 	val2 = ucontrol->value.integer.value[1] & mask;
631*4882a593Smuzhiyun 	if (invert) {
632*4882a593Smuzhiyun 		val1 = mask - val1;
633*4882a593Smuzhiyun 		val2 = mask - val2;
634*4882a593Smuzhiyun 	}
635*4882a593Smuzhiyun 	val1 <<= shift_left;
636*4882a593Smuzhiyun 	val2 <<= shift_right;
637*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
638*4882a593Smuzhiyun 	val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
639*4882a593Smuzhiyun 	val2 = (chip->eimage[CS4236_REG(right_reg)] & ~(mask << shift_right)) | val2;
640*4882a593Smuzhiyun 	change = val1 != chip->image[left_reg] || val2 != chip->eimage[CS4236_REG(right_reg)];
641*4882a593Smuzhiyun 	snd_wss_out(chip, left_reg, val1);
642*4882a593Smuzhiyun 	snd_cs4236_ext_out(chip, right_reg, val2);
643*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
644*4882a593Smuzhiyun 	return change;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun #define CS4236_MASTER_DIGITAL(xname, xindex, xtlv) \
648*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
649*4882a593Smuzhiyun   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
650*4882a593Smuzhiyun   .info = snd_cs4236_info_double, \
651*4882a593Smuzhiyun   .get = snd_cs4236_get_master_digital, .put = snd_cs4236_put_master_digital, \
652*4882a593Smuzhiyun   .private_value = 71 << 24, \
653*4882a593Smuzhiyun   .tlv = { .p = (xtlv) } }
654*4882a593Smuzhiyun 
snd_cs4236_mixer_master_digital_invert_volume(int vol)655*4882a593Smuzhiyun static inline int snd_cs4236_mixer_master_digital_invert_volume(int vol)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun 	return (vol < 64) ? 63 - vol : 64 + (71 - vol);
658*4882a593Smuzhiyun }
659*4882a593Smuzhiyun 
snd_cs4236_get_master_digital(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)660*4882a593Smuzhiyun static int snd_cs4236_get_master_digital(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
661*4882a593Smuzhiyun {
662*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
663*4882a593Smuzhiyun 	unsigned long flags;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
666*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = snd_cs4236_mixer_master_digital_invert_volume(chip->eimage[CS4236_REG(CS4236_LEFT_MASTER)] & 0x7f);
667*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] = snd_cs4236_mixer_master_digital_invert_volume(chip->eimage[CS4236_REG(CS4236_RIGHT_MASTER)] & 0x7f);
668*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
669*4882a593Smuzhiyun 	return 0;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun 
snd_cs4236_put_master_digital(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)672*4882a593Smuzhiyun static int snd_cs4236_put_master_digital(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
675*4882a593Smuzhiyun 	unsigned long flags;
676*4882a593Smuzhiyun 	int change;
677*4882a593Smuzhiyun 	unsigned short val1, val2;
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun 	val1 = snd_cs4236_mixer_master_digital_invert_volume(ucontrol->value.integer.value[0] & 0x7f);
680*4882a593Smuzhiyun 	val2 = snd_cs4236_mixer_master_digital_invert_volume(ucontrol->value.integer.value[1] & 0x7f);
681*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
682*4882a593Smuzhiyun 	val1 = (chip->eimage[CS4236_REG(CS4236_LEFT_MASTER)] & ~0x7f) | val1;
683*4882a593Smuzhiyun 	val2 = (chip->eimage[CS4236_REG(CS4236_RIGHT_MASTER)] & ~0x7f) | val2;
684*4882a593Smuzhiyun 	change = val1 != chip->eimage[CS4236_REG(CS4236_LEFT_MASTER)] || val2 != chip->eimage[CS4236_REG(CS4236_RIGHT_MASTER)];
685*4882a593Smuzhiyun 	snd_cs4236_ext_out(chip, CS4236_LEFT_MASTER, val1);
686*4882a593Smuzhiyun 	snd_cs4236_ext_out(chip, CS4236_RIGHT_MASTER, val2);
687*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
688*4882a593Smuzhiyun 	return change;
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun #define CS4235_OUTPUT_ACCU(xname, xindex, xtlv) \
692*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
693*4882a593Smuzhiyun   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
694*4882a593Smuzhiyun   .info = snd_cs4236_info_double, \
695*4882a593Smuzhiyun   .get = snd_cs4235_get_output_accu, .put = snd_cs4235_put_output_accu, \
696*4882a593Smuzhiyun   .private_value = 3 << 24, \
697*4882a593Smuzhiyun   .tlv = { .p = (xtlv) } }
698*4882a593Smuzhiyun 
snd_cs4235_mixer_output_accu_get_volume(int vol)699*4882a593Smuzhiyun static inline int snd_cs4235_mixer_output_accu_get_volume(int vol)
700*4882a593Smuzhiyun {
701*4882a593Smuzhiyun 	switch ((vol >> 5) & 3) {
702*4882a593Smuzhiyun 	case 0: return 1;
703*4882a593Smuzhiyun 	case 1: return 3;
704*4882a593Smuzhiyun 	case 2: return 2;
705*4882a593Smuzhiyun 	case 3: return 0;
706*4882a593Smuzhiyun  	}
707*4882a593Smuzhiyun 	return 3;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun 
snd_cs4235_mixer_output_accu_set_volume(int vol)710*4882a593Smuzhiyun static inline int snd_cs4235_mixer_output_accu_set_volume(int vol)
711*4882a593Smuzhiyun {
712*4882a593Smuzhiyun 	switch (vol & 3) {
713*4882a593Smuzhiyun 	case 0: return 3 << 5;
714*4882a593Smuzhiyun 	case 1: return 0 << 5;
715*4882a593Smuzhiyun 	case 2: return 2 << 5;
716*4882a593Smuzhiyun 	case 3: return 1 << 5;
717*4882a593Smuzhiyun 	}
718*4882a593Smuzhiyun 	return 1 << 5;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun 
snd_cs4235_get_output_accu(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)721*4882a593Smuzhiyun static int snd_cs4235_get_output_accu(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
722*4882a593Smuzhiyun {
723*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
724*4882a593Smuzhiyun 	unsigned long flags;
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
727*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = snd_cs4235_mixer_output_accu_get_volume(chip->image[CS4235_LEFT_MASTER]);
728*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] = snd_cs4235_mixer_output_accu_get_volume(chip->image[CS4235_RIGHT_MASTER]);
729*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
730*4882a593Smuzhiyun 	return 0;
731*4882a593Smuzhiyun }
732*4882a593Smuzhiyun 
snd_cs4235_put_output_accu(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)733*4882a593Smuzhiyun static int snd_cs4235_put_output_accu(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
734*4882a593Smuzhiyun {
735*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
736*4882a593Smuzhiyun 	unsigned long flags;
737*4882a593Smuzhiyun 	int change;
738*4882a593Smuzhiyun 	unsigned short val1, val2;
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	val1 = snd_cs4235_mixer_output_accu_set_volume(ucontrol->value.integer.value[0]);
741*4882a593Smuzhiyun 	val2 = snd_cs4235_mixer_output_accu_set_volume(ucontrol->value.integer.value[1]);
742*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
743*4882a593Smuzhiyun 	val1 = (chip->image[CS4235_LEFT_MASTER] & ~(3 << 5)) | val1;
744*4882a593Smuzhiyun 	val2 = (chip->image[CS4235_RIGHT_MASTER] & ~(3 << 5)) | val2;
745*4882a593Smuzhiyun 	change = val1 != chip->image[CS4235_LEFT_MASTER] || val2 != chip->image[CS4235_RIGHT_MASTER];
746*4882a593Smuzhiyun 	snd_wss_out(chip, CS4235_LEFT_MASTER, val1);
747*4882a593Smuzhiyun 	snd_wss_out(chip, CS4235_RIGHT_MASTER, val2);
748*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
749*4882a593Smuzhiyun 	return change;
750*4882a593Smuzhiyun }
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_7bit, -9450, 150, 0);
753*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
754*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_6bit_12db_max, -8250, 150, 0);
755*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
756*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_5bit_22db_max, -2400, 150, 0);
757*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_4bit, -4500, 300, 0);
758*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_2bit, -1800, 600, 0);
759*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_cs4236_controls[] = {
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun CS4236_DOUBLE("Master Digital Playback Switch", 0,
764*4882a593Smuzhiyun 		CS4236_LEFT_MASTER, CS4236_RIGHT_MASTER, 7, 7, 1, 1),
765*4882a593Smuzhiyun CS4236_DOUBLE("Master Digital Capture Switch", 0,
766*4882a593Smuzhiyun 		CS4236_DAC_MUTE, CS4236_DAC_MUTE, 7, 6, 1, 1),
767*4882a593Smuzhiyun CS4236_MASTER_DIGITAL("Master Digital Volume", 0, db_scale_7bit),
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun CS4236_DOUBLE_TLV("Capture Boost Volume", 0,
770*4882a593Smuzhiyun 		  CS4236_LEFT_MIX_CTRL, CS4236_RIGHT_MIX_CTRL, 5, 5, 3, 1,
771*4882a593Smuzhiyun 		  db_scale_2bit),
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun WSS_DOUBLE("PCM Playback Switch", 0,
774*4882a593Smuzhiyun 		CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
775*4882a593Smuzhiyun WSS_DOUBLE_TLV("PCM Playback Volume", 0,
776*4882a593Smuzhiyun 		CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
777*4882a593Smuzhiyun 		db_scale_6bit),
778*4882a593Smuzhiyun 
779*4882a593Smuzhiyun CS4236_DOUBLE("DSP Playback Switch", 0,
780*4882a593Smuzhiyun 		CS4236_LEFT_DSP, CS4236_RIGHT_DSP, 7, 7, 1, 1),
781*4882a593Smuzhiyun CS4236_DOUBLE_TLV("DSP Playback Volume", 0,
782*4882a593Smuzhiyun 		  CS4236_LEFT_DSP, CS4236_RIGHT_DSP, 0, 0, 63, 1,
783*4882a593Smuzhiyun 		  db_scale_6bit),
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun CS4236_DOUBLE("FM Playback Switch", 0,
786*4882a593Smuzhiyun 		CS4236_LEFT_FM, CS4236_RIGHT_FM, 7, 7, 1, 1),
787*4882a593Smuzhiyun CS4236_DOUBLE_TLV("FM Playback Volume", 0,
788*4882a593Smuzhiyun 		  CS4236_LEFT_FM, CS4236_RIGHT_FM, 0, 0, 63, 1,
789*4882a593Smuzhiyun 		  db_scale_6bit),
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun CS4236_DOUBLE("Wavetable Playback Switch", 0,
792*4882a593Smuzhiyun 		CS4236_LEFT_WAVE, CS4236_RIGHT_WAVE, 7, 7, 1, 1),
793*4882a593Smuzhiyun CS4236_DOUBLE_TLV("Wavetable Playback Volume", 0,
794*4882a593Smuzhiyun 		  CS4236_LEFT_WAVE, CS4236_RIGHT_WAVE, 0, 0, 63, 1,
795*4882a593Smuzhiyun 		  db_scale_6bit_12db_max),
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun WSS_DOUBLE("Synth Playback Switch", 0,
798*4882a593Smuzhiyun 		CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
799*4882a593Smuzhiyun WSS_DOUBLE_TLV("Synth Volume", 0,
800*4882a593Smuzhiyun 		CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1,
801*4882a593Smuzhiyun 		db_scale_5bit_12db_max),
802*4882a593Smuzhiyun WSS_DOUBLE("Synth Capture Switch", 0,
803*4882a593Smuzhiyun 		CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 6, 6, 1, 1),
804*4882a593Smuzhiyun WSS_DOUBLE("Synth Capture Bypass", 0,
805*4882a593Smuzhiyun 		CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 5, 5, 1, 1),
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun CS4236_DOUBLE("Mic Playback Switch", 0,
808*4882a593Smuzhiyun 		CS4236_LEFT_MIC, CS4236_RIGHT_MIC, 6, 6, 1, 1),
809*4882a593Smuzhiyun CS4236_DOUBLE("Mic Capture Switch", 0,
810*4882a593Smuzhiyun 		CS4236_LEFT_MIC, CS4236_RIGHT_MIC, 7, 7, 1, 1),
811*4882a593Smuzhiyun CS4236_DOUBLE_TLV("Mic Volume", 0, CS4236_LEFT_MIC, CS4236_RIGHT_MIC,
812*4882a593Smuzhiyun 		  0, 0, 31, 1, db_scale_5bit_22db_max),
813*4882a593Smuzhiyun CS4236_DOUBLE("Mic Playback Boost (+20dB)", 0,
814*4882a593Smuzhiyun 		CS4236_LEFT_MIC, CS4236_RIGHT_MIC, 5, 5, 1, 0),
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun WSS_DOUBLE("Line Playback Switch", 0,
817*4882a593Smuzhiyun 		CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
818*4882a593Smuzhiyun WSS_DOUBLE_TLV("Line Volume", 0,
819*4882a593Smuzhiyun 		CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
820*4882a593Smuzhiyun 		db_scale_5bit_12db_max),
821*4882a593Smuzhiyun WSS_DOUBLE("Line Capture Switch", 0,
822*4882a593Smuzhiyun 		CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 6, 6, 1, 1),
823*4882a593Smuzhiyun WSS_DOUBLE("Line Capture Bypass", 0,
824*4882a593Smuzhiyun 		CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 5, 5, 1, 1),
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun WSS_DOUBLE("CD Playback Switch", 0,
827*4882a593Smuzhiyun 		CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
828*4882a593Smuzhiyun WSS_DOUBLE_TLV("CD Volume", 0,
829*4882a593Smuzhiyun 		CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
830*4882a593Smuzhiyun 		db_scale_5bit_12db_max),
831*4882a593Smuzhiyun WSS_DOUBLE("CD Capture Switch", 0,
832*4882a593Smuzhiyun 		CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 6, 6, 1, 1),
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun CS4236_DOUBLE1("Mono Output Playback Switch", 0,
835*4882a593Smuzhiyun 		CS4231_MONO_CTRL, CS4236_RIGHT_MIX_CTRL, 6, 7, 1, 1),
836*4882a593Smuzhiyun CS4236_DOUBLE1("Beep Playback Switch", 0,
837*4882a593Smuzhiyun 		CS4231_MONO_CTRL, CS4236_LEFT_MIX_CTRL, 7, 7, 1, 1),
838*4882a593Smuzhiyun WSS_SINGLE_TLV("Beep Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1,
839*4882a593Smuzhiyun 		db_scale_4bit),
840*4882a593Smuzhiyun WSS_SINGLE("Beep Bypass Playback Switch", 0, CS4231_MONO_CTRL, 5, 1, 0),
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,
843*4882a593Smuzhiyun 		0, 0, 15, 0, db_scale_rec_gain),
844*4882a593Smuzhiyun WSS_DOUBLE("Analog Loopback Capture Switch", 0,
845*4882a593Smuzhiyun 		CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 7, 7, 1, 0),
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun WSS_SINGLE("Loopback Digital Playback Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
848*4882a593Smuzhiyun CS4236_DOUBLE1_TLV("Loopback Digital Playback Volume", 0,
849*4882a593Smuzhiyun 		   CS4231_LOOPBACK, CS4236_RIGHT_LOOPBACK, 2, 0, 63, 1,
850*4882a593Smuzhiyun 		   db_scale_6bit),
851*4882a593Smuzhiyun };
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_5bit_6db_max, -5600, 200, 0);
854*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_2bit_16db_max, -2400, 800, 0);
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_cs4235_controls[] = {
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun WSS_DOUBLE("Master Playback Switch", 0,
859*4882a593Smuzhiyun 		CS4235_LEFT_MASTER, CS4235_RIGHT_MASTER, 7, 7, 1, 1),
860*4882a593Smuzhiyun WSS_DOUBLE_TLV("Master Playback Volume", 0,
861*4882a593Smuzhiyun 		CS4235_LEFT_MASTER, CS4235_RIGHT_MASTER, 0, 0, 31, 1,
862*4882a593Smuzhiyun 		db_scale_5bit_6db_max),
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun CS4235_OUTPUT_ACCU("Playback Volume", 0, db_scale_2bit_16db_max),
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun WSS_DOUBLE("Synth Playback Switch", 1,
867*4882a593Smuzhiyun 		CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
868*4882a593Smuzhiyun WSS_DOUBLE("Synth Capture Switch", 1,
869*4882a593Smuzhiyun 		CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 6, 6, 1, 1),
870*4882a593Smuzhiyun WSS_DOUBLE_TLV("Synth Volume", 1,
871*4882a593Smuzhiyun 		CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1,
872*4882a593Smuzhiyun 		db_scale_5bit_12db_max),
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun CS4236_DOUBLE_TLV("Capture Volume", 0,
875*4882a593Smuzhiyun 		  CS4236_LEFT_MIX_CTRL, CS4236_RIGHT_MIX_CTRL, 5, 5, 3, 1,
876*4882a593Smuzhiyun 		  db_scale_2bit),
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun WSS_DOUBLE("PCM Playback Switch", 0,
879*4882a593Smuzhiyun 		CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
880*4882a593Smuzhiyun WSS_DOUBLE("PCM Capture Switch", 0,
881*4882a593Smuzhiyun 		CS4236_DAC_MUTE, CS4236_DAC_MUTE, 7, 6, 1, 1),
882*4882a593Smuzhiyun WSS_DOUBLE_TLV("PCM Volume", 0,
883*4882a593Smuzhiyun 		CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
884*4882a593Smuzhiyun 		db_scale_6bit),
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun CS4236_DOUBLE("DSP Switch", 0, CS4236_LEFT_DSP, CS4236_RIGHT_DSP, 7, 7, 1, 1),
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun CS4236_DOUBLE("FM Switch", 0, CS4236_LEFT_FM, CS4236_RIGHT_FM, 7, 7, 1, 1),
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun CS4236_DOUBLE("Wavetable Switch", 0,
891*4882a593Smuzhiyun 		CS4236_LEFT_WAVE, CS4236_RIGHT_WAVE, 7, 7, 1, 1),
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun CS4236_DOUBLE("Mic Capture Switch", 0,
894*4882a593Smuzhiyun 		CS4236_LEFT_MIC, CS4236_RIGHT_MIC, 7, 7, 1, 1),
895*4882a593Smuzhiyun CS4236_DOUBLE("Mic Playback Switch", 0,
896*4882a593Smuzhiyun 		CS4236_LEFT_MIC, CS4236_RIGHT_MIC, 6, 6, 1, 1),
897*4882a593Smuzhiyun CS4236_SINGLE_TLV("Mic Volume", 0, CS4236_LEFT_MIC, 0, 31, 1,
898*4882a593Smuzhiyun 		  db_scale_5bit_22db_max),
899*4882a593Smuzhiyun CS4236_SINGLE("Mic Boost (+20dB)", 0, CS4236_LEFT_MIC, 5, 1, 0),
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun WSS_DOUBLE("Line Playback Switch", 0,
902*4882a593Smuzhiyun 		CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
903*4882a593Smuzhiyun WSS_DOUBLE("Line Capture Switch", 0,
904*4882a593Smuzhiyun 		CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 6, 6, 1, 1),
905*4882a593Smuzhiyun WSS_DOUBLE_TLV("Line Volume", 0,
906*4882a593Smuzhiyun 		CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
907*4882a593Smuzhiyun 		db_scale_5bit_12db_max),
908*4882a593Smuzhiyun 
909*4882a593Smuzhiyun WSS_DOUBLE("CD Playback Switch", 1,
910*4882a593Smuzhiyun 		CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
911*4882a593Smuzhiyun WSS_DOUBLE("CD Capture Switch", 1,
912*4882a593Smuzhiyun 		CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 6, 6, 1, 1),
913*4882a593Smuzhiyun WSS_DOUBLE_TLV("CD Volume", 1,
914*4882a593Smuzhiyun 		CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
915*4882a593Smuzhiyun 		db_scale_5bit_12db_max),
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun CS4236_DOUBLE1("Beep Playback Switch", 0,
918*4882a593Smuzhiyun 		CS4231_MONO_CTRL, CS4236_LEFT_MIX_CTRL, 7, 7, 1, 1),
919*4882a593Smuzhiyun WSS_SINGLE("Beep Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun WSS_DOUBLE("Analog Loopback Switch", 0,
922*4882a593Smuzhiyun 		CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 7, 7, 1, 0),
923*4882a593Smuzhiyun };
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun #define CS4236_IEC958_ENABLE(xname, xindex) \
926*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
927*4882a593Smuzhiyun   .info = snd_cs4236_info_single, \
928*4882a593Smuzhiyun   .get = snd_cs4236_get_iec958_switch, .put = snd_cs4236_put_iec958_switch, \
929*4882a593Smuzhiyun   .private_value = 1 << 16 }
930*4882a593Smuzhiyun 
snd_cs4236_get_iec958_switch(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)931*4882a593Smuzhiyun static int snd_cs4236_get_iec958_switch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
934*4882a593Smuzhiyun 	unsigned long flags;
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
937*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = chip->image[CS4231_ALT_FEATURE_1] & 0x02 ? 1 : 0;
938*4882a593Smuzhiyun #if 0
939*4882a593Smuzhiyun 	printk(KERN_DEBUG "get valid: ALT = 0x%x, C3 = 0x%x, C4 = 0x%x, "
940*4882a593Smuzhiyun 	       "C5 = 0x%x, C6 = 0x%x, C8 = 0x%x\n",
941*4882a593Smuzhiyun 			snd_wss_in(chip, CS4231_ALT_FEATURE_1),
942*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 3),
943*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 4),
944*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 5),
945*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 6),
946*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 8));
947*4882a593Smuzhiyun #endif
948*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
949*4882a593Smuzhiyun 	return 0;
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun 
snd_cs4236_put_iec958_switch(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)952*4882a593Smuzhiyun static int snd_cs4236_put_iec958_switch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
953*4882a593Smuzhiyun {
954*4882a593Smuzhiyun 	struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
955*4882a593Smuzhiyun 	unsigned long flags;
956*4882a593Smuzhiyun 	int change;
957*4882a593Smuzhiyun 	unsigned short enable, val;
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	enable = ucontrol->value.integer.value[0] & 1;
960*4882a593Smuzhiyun 
961*4882a593Smuzhiyun 	mutex_lock(&chip->mce_mutex);
962*4882a593Smuzhiyun 	snd_wss_mce_up(chip);
963*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->reg_lock, flags);
964*4882a593Smuzhiyun 	val = (chip->image[CS4231_ALT_FEATURE_1] & ~0x0e) | (0<<2) | (enable << 1);
965*4882a593Smuzhiyun 	change = val != chip->image[CS4231_ALT_FEATURE_1];
966*4882a593Smuzhiyun 	snd_wss_out(chip, CS4231_ALT_FEATURE_1, val);
967*4882a593Smuzhiyun 	val = snd_cs4236_ctrl_in(chip, 4) | 0xc0;
968*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 4, val);
969*4882a593Smuzhiyun 	udelay(100);
970*4882a593Smuzhiyun 	val &= ~0x40;
971*4882a593Smuzhiyun 	snd_cs4236_ctrl_out(chip, 4, val);
972*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->reg_lock, flags);
973*4882a593Smuzhiyun 	snd_wss_mce_down(chip);
974*4882a593Smuzhiyun 	mutex_unlock(&chip->mce_mutex);
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun #if 0
977*4882a593Smuzhiyun 	printk(KERN_DEBUG "set valid: ALT = 0x%x, C3 = 0x%x, C4 = 0x%x, "
978*4882a593Smuzhiyun 	       "C5 = 0x%x, C6 = 0x%x, C8 = 0x%x\n",
979*4882a593Smuzhiyun 			snd_wss_in(chip, CS4231_ALT_FEATURE_1),
980*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 3),
981*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 4),
982*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 5),
983*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 6),
984*4882a593Smuzhiyun 			snd_cs4236_ctrl_in(chip, 8));
985*4882a593Smuzhiyun #endif
986*4882a593Smuzhiyun 	return change;
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_cs4236_iec958_controls[] = {
990*4882a593Smuzhiyun CS4236_IEC958_ENABLE("IEC958 Output Enable", 0),
991*4882a593Smuzhiyun CS4236_SINGLEC("IEC958 Output Validity", 0, 4, 4, 1, 0),
992*4882a593Smuzhiyun CS4236_SINGLEC("IEC958 Output User", 0, 4, 5, 1, 0),
993*4882a593Smuzhiyun CS4236_SINGLEC("IEC958 Output CSBR", 0, 4, 6, 1, 0),
994*4882a593Smuzhiyun CS4236_SINGLEC("IEC958 Output Channel Status Low", 0, 5, 1, 127, 0),
995*4882a593Smuzhiyun CS4236_SINGLEC("IEC958 Output Channel Status High", 0, 6, 0, 255, 0)
996*4882a593Smuzhiyun };
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_cs4236_3d_controls_cs4235[] = {
999*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Switch", 0, 3, 4, 1, 0),
1000*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Space", 0, 2, 4, 15, 1)
1001*4882a593Smuzhiyun };
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_cs4236_3d_controls_cs4237[] = {
1004*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Switch", 0, 3, 7, 1, 0),
1005*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Space", 0, 2, 4, 15, 1),
1006*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Center", 0, 2, 0, 15, 1),
1007*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Mono", 0, 3, 6, 1, 0),
1008*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - IEC958", 0, 3, 5, 1, 0)
1009*4882a593Smuzhiyun };
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_cs4236_3d_controls_cs4238[] = {
1012*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Switch", 0, 3, 4, 1, 0),
1013*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Space", 0, 2, 4, 15, 1),
1014*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - Volume", 0, 2, 0, 15, 1),
1015*4882a593Smuzhiyun CS4236_SINGLEC("3D Control - IEC958", 0, 3, 5, 1, 0)
1016*4882a593Smuzhiyun };
1017*4882a593Smuzhiyun 
snd_cs4236_mixer(struct snd_wss * chip)1018*4882a593Smuzhiyun int snd_cs4236_mixer(struct snd_wss *chip)
1019*4882a593Smuzhiyun {
1020*4882a593Smuzhiyun 	struct snd_card *card;
1021*4882a593Smuzhiyun 	unsigned int idx, count;
1022*4882a593Smuzhiyun 	int err;
1023*4882a593Smuzhiyun 	const struct snd_kcontrol_new *kcontrol;
1024*4882a593Smuzhiyun 
1025*4882a593Smuzhiyun 	if (snd_BUG_ON(!chip || !chip->card))
1026*4882a593Smuzhiyun 		return -EINVAL;
1027*4882a593Smuzhiyun 	card = chip->card;
1028*4882a593Smuzhiyun 	strcpy(card->mixername, snd_wss_chip_id(chip));
1029*4882a593Smuzhiyun 
1030*4882a593Smuzhiyun 	if (chip->hardware == WSS_HW_CS4235 ||
1031*4882a593Smuzhiyun 	    chip->hardware == WSS_HW_CS4239) {
1032*4882a593Smuzhiyun 		for (idx = 0; idx < ARRAY_SIZE(snd_cs4235_controls); idx++) {
1033*4882a593Smuzhiyun 			if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4235_controls[idx], chip))) < 0)
1034*4882a593Smuzhiyun 				return err;
1035*4882a593Smuzhiyun 		}
1036*4882a593Smuzhiyun 	} else {
1037*4882a593Smuzhiyun 		for (idx = 0; idx < ARRAY_SIZE(snd_cs4236_controls); idx++) {
1038*4882a593Smuzhiyun 			if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4236_controls[idx], chip))) < 0)
1039*4882a593Smuzhiyun 				return err;
1040*4882a593Smuzhiyun 		}
1041*4882a593Smuzhiyun 	}
1042*4882a593Smuzhiyun 	switch (chip->hardware) {
1043*4882a593Smuzhiyun 	case WSS_HW_CS4235:
1044*4882a593Smuzhiyun 	case WSS_HW_CS4239:
1045*4882a593Smuzhiyun 		count = ARRAY_SIZE(snd_cs4236_3d_controls_cs4235);
1046*4882a593Smuzhiyun 		kcontrol = snd_cs4236_3d_controls_cs4235;
1047*4882a593Smuzhiyun 		break;
1048*4882a593Smuzhiyun 	case WSS_HW_CS4237B:
1049*4882a593Smuzhiyun 		count = ARRAY_SIZE(snd_cs4236_3d_controls_cs4237);
1050*4882a593Smuzhiyun 		kcontrol = snd_cs4236_3d_controls_cs4237;
1051*4882a593Smuzhiyun 		break;
1052*4882a593Smuzhiyun 	case WSS_HW_CS4238B:
1053*4882a593Smuzhiyun 		count = ARRAY_SIZE(snd_cs4236_3d_controls_cs4238);
1054*4882a593Smuzhiyun 		kcontrol = snd_cs4236_3d_controls_cs4238;
1055*4882a593Smuzhiyun 		break;
1056*4882a593Smuzhiyun 	default:
1057*4882a593Smuzhiyun 		count = 0;
1058*4882a593Smuzhiyun 		kcontrol = NULL;
1059*4882a593Smuzhiyun 	}
1060*4882a593Smuzhiyun 	for (idx = 0; idx < count; idx++, kcontrol++) {
1061*4882a593Smuzhiyun 		if ((err = snd_ctl_add(card, snd_ctl_new1(kcontrol, chip))) < 0)
1062*4882a593Smuzhiyun 			return err;
1063*4882a593Smuzhiyun 	}
1064*4882a593Smuzhiyun 	if (chip->hardware == WSS_HW_CS4237B ||
1065*4882a593Smuzhiyun 	    chip->hardware == WSS_HW_CS4238B) {
1066*4882a593Smuzhiyun 		for (idx = 0; idx < ARRAY_SIZE(snd_cs4236_iec958_controls); idx++) {
1067*4882a593Smuzhiyun 			if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4236_iec958_controls[idx], chip))) < 0)
1068*4882a593Smuzhiyun 				return err;
1069*4882a593Smuzhiyun 		}
1070*4882a593Smuzhiyun 	}
1071*4882a593Smuzhiyun 	return 0;
1072*4882a593Smuzhiyun }
1073