xref: /OK3568_Linux_fs/kernel/sound/isa/ad1816a/ad1816a_lib.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun     ad1816a.c - lowlevel code for Analog Devices AD1816A chip.
4*4882a593Smuzhiyun     Copyright (C) 1999-2000 by Massimo Piccioni <dafastidio@libero.it>
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/ioport.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <sound/core.h>
15*4882a593Smuzhiyun #include <sound/tlv.h>
16*4882a593Smuzhiyun #include <sound/ad1816a.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <asm/dma.h>
19*4882a593Smuzhiyun 
snd_ad1816a_busy_wait(struct snd_ad1816a * chip)20*4882a593Smuzhiyun static inline int snd_ad1816a_busy_wait(struct snd_ad1816a *chip)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun 	int timeout;
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun 	for (timeout = 1000; timeout-- > 0; udelay(10))
25*4882a593Smuzhiyun 		if (inb(AD1816A_REG(AD1816A_CHIP_STATUS)) & AD1816A_READY)
26*4882a593Smuzhiyun 			return 0;
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun 	snd_printk(KERN_WARNING "chip busy.\n");
29*4882a593Smuzhiyun 	return -EBUSY;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun 
snd_ad1816a_in(struct snd_ad1816a * chip,unsigned char reg)32*4882a593Smuzhiyun static inline unsigned char snd_ad1816a_in(struct snd_ad1816a *chip, unsigned char reg)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	snd_ad1816a_busy_wait(chip);
35*4882a593Smuzhiyun 	return inb(AD1816A_REG(reg));
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun 
snd_ad1816a_out(struct snd_ad1816a * chip,unsigned char reg,unsigned char value)38*4882a593Smuzhiyun static inline void snd_ad1816a_out(struct snd_ad1816a *chip, unsigned char reg,
39*4882a593Smuzhiyun 			    unsigned char value)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	snd_ad1816a_busy_wait(chip);
42*4882a593Smuzhiyun 	outb(value, AD1816A_REG(reg));
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
snd_ad1816a_out_mask(struct snd_ad1816a * chip,unsigned char reg,unsigned char mask,unsigned char value)45*4882a593Smuzhiyun static inline void snd_ad1816a_out_mask(struct snd_ad1816a *chip, unsigned char reg,
46*4882a593Smuzhiyun 				 unsigned char mask, unsigned char value)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	snd_ad1816a_out(chip, reg,
49*4882a593Smuzhiyun 		(value & mask) | (snd_ad1816a_in(chip, reg) & ~mask));
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun 
snd_ad1816a_read(struct snd_ad1816a * chip,unsigned char reg)52*4882a593Smuzhiyun static unsigned short snd_ad1816a_read(struct snd_ad1816a *chip, unsigned char reg)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun 	snd_ad1816a_out(chip, AD1816A_INDIR_ADDR, reg & 0x3f);
55*4882a593Smuzhiyun 	return snd_ad1816a_in(chip, AD1816A_INDIR_DATA_LOW) |
56*4882a593Smuzhiyun 		(snd_ad1816a_in(chip, AD1816A_INDIR_DATA_HIGH) << 8);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
snd_ad1816a_write(struct snd_ad1816a * chip,unsigned char reg,unsigned short value)59*4882a593Smuzhiyun static void snd_ad1816a_write(struct snd_ad1816a *chip, unsigned char reg,
60*4882a593Smuzhiyun 			      unsigned short value)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	snd_ad1816a_out(chip, AD1816A_INDIR_ADDR, reg & 0x3f);
63*4882a593Smuzhiyun 	snd_ad1816a_out(chip, AD1816A_INDIR_DATA_LOW, value & 0xff);
64*4882a593Smuzhiyun 	snd_ad1816a_out(chip, AD1816A_INDIR_DATA_HIGH, (value >> 8) & 0xff);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun 
snd_ad1816a_write_mask(struct snd_ad1816a * chip,unsigned char reg,unsigned short mask,unsigned short value)67*4882a593Smuzhiyun static void snd_ad1816a_write_mask(struct snd_ad1816a *chip, unsigned char reg,
68*4882a593Smuzhiyun 				   unsigned short mask, unsigned short value)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun 	snd_ad1816a_write(chip, reg,
71*4882a593Smuzhiyun 		(value & mask) | (snd_ad1816a_read(chip, reg) & ~mask));
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 
snd_ad1816a_get_format(struct snd_ad1816a * chip,snd_pcm_format_t format,int channels)75*4882a593Smuzhiyun static unsigned char snd_ad1816a_get_format(struct snd_ad1816a *chip,
76*4882a593Smuzhiyun 					    snd_pcm_format_t format,
77*4882a593Smuzhiyun 					    int channels)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun 	unsigned char retval = AD1816A_FMT_LINEAR_8;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	switch (format) {
82*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_MU_LAW:
83*4882a593Smuzhiyun 		retval = AD1816A_FMT_ULAW_8;
84*4882a593Smuzhiyun 		break;
85*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_A_LAW:
86*4882a593Smuzhiyun 		retval = AD1816A_FMT_ALAW_8;
87*4882a593Smuzhiyun 		break;
88*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S16_LE:
89*4882a593Smuzhiyun 		retval = AD1816A_FMT_LINEAR_16_LIT;
90*4882a593Smuzhiyun 		break;
91*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S16_BE:
92*4882a593Smuzhiyun 		retval = AD1816A_FMT_LINEAR_16_BIG;
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun 	return (channels > 1) ? (retval | AD1816A_FMT_STEREO) : retval;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
snd_ad1816a_open(struct snd_ad1816a * chip,unsigned int mode)97*4882a593Smuzhiyun static int snd_ad1816a_open(struct snd_ad1816a *chip, unsigned int mode)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	unsigned long flags;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	if (chip->mode & mode) {
104*4882a593Smuzhiyun 		spin_unlock_irqrestore(&chip->lock, flags);
105*4882a593Smuzhiyun 		return -EAGAIN;
106*4882a593Smuzhiyun 	}
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	switch ((mode &= AD1816A_MODE_OPEN)) {
109*4882a593Smuzhiyun 	case AD1816A_MODE_PLAYBACK:
110*4882a593Smuzhiyun 		snd_ad1816a_out_mask(chip, AD1816A_INTERRUPT_STATUS,
111*4882a593Smuzhiyun 			AD1816A_PLAYBACK_IRQ_PENDING, 0x00);
112*4882a593Smuzhiyun 		snd_ad1816a_write_mask(chip, AD1816A_INTERRUPT_ENABLE,
113*4882a593Smuzhiyun 			AD1816A_PLAYBACK_IRQ_ENABLE, 0xffff);
114*4882a593Smuzhiyun 		break;
115*4882a593Smuzhiyun 	case AD1816A_MODE_CAPTURE:
116*4882a593Smuzhiyun 		snd_ad1816a_out_mask(chip, AD1816A_INTERRUPT_STATUS,
117*4882a593Smuzhiyun 			AD1816A_CAPTURE_IRQ_PENDING, 0x00);
118*4882a593Smuzhiyun 		snd_ad1816a_write_mask(chip, AD1816A_INTERRUPT_ENABLE,
119*4882a593Smuzhiyun 			AD1816A_CAPTURE_IRQ_ENABLE, 0xffff);
120*4882a593Smuzhiyun 		break;
121*4882a593Smuzhiyun 	case AD1816A_MODE_TIMER:
122*4882a593Smuzhiyun 		snd_ad1816a_out_mask(chip, AD1816A_INTERRUPT_STATUS,
123*4882a593Smuzhiyun 			AD1816A_TIMER_IRQ_PENDING, 0x00);
124*4882a593Smuzhiyun 		snd_ad1816a_write_mask(chip, AD1816A_INTERRUPT_ENABLE,
125*4882a593Smuzhiyun 			AD1816A_TIMER_IRQ_ENABLE, 0xffff);
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun 	chip->mode |= mode;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
snd_ad1816a_close(struct snd_ad1816a * chip,unsigned int mode)133*4882a593Smuzhiyun static void snd_ad1816a_close(struct snd_ad1816a *chip, unsigned int mode)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	unsigned long flags;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	switch ((mode &= AD1816A_MODE_OPEN)) {
140*4882a593Smuzhiyun 	case AD1816A_MODE_PLAYBACK:
141*4882a593Smuzhiyun 		snd_ad1816a_out_mask(chip, AD1816A_INTERRUPT_STATUS,
142*4882a593Smuzhiyun 			AD1816A_PLAYBACK_IRQ_PENDING, 0x00);
143*4882a593Smuzhiyun 		snd_ad1816a_write_mask(chip, AD1816A_INTERRUPT_ENABLE,
144*4882a593Smuzhiyun 			AD1816A_PLAYBACK_IRQ_ENABLE, 0x0000);
145*4882a593Smuzhiyun 		break;
146*4882a593Smuzhiyun 	case AD1816A_MODE_CAPTURE:
147*4882a593Smuzhiyun 		snd_ad1816a_out_mask(chip, AD1816A_INTERRUPT_STATUS,
148*4882a593Smuzhiyun 			AD1816A_CAPTURE_IRQ_PENDING, 0x00);
149*4882a593Smuzhiyun 		snd_ad1816a_write_mask(chip, AD1816A_INTERRUPT_ENABLE,
150*4882a593Smuzhiyun 			AD1816A_CAPTURE_IRQ_ENABLE, 0x0000);
151*4882a593Smuzhiyun 		break;
152*4882a593Smuzhiyun 	case AD1816A_MODE_TIMER:
153*4882a593Smuzhiyun 		snd_ad1816a_out_mask(chip, AD1816A_INTERRUPT_STATUS,
154*4882a593Smuzhiyun 			AD1816A_TIMER_IRQ_PENDING, 0x00);
155*4882a593Smuzhiyun 		snd_ad1816a_write_mask(chip, AD1816A_INTERRUPT_ENABLE,
156*4882a593Smuzhiyun 			AD1816A_TIMER_IRQ_ENABLE, 0x0000);
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun 	if (!((chip->mode &= ~mode) & AD1816A_MODE_OPEN))
159*4882a593Smuzhiyun 		chip->mode = 0;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 
snd_ad1816a_trigger(struct snd_ad1816a * chip,unsigned char what,int channel,int cmd,int iscapture)165*4882a593Smuzhiyun static int snd_ad1816a_trigger(struct snd_ad1816a *chip, unsigned char what,
166*4882a593Smuzhiyun 			       int channel, int cmd, int iscapture)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	int error = 0;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	switch (cmd) {
171*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
172*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
173*4882a593Smuzhiyun 		spin_lock(&chip->lock);
174*4882a593Smuzhiyun 		cmd = (cmd == SNDRV_PCM_TRIGGER_START) ? 0xff: 0x00;
175*4882a593Smuzhiyun 		/* if (what & AD1816A_PLAYBACK_ENABLE) */
176*4882a593Smuzhiyun 		/* That is not valid, because playback and capture enable
177*4882a593Smuzhiyun 		 * are the same bit pattern, just to different addresses
178*4882a593Smuzhiyun 		 */
179*4882a593Smuzhiyun 		if (! iscapture)
180*4882a593Smuzhiyun 			snd_ad1816a_out_mask(chip, AD1816A_PLAYBACK_CONFIG,
181*4882a593Smuzhiyun 				AD1816A_PLAYBACK_ENABLE, cmd);
182*4882a593Smuzhiyun 		else
183*4882a593Smuzhiyun 			snd_ad1816a_out_mask(chip, AD1816A_CAPTURE_CONFIG,
184*4882a593Smuzhiyun 				AD1816A_CAPTURE_ENABLE, cmd);
185*4882a593Smuzhiyun 		spin_unlock(&chip->lock);
186*4882a593Smuzhiyun 		break;
187*4882a593Smuzhiyun 	default:
188*4882a593Smuzhiyun 		snd_printk(KERN_WARNING "invalid trigger mode 0x%x.\n", what);
189*4882a593Smuzhiyun 		error = -EINVAL;
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	return error;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
snd_ad1816a_playback_trigger(struct snd_pcm_substream * substream,int cmd)195*4882a593Smuzhiyun static int snd_ad1816a_playback_trigger(struct snd_pcm_substream *substream, int cmd)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
198*4882a593Smuzhiyun 	return snd_ad1816a_trigger(chip, AD1816A_PLAYBACK_ENABLE,
199*4882a593Smuzhiyun 				   SNDRV_PCM_STREAM_PLAYBACK, cmd, 0);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
snd_ad1816a_capture_trigger(struct snd_pcm_substream * substream,int cmd)202*4882a593Smuzhiyun static int snd_ad1816a_capture_trigger(struct snd_pcm_substream *substream, int cmd)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
205*4882a593Smuzhiyun 	return snd_ad1816a_trigger(chip, AD1816A_CAPTURE_ENABLE,
206*4882a593Smuzhiyun 				   SNDRV_PCM_STREAM_CAPTURE, cmd, 1);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
snd_ad1816a_playback_prepare(struct snd_pcm_substream * substream)209*4882a593Smuzhiyun static int snd_ad1816a_playback_prepare(struct snd_pcm_substream *substream)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
212*4882a593Smuzhiyun 	unsigned long flags;
213*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
214*4882a593Smuzhiyun 	unsigned int size, rate;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	chip->p_dma_size = size = snd_pcm_lib_buffer_bytes(substream);
219*4882a593Smuzhiyun 	snd_ad1816a_out_mask(chip, AD1816A_PLAYBACK_CONFIG,
220*4882a593Smuzhiyun 		AD1816A_PLAYBACK_ENABLE | AD1816A_PLAYBACK_PIO, 0x00);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	snd_dma_program(chip->dma1, runtime->dma_addr, size,
223*4882a593Smuzhiyun 			DMA_MODE_WRITE | DMA_AUTOINIT);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	rate = runtime->rate;
226*4882a593Smuzhiyun 	if (chip->clock_freq)
227*4882a593Smuzhiyun 		rate = (rate * 33000) / chip->clock_freq;
228*4882a593Smuzhiyun 	snd_ad1816a_write(chip, AD1816A_PLAYBACK_SAMPLE_RATE, rate);
229*4882a593Smuzhiyun 	snd_ad1816a_out_mask(chip, AD1816A_PLAYBACK_CONFIG,
230*4882a593Smuzhiyun 		AD1816A_FMT_ALL | AD1816A_FMT_STEREO,
231*4882a593Smuzhiyun 		snd_ad1816a_get_format(chip, runtime->format,
232*4882a593Smuzhiyun 			runtime->channels));
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	snd_ad1816a_write(chip, AD1816A_PLAYBACK_BASE_COUNT,
235*4882a593Smuzhiyun 		snd_pcm_lib_period_bytes(substream) / 4 - 1);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
238*4882a593Smuzhiyun 	return 0;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
snd_ad1816a_capture_prepare(struct snd_pcm_substream * substream)241*4882a593Smuzhiyun static int snd_ad1816a_capture_prepare(struct snd_pcm_substream *substream)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
244*4882a593Smuzhiyun 	unsigned long flags;
245*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
246*4882a593Smuzhiyun 	unsigned int size, rate;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	chip->c_dma_size = size = snd_pcm_lib_buffer_bytes(substream);
251*4882a593Smuzhiyun 	snd_ad1816a_out_mask(chip, AD1816A_CAPTURE_CONFIG,
252*4882a593Smuzhiyun 		AD1816A_CAPTURE_ENABLE | AD1816A_CAPTURE_PIO, 0x00);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	snd_dma_program(chip->dma2, runtime->dma_addr, size,
255*4882a593Smuzhiyun 			DMA_MODE_READ | DMA_AUTOINIT);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	rate = runtime->rate;
258*4882a593Smuzhiyun 	if (chip->clock_freq)
259*4882a593Smuzhiyun 		rate = (rate * 33000) / chip->clock_freq;
260*4882a593Smuzhiyun 	snd_ad1816a_write(chip, AD1816A_CAPTURE_SAMPLE_RATE, rate);
261*4882a593Smuzhiyun 	snd_ad1816a_out_mask(chip, AD1816A_CAPTURE_CONFIG,
262*4882a593Smuzhiyun 		AD1816A_FMT_ALL | AD1816A_FMT_STEREO,
263*4882a593Smuzhiyun 		snd_ad1816a_get_format(chip, runtime->format,
264*4882a593Smuzhiyun 			runtime->channels));
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	snd_ad1816a_write(chip, AD1816A_CAPTURE_BASE_COUNT,
267*4882a593Smuzhiyun 		snd_pcm_lib_period_bytes(substream) / 4 - 1);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
270*4882a593Smuzhiyun 	return 0;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 
snd_ad1816a_playback_pointer(struct snd_pcm_substream * substream)274*4882a593Smuzhiyun static snd_pcm_uframes_t snd_ad1816a_playback_pointer(struct snd_pcm_substream *substream)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
277*4882a593Smuzhiyun 	size_t ptr;
278*4882a593Smuzhiyun 	if (!(chip->mode & AD1816A_MODE_PLAYBACK))
279*4882a593Smuzhiyun 		return 0;
280*4882a593Smuzhiyun 	ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
281*4882a593Smuzhiyun 	return bytes_to_frames(substream->runtime, ptr);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
snd_ad1816a_capture_pointer(struct snd_pcm_substream * substream)284*4882a593Smuzhiyun static snd_pcm_uframes_t snd_ad1816a_capture_pointer(struct snd_pcm_substream *substream)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
287*4882a593Smuzhiyun 	size_t ptr;
288*4882a593Smuzhiyun 	if (!(chip->mode & AD1816A_MODE_CAPTURE))
289*4882a593Smuzhiyun 		return 0;
290*4882a593Smuzhiyun 	ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
291*4882a593Smuzhiyun 	return bytes_to_frames(substream->runtime, ptr);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 
snd_ad1816a_interrupt(int irq,void * dev_id)295*4882a593Smuzhiyun static irqreturn_t snd_ad1816a_interrupt(int irq, void *dev_id)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun 	struct snd_ad1816a *chip = dev_id;
298*4882a593Smuzhiyun 	unsigned char status;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	spin_lock(&chip->lock);
301*4882a593Smuzhiyun 	status = snd_ad1816a_in(chip, AD1816A_INTERRUPT_STATUS);
302*4882a593Smuzhiyun 	spin_unlock(&chip->lock);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	if ((status & AD1816A_PLAYBACK_IRQ_PENDING) && chip->playback_substream)
305*4882a593Smuzhiyun 		snd_pcm_period_elapsed(chip->playback_substream);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	if ((status & AD1816A_CAPTURE_IRQ_PENDING) && chip->capture_substream)
308*4882a593Smuzhiyun 		snd_pcm_period_elapsed(chip->capture_substream);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	if ((status & AD1816A_TIMER_IRQ_PENDING) && chip->timer)
311*4882a593Smuzhiyun 		snd_timer_interrupt(chip->timer, chip->timer->sticks);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	spin_lock(&chip->lock);
314*4882a593Smuzhiyun 	snd_ad1816a_out(chip, AD1816A_INTERRUPT_STATUS, 0x00);
315*4882a593Smuzhiyun 	spin_unlock(&chip->lock);
316*4882a593Smuzhiyun 	return IRQ_HANDLED;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ad1816a_playback = {
321*4882a593Smuzhiyun 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
322*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_MMAP_VALID),
323*4882a593Smuzhiyun 	.formats =		(SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
324*4882a593Smuzhiyun 				 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
325*4882a593Smuzhiyun 				 SNDRV_PCM_FMTBIT_S16_BE),
326*4882a593Smuzhiyun 	.rates =		SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
327*4882a593Smuzhiyun 	.rate_min =		4000,
328*4882a593Smuzhiyun 	.rate_max =		55200,
329*4882a593Smuzhiyun 	.channels_min =		1,
330*4882a593Smuzhiyun 	.channels_max =		2,
331*4882a593Smuzhiyun 	.buffer_bytes_max =	(128*1024),
332*4882a593Smuzhiyun 	.period_bytes_min =	64,
333*4882a593Smuzhiyun 	.period_bytes_max =	(128*1024),
334*4882a593Smuzhiyun 	.periods_min =		1,
335*4882a593Smuzhiyun 	.periods_max =		1024,
336*4882a593Smuzhiyun 	.fifo_size =		0,
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun static const struct snd_pcm_hardware snd_ad1816a_capture = {
340*4882a593Smuzhiyun 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
341*4882a593Smuzhiyun 				 SNDRV_PCM_INFO_MMAP_VALID),
342*4882a593Smuzhiyun 	.formats =		(SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
343*4882a593Smuzhiyun 				 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
344*4882a593Smuzhiyun 				 SNDRV_PCM_FMTBIT_S16_BE),
345*4882a593Smuzhiyun 	.rates =		SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
346*4882a593Smuzhiyun 	.rate_min =		4000,
347*4882a593Smuzhiyun 	.rate_max =		55200,
348*4882a593Smuzhiyun 	.channels_min =		1,
349*4882a593Smuzhiyun 	.channels_max =		2,
350*4882a593Smuzhiyun 	.buffer_bytes_max =	(128*1024),
351*4882a593Smuzhiyun 	.period_bytes_min =	64,
352*4882a593Smuzhiyun 	.period_bytes_max =	(128*1024),
353*4882a593Smuzhiyun 	.periods_min =		1,
354*4882a593Smuzhiyun 	.periods_max =		1024,
355*4882a593Smuzhiyun 	.fifo_size =		0,
356*4882a593Smuzhiyun };
357*4882a593Smuzhiyun 
snd_ad1816a_timer_close(struct snd_timer * timer)358*4882a593Smuzhiyun static int snd_ad1816a_timer_close(struct snd_timer *timer)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_timer_chip(timer);
361*4882a593Smuzhiyun 	snd_ad1816a_close(chip, AD1816A_MODE_TIMER);
362*4882a593Smuzhiyun 	return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun 
snd_ad1816a_timer_open(struct snd_timer * timer)365*4882a593Smuzhiyun static int snd_ad1816a_timer_open(struct snd_timer *timer)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_timer_chip(timer);
368*4882a593Smuzhiyun 	snd_ad1816a_open(chip, AD1816A_MODE_TIMER);
369*4882a593Smuzhiyun 	return 0;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun 
snd_ad1816a_timer_resolution(struct snd_timer * timer)372*4882a593Smuzhiyun static unsigned long snd_ad1816a_timer_resolution(struct snd_timer *timer)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun 	if (snd_BUG_ON(!timer))
375*4882a593Smuzhiyun 		return 0;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	return 10000;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun 
snd_ad1816a_timer_start(struct snd_timer * timer)380*4882a593Smuzhiyun static int snd_ad1816a_timer_start(struct snd_timer *timer)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	unsigned short bits;
383*4882a593Smuzhiyun 	unsigned long flags;
384*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_timer_chip(timer);
385*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
386*4882a593Smuzhiyun 	bits = snd_ad1816a_read(chip, AD1816A_INTERRUPT_ENABLE);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	if (!(bits & AD1816A_TIMER_ENABLE)) {
389*4882a593Smuzhiyun 		snd_ad1816a_write(chip, AD1816A_TIMER_BASE_COUNT,
390*4882a593Smuzhiyun 			timer->sticks & 0xffff);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 		snd_ad1816a_write_mask(chip, AD1816A_INTERRUPT_ENABLE,
393*4882a593Smuzhiyun 			AD1816A_TIMER_ENABLE, 0xffff);
394*4882a593Smuzhiyun 	}
395*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
396*4882a593Smuzhiyun 	return 0;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun 
snd_ad1816a_timer_stop(struct snd_timer * timer)399*4882a593Smuzhiyun static int snd_ad1816a_timer_stop(struct snd_timer *timer)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun 	unsigned long flags;
402*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_timer_chip(timer);
403*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	snd_ad1816a_write_mask(chip, AD1816A_INTERRUPT_ENABLE,
406*4882a593Smuzhiyun 		AD1816A_TIMER_ENABLE, 0x0000);
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
409*4882a593Smuzhiyun 	return 0;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun static const struct snd_timer_hardware snd_ad1816a_timer_table = {
413*4882a593Smuzhiyun 	.flags =	SNDRV_TIMER_HW_AUTO,
414*4882a593Smuzhiyun 	.resolution =	10000,
415*4882a593Smuzhiyun 	.ticks =	65535,
416*4882a593Smuzhiyun 	.open =		snd_ad1816a_timer_open,
417*4882a593Smuzhiyun 	.close =	snd_ad1816a_timer_close,
418*4882a593Smuzhiyun 	.c_resolution =	snd_ad1816a_timer_resolution,
419*4882a593Smuzhiyun 	.start =	snd_ad1816a_timer_start,
420*4882a593Smuzhiyun 	.stop =		snd_ad1816a_timer_stop,
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun 
snd_ad1816a_playback_open(struct snd_pcm_substream * substream)423*4882a593Smuzhiyun static int snd_ad1816a_playback_open(struct snd_pcm_substream *substream)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
426*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
427*4882a593Smuzhiyun 	int error;
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	if ((error = snd_ad1816a_open(chip, AD1816A_MODE_PLAYBACK)) < 0)
430*4882a593Smuzhiyun 		return error;
431*4882a593Smuzhiyun 	runtime->hw = snd_ad1816a_playback;
432*4882a593Smuzhiyun 	snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
433*4882a593Smuzhiyun 	snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
434*4882a593Smuzhiyun 	chip->playback_substream = substream;
435*4882a593Smuzhiyun 	return 0;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun 
snd_ad1816a_capture_open(struct snd_pcm_substream * substream)438*4882a593Smuzhiyun static int snd_ad1816a_capture_open(struct snd_pcm_substream *substream)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
441*4882a593Smuzhiyun 	struct snd_pcm_runtime *runtime = substream->runtime;
442*4882a593Smuzhiyun 	int error;
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	if ((error = snd_ad1816a_open(chip, AD1816A_MODE_CAPTURE)) < 0)
445*4882a593Smuzhiyun 		return error;
446*4882a593Smuzhiyun 	runtime->hw = snd_ad1816a_capture;
447*4882a593Smuzhiyun 	snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
448*4882a593Smuzhiyun 	snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
449*4882a593Smuzhiyun 	chip->capture_substream = substream;
450*4882a593Smuzhiyun 	return 0;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun 
snd_ad1816a_playback_close(struct snd_pcm_substream * substream)453*4882a593Smuzhiyun static int snd_ad1816a_playback_close(struct snd_pcm_substream *substream)
454*4882a593Smuzhiyun {
455*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	chip->playback_substream = NULL;
458*4882a593Smuzhiyun 	snd_ad1816a_close(chip, AD1816A_MODE_PLAYBACK);
459*4882a593Smuzhiyun 	return 0;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun 
snd_ad1816a_capture_close(struct snd_pcm_substream * substream)462*4882a593Smuzhiyun static int snd_ad1816a_capture_close(struct snd_pcm_substream *substream)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_pcm_substream_chip(substream);
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	chip->capture_substream = NULL;
467*4882a593Smuzhiyun 	snd_ad1816a_close(chip, AD1816A_MODE_CAPTURE);
468*4882a593Smuzhiyun 	return 0;
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 
snd_ad1816a_init(struct snd_ad1816a * chip)472*4882a593Smuzhiyun static void snd_ad1816a_init(struct snd_ad1816a *chip)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun 	unsigned long flags;
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	snd_ad1816a_out(chip, AD1816A_INTERRUPT_STATUS, 0x00);
479*4882a593Smuzhiyun 	snd_ad1816a_out_mask(chip, AD1816A_PLAYBACK_CONFIG,
480*4882a593Smuzhiyun 		AD1816A_PLAYBACK_ENABLE | AD1816A_PLAYBACK_PIO, 0x00);
481*4882a593Smuzhiyun 	snd_ad1816a_out_mask(chip, AD1816A_CAPTURE_CONFIG,
482*4882a593Smuzhiyun 		AD1816A_CAPTURE_ENABLE | AD1816A_CAPTURE_PIO, 0x00);
483*4882a593Smuzhiyun 	snd_ad1816a_write(chip, AD1816A_INTERRUPT_ENABLE, 0x0000);
484*4882a593Smuzhiyun 	snd_ad1816a_write_mask(chip, AD1816A_CHIP_CONFIG,
485*4882a593Smuzhiyun 		AD1816A_CAPTURE_NOT_EQUAL | AD1816A_WSS_ENABLE, 0xffff);
486*4882a593Smuzhiyun 	snd_ad1816a_write(chip, AD1816A_DSP_CONFIG, 0x0000);
487*4882a593Smuzhiyun 	snd_ad1816a_write(chip, AD1816A_POWERDOWN_CTRL, 0x0000);
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun #ifdef CONFIG_PM
snd_ad1816a_suspend(struct snd_ad1816a * chip)493*4882a593Smuzhiyun void snd_ad1816a_suspend(struct snd_ad1816a *chip)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun 	int reg;
496*4882a593Smuzhiyun 	unsigned long flags;
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
499*4882a593Smuzhiyun 	for (reg = 0; reg < 48; reg++)
500*4882a593Smuzhiyun 		chip->image[reg] = snd_ad1816a_read(chip, reg);
501*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun 
snd_ad1816a_resume(struct snd_ad1816a * chip)504*4882a593Smuzhiyun void snd_ad1816a_resume(struct snd_ad1816a *chip)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun 	int reg;
507*4882a593Smuzhiyun 	unsigned long flags;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	snd_ad1816a_init(chip);
510*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
511*4882a593Smuzhiyun 	for (reg = 0; reg < 48; reg++)
512*4882a593Smuzhiyun 		snd_ad1816a_write(chip, reg, chip->image[reg]);
513*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun #endif
516*4882a593Smuzhiyun 
snd_ad1816a_probe(struct snd_ad1816a * chip)517*4882a593Smuzhiyun static int snd_ad1816a_probe(struct snd_ad1816a *chip)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun 	unsigned long flags;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	switch (chip->version = snd_ad1816a_read(chip, AD1816A_VERSION_ID)) {
524*4882a593Smuzhiyun 	case 0:
525*4882a593Smuzhiyun 		chip->hardware = AD1816A_HW_AD1815;
526*4882a593Smuzhiyun 		break;
527*4882a593Smuzhiyun 	case 1:
528*4882a593Smuzhiyun 		chip->hardware = AD1816A_HW_AD18MAX10;
529*4882a593Smuzhiyun 		break;
530*4882a593Smuzhiyun 	case 3:
531*4882a593Smuzhiyun 		chip->hardware = AD1816A_HW_AD1816A;
532*4882a593Smuzhiyun 		break;
533*4882a593Smuzhiyun 	default:
534*4882a593Smuzhiyun 		chip->hardware = AD1816A_HW_AUTO;
535*4882a593Smuzhiyun 	}
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
538*4882a593Smuzhiyun 	return 0;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun 
snd_ad1816a_free(struct snd_ad1816a * chip)541*4882a593Smuzhiyun static int snd_ad1816a_free(struct snd_ad1816a *chip)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun 	release_and_free_resource(chip->res_port);
544*4882a593Smuzhiyun 	if (chip->irq >= 0)
545*4882a593Smuzhiyun 		free_irq(chip->irq, (void *) chip);
546*4882a593Smuzhiyun 	if (chip->dma1 >= 0) {
547*4882a593Smuzhiyun 		snd_dma_disable(chip->dma1);
548*4882a593Smuzhiyun 		free_dma(chip->dma1);
549*4882a593Smuzhiyun 	}
550*4882a593Smuzhiyun 	if (chip->dma2 >= 0) {
551*4882a593Smuzhiyun 		snd_dma_disable(chip->dma2);
552*4882a593Smuzhiyun 		free_dma(chip->dma2);
553*4882a593Smuzhiyun 	}
554*4882a593Smuzhiyun 	return 0;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun 
snd_ad1816a_dev_free(struct snd_device * device)557*4882a593Smuzhiyun static int snd_ad1816a_dev_free(struct snd_device *device)
558*4882a593Smuzhiyun {
559*4882a593Smuzhiyun 	struct snd_ad1816a *chip = device->device_data;
560*4882a593Smuzhiyun 	return snd_ad1816a_free(chip);
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun 
snd_ad1816a_chip_id(struct snd_ad1816a * chip)563*4882a593Smuzhiyun static const char *snd_ad1816a_chip_id(struct snd_ad1816a *chip)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun 	switch (chip->hardware) {
566*4882a593Smuzhiyun 	case AD1816A_HW_AD1816A: return "AD1816A";
567*4882a593Smuzhiyun 	case AD1816A_HW_AD1815:	return "AD1815";
568*4882a593Smuzhiyun 	case AD1816A_HW_AD18MAX10: return "AD18max10";
569*4882a593Smuzhiyun 	default:
570*4882a593Smuzhiyun 		snd_printk(KERN_WARNING "Unknown chip version %d:%d.\n",
571*4882a593Smuzhiyun 			chip->version, chip->hardware);
572*4882a593Smuzhiyun 		return "AD1816A - unknown";
573*4882a593Smuzhiyun 	}
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun 
snd_ad1816a_create(struct snd_card * card,unsigned long port,int irq,int dma1,int dma2,struct snd_ad1816a * chip)576*4882a593Smuzhiyun int snd_ad1816a_create(struct snd_card *card,
577*4882a593Smuzhiyun 		       unsigned long port, int irq, int dma1, int dma2,
578*4882a593Smuzhiyun 		       struct snd_ad1816a *chip)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun 	static const struct snd_device_ops ops = {
581*4882a593Smuzhiyun 		.dev_free =	snd_ad1816a_dev_free,
582*4882a593Smuzhiyun 	};
583*4882a593Smuzhiyun 	int error;
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	chip->irq = -1;
586*4882a593Smuzhiyun 	chip->dma1 = -1;
587*4882a593Smuzhiyun 	chip->dma2 = -1;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	if ((chip->res_port = request_region(port, 16, "AD1816A")) == NULL) {
590*4882a593Smuzhiyun 		snd_printk(KERN_ERR "ad1816a: can't grab port 0x%lx\n", port);
591*4882a593Smuzhiyun 		snd_ad1816a_free(chip);
592*4882a593Smuzhiyun 		return -EBUSY;
593*4882a593Smuzhiyun 	}
594*4882a593Smuzhiyun 	if (request_irq(irq, snd_ad1816a_interrupt, 0, "AD1816A", (void *) chip)) {
595*4882a593Smuzhiyun 		snd_printk(KERN_ERR "ad1816a: can't grab IRQ %d\n", irq);
596*4882a593Smuzhiyun 		snd_ad1816a_free(chip);
597*4882a593Smuzhiyun 		return -EBUSY;
598*4882a593Smuzhiyun 	}
599*4882a593Smuzhiyun 	chip->irq = irq;
600*4882a593Smuzhiyun 	card->sync_irq = chip->irq;
601*4882a593Smuzhiyun 	if (request_dma(dma1, "AD1816A - 1")) {
602*4882a593Smuzhiyun 		snd_printk(KERN_ERR "ad1816a: can't grab DMA1 %d\n", dma1);
603*4882a593Smuzhiyun 		snd_ad1816a_free(chip);
604*4882a593Smuzhiyun 		return -EBUSY;
605*4882a593Smuzhiyun 	}
606*4882a593Smuzhiyun 	chip->dma1 = dma1;
607*4882a593Smuzhiyun 	if (request_dma(dma2, "AD1816A - 2")) {
608*4882a593Smuzhiyun 		snd_printk(KERN_ERR "ad1816a: can't grab DMA2 %d\n", dma2);
609*4882a593Smuzhiyun 		snd_ad1816a_free(chip);
610*4882a593Smuzhiyun 		return -EBUSY;
611*4882a593Smuzhiyun 	}
612*4882a593Smuzhiyun 	chip->dma2 = dma2;
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	chip->card = card;
615*4882a593Smuzhiyun 	chip->port = port;
616*4882a593Smuzhiyun 	spin_lock_init(&chip->lock);
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	if ((error = snd_ad1816a_probe(chip))) {
619*4882a593Smuzhiyun 		snd_ad1816a_free(chip);
620*4882a593Smuzhiyun 		return error;
621*4882a593Smuzhiyun 	}
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	snd_ad1816a_init(chip);
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	/* Register device */
626*4882a593Smuzhiyun 	if ((error = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
627*4882a593Smuzhiyun 		snd_ad1816a_free(chip);
628*4882a593Smuzhiyun 		return error;
629*4882a593Smuzhiyun 	}
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	return 0;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ad1816a_playback_ops = {
635*4882a593Smuzhiyun 	.open =		snd_ad1816a_playback_open,
636*4882a593Smuzhiyun 	.close =	snd_ad1816a_playback_close,
637*4882a593Smuzhiyun 	.prepare =	snd_ad1816a_playback_prepare,
638*4882a593Smuzhiyun 	.trigger =	snd_ad1816a_playback_trigger,
639*4882a593Smuzhiyun 	.pointer =	snd_ad1816a_playback_pointer,
640*4882a593Smuzhiyun };
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun static const struct snd_pcm_ops snd_ad1816a_capture_ops = {
643*4882a593Smuzhiyun 	.open =		snd_ad1816a_capture_open,
644*4882a593Smuzhiyun 	.close =	snd_ad1816a_capture_close,
645*4882a593Smuzhiyun 	.prepare =	snd_ad1816a_capture_prepare,
646*4882a593Smuzhiyun 	.trigger =	snd_ad1816a_capture_trigger,
647*4882a593Smuzhiyun 	.pointer =	snd_ad1816a_capture_pointer,
648*4882a593Smuzhiyun };
649*4882a593Smuzhiyun 
snd_ad1816a_pcm(struct snd_ad1816a * chip,int device)650*4882a593Smuzhiyun int snd_ad1816a_pcm(struct snd_ad1816a *chip, int device)
651*4882a593Smuzhiyun {
652*4882a593Smuzhiyun 	int error;
653*4882a593Smuzhiyun 	struct snd_pcm *pcm;
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	if ((error = snd_pcm_new(chip->card, "AD1816A", device, 1, 1, &pcm)))
656*4882a593Smuzhiyun 		return error;
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ad1816a_playback_ops);
659*4882a593Smuzhiyun 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ad1816a_capture_ops);
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	pcm->private_data = chip;
662*4882a593Smuzhiyun 	pcm->info_flags = (chip->dma1 == chip->dma2 ) ? SNDRV_PCM_INFO_JOINT_DUPLEX : 0;
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	strcpy(pcm->name, snd_ad1816a_chip_id(chip));
665*4882a593Smuzhiyun 	snd_ad1816a_init(chip);
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, chip->card->dev,
668*4882a593Smuzhiyun 				       64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	chip->pcm = pcm;
671*4882a593Smuzhiyun 	return 0;
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun 
snd_ad1816a_timer(struct snd_ad1816a * chip,int device)674*4882a593Smuzhiyun int snd_ad1816a_timer(struct snd_ad1816a *chip, int device)
675*4882a593Smuzhiyun {
676*4882a593Smuzhiyun 	struct snd_timer *timer;
677*4882a593Smuzhiyun 	struct snd_timer_id tid;
678*4882a593Smuzhiyun 	int error;
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	tid.dev_class = SNDRV_TIMER_CLASS_CARD;
681*4882a593Smuzhiyun 	tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
682*4882a593Smuzhiyun 	tid.card = chip->card->number;
683*4882a593Smuzhiyun 	tid.device = device;
684*4882a593Smuzhiyun 	tid.subdevice = 0;
685*4882a593Smuzhiyun 	if ((error = snd_timer_new(chip->card, "AD1816A", &tid, &timer)) < 0)
686*4882a593Smuzhiyun 		return error;
687*4882a593Smuzhiyun 	strcpy(timer->name, snd_ad1816a_chip_id(chip));
688*4882a593Smuzhiyun 	timer->private_data = chip;
689*4882a593Smuzhiyun 	chip->timer = timer;
690*4882a593Smuzhiyun 	timer->hw = snd_ad1816a_timer_table;
691*4882a593Smuzhiyun 	return 0;
692*4882a593Smuzhiyun }
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun /*
695*4882a593Smuzhiyun  *
696*4882a593Smuzhiyun  */
697*4882a593Smuzhiyun 
snd_ad1816a_info_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)698*4882a593Smuzhiyun static int snd_ad1816a_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
699*4882a593Smuzhiyun {
700*4882a593Smuzhiyun 	static const char * const texts[8] = {
701*4882a593Smuzhiyun 		"Line", "Mix", "CD", "Synth", "Video",
702*4882a593Smuzhiyun 		"Mic", "Phone",
703*4882a593Smuzhiyun 	};
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun 	return snd_ctl_enum_info(uinfo, 2, 7, texts);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun 
snd_ad1816a_get_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)708*4882a593Smuzhiyun static int snd_ad1816a_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_kcontrol_chip(kcontrol);
711*4882a593Smuzhiyun 	unsigned long flags;
712*4882a593Smuzhiyun 	unsigned short val;
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
715*4882a593Smuzhiyun 	val = snd_ad1816a_read(chip, AD1816A_ADC_SOURCE_SEL);
716*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
717*4882a593Smuzhiyun 	ucontrol->value.enumerated.item[0] = (val >> 12) & 7;
718*4882a593Smuzhiyun 	ucontrol->value.enumerated.item[1] = (val >> 4) & 7;
719*4882a593Smuzhiyun 	return 0;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun 
snd_ad1816a_put_mux(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)722*4882a593Smuzhiyun static int snd_ad1816a_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_kcontrol_chip(kcontrol);
725*4882a593Smuzhiyun 	unsigned long flags;
726*4882a593Smuzhiyun 	unsigned short val;
727*4882a593Smuzhiyun 	int change;
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	if (ucontrol->value.enumerated.item[0] > 6 ||
730*4882a593Smuzhiyun 	    ucontrol->value.enumerated.item[1] > 6)
731*4882a593Smuzhiyun 		return -EINVAL;
732*4882a593Smuzhiyun 	val = (ucontrol->value.enumerated.item[0] << 12) |
733*4882a593Smuzhiyun 	      (ucontrol->value.enumerated.item[1] << 4);
734*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
735*4882a593Smuzhiyun 	change = snd_ad1816a_read(chip, AD1816A_ADC_SOURCE_SEL) != val;
736*4882a593Smuzhiyun 	snd_ad1816a_write(chip, AD1816A_ADC_SOURCE_SEL, val);
737*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
738*4882a593Smuzhiyun 	return change;
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun #define AD1816A_SINGLE_TLV(xname, reg, shift, mask, invert, xtlv)	\
742*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
743*4882a593Smuzhiyun   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
744*4882a593Smuzhiyun   .name = xname, .info = snd_ad1816a_info_single, \
745*4882a593Smuzhiyun   .get = snd_ad1816a_get_single, .put = snd_ad1816a_put_single, \
746*4882a593Smuzhiyun   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
747*4882a593Smuzhiyun   .tlv = { .p = (xtlv) } }
748*4882a593Smuzhiyun #define AD1816A_SINGLE(xname, reg, shift, mask, invert) \
749*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_ad1816a_info_single, \
750*4882a593Smuzhiyun   .get = snd_ad1816a_get_single, .put = snd_ad1816a_put_single, \
751*4882a593Smuzhiyun   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
752*4882a593Smuzhiyun 
snd_ad1816a_info_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)753*4882a593Smuzhiyun static int snd_ad1816a_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
754*4882a593Smuzhiyun {
755*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
758*4882a593Smuzhiyun 	uinfo->count = 1;
759*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
760*4882a593Smuzhiyun 	uinfo->value.integer.max = mask;
761*4882a593Smuzhiyun 	return 0;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun 
snd_ad1816a_get_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)764*4882a593Smuzhiyun static int snd_ad1816a_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_kcontrol_chip(kcontrol);
767*4882a593Smuzhiyun 	unsigned long flags;
768*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
769*4882a593Smuzhiyun 	int shift = (kcontrol->private_value >> 8) & 0xff;
770*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
771*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
774*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (snd_ad1816a_read(chip, reg) >> shift) & mask;
775*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
776*4882a593Smuzhiyun 	if (invert)
777*4882a593Smuzhiyun 		ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
778*4882a593Smuzhiyun 	return 0;
779*4882a593Smuzhiyun }
780*4882a593Smuzhiyun 
snd_ad1816a_put_single(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)781*4882a593Smuzhiyun static int snd_ad1816a_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
782*4882a593Smuzhiyun {
783*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_kcontrol_chip(kcontrol);
784*4882a593Smuzhiyun 	unsigned long flags;
785*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
786*4882a593Smuzhiyun 	int shift = (kcontrol->private_value >> 8) & 0xff;
787*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
788*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
789*4882a593Smuzhiyun 	int change;
790*4882a593Smuzhiyun 	unsigned short old_val, val;
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun 	val = (ucontrol->value.integer.value[0] & mask);
793*4882a593Smuzhiyun 	if (invert)
794*4882a593Smuzhiyun 		val = mask - val;
795*4882a593Smuzhiyun 	val <<= shift;
796*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
797*4882a593Smuzhiyun 	old_val = snd_ad1816a_read(chip, reg);
798*4882a593Smuzhiyun 	val = (old_val & ~(mask << shift)) | val;
799*4882a593Smuzhiyun 	change = val != old_val;
800*4882a593Smuzhiyun 	snd_ad1816a_write(chip, reg, val);
801*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
802*4882a593Smuzhiyun 	return change;
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun #define AD1816A_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \
806*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
807*4882a593Smuzhiyun   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
808*4882a593Smuzhiyun   .name = xname, .info = snd_ad1816a_info_double,		\
809*4882a593Smuzhiyun   .get = snd_ad1816a_get_double, .put = snd_ad1816a_put_double, \
810*4882a593Smuzhiyun   .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \
811*4882a593Smuzhiyun   .tlv = { .p = (xtlv) } }
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun #define AD1816A_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
814*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_ad1816a_info_double, \
815*4882a593Smuzhiyun   .get = snd_ad1816a_get_double, .put = snd_ad1816a_put_double, \
816*4882a593Smuzhiyun   .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) }
817*4882a593Smuzhiyun 
snd_ad1816a_info_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)818*4882a593Smuzhiyun static int snd_ad1816a_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
819*4882a593Smuzhiyun {
820*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
823*4882a593Smuzhiyun 	uinfo->count = 2;
824*4882a593Smuzhiyun 	uinfo->value.integer.min = 0;
825*4882a593Smuzhiyun 	uinfo->value.integer.max = mask;
826*4882a593Smuzhiyun 	return 0;
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun 
snd_ad1816a_get_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)829*4882a593Smuzhiyun static int snd_ad1816a_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
830*4882a593Smuzhiyun {
831*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_kcontrol_chip(kcontrol);
832*4882a593Smuzhiyun 	unsigned long flags;
833*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
834*4882a593Smuzhiyun 	int shift_left = (kcontrol->private_value >> 8) & 0x0f;
835*4882a593Smuzhiyun 	int shift_right = (kcontrol->private_value >> 12) & 0x0f;
836*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
837*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
838*4882a593Smuzhiyun 	unsigned short val;
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
841*4882a593Smuzhiyun 	val = snd_ad1816a_read(chip, reg);
842*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
843*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
844*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
845*4882a593Smuzhiyun 	if (invert) {
846*4882a593Smuzhiyun 		ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
847*4882a593Smuzhiyun 		ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
848*4882a593Smuzhiyun 	}
849*4882a593Smuzhiyun 	return 0;
850*4882a593Smuzhiyun }
851*4882a593Smuzhiyun 
snd_ad1816a_put_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)852*4882a593Smuzhiyun static int snd_ad1816a_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
853*4882a593Smuzhiyun {
854*4882a593Smuzhiyun 	struct snd_ad1816a *chip = snd_kcontrol_chip(kcontrol);
855*4882a593Smuzhiyun 	unsigned long flags;
856*4882a593Smuzhiyun 	int reg = kcontrol->private_value & 0xff;
857*4882a593Smuzhiyun 	int shift_left = (kcontrol->private_value >> 8) & 0x0f;
858*4882a593Smuzhiyun 	int shift_right = (kcontrol->private_value >> 12) & 0x0f;
859*4882a593Smuzhiyun 	int mask = (kcontrol->private_value >> 16) & 0xff;
860*4882a593Smuzhiyun 	int invert = (kcontrol->private_value >> 24) & 0xff;
861*4882a593Smuzhiyun 	int change;
862*4882a593Smuzhiyun 	unsigned short old_val, val1, val2;
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 	val1 = ucontrol->value.integer.value[0] & mask;
865*4882a593Smuzhiyun 	val2 = ucontrol->value.integer.value[1] & mask;
866*4882a593Smuzhiyun 	if (invert) {
867*4882a593Smuzhiyun 		val1 = mask - val1;
868*4882a593Smuzhiyun 		val2 = mask - val2;
869*4882a593Smuzhiyun 	}
870*4882a593Smuzhiyun 	val1 <<= shift_left;
871*4882a593Smuzhiyun 	val2 <<= shift_right;
872*4882a593Smuzhiyun 	spin_lock_irqsave(&chip->lock, flags);
873*4882a593Smuzhiyun 	old_val = snd_ad1816a_read(chip, reg);
874*4882a593Smuzhiyun 	val1 = (old_val & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
875*4882a593Smuzhiyun 	change = val1 != old_val;
876*4882a593Smuzhiyun 	snd_ad1816a_write(chip, reg, val1);
877*4882a593Smuzhiyun 	spin_unlock_irqrestore(&chip->lock, flags);
878*4882a593Smuzhiyun 	return change;
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_4bit, -4500, 300, 0);
882*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_5bit, -4650, 150, 0);
883*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
884*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
885*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun static const struct snd_kcontrol_new snd_ad1816a_controls[] = {
888*4882a593Smuzhiyun AD1816A_DOUBLE("Master Playback Switch", AD1816A_MASTER_ATT, 15, 7, 1, 1),
889*4882a593Smuzhiyun AD1816A_DOUBLE_TLV("Master Playback Volume", AD1816A_MASTER_ATT, 8, 0, 31, 1,
890*4882a593Smuzhiyun 		   db_scale_5bit),
891*4882a593Smuzhiyun AD1816A_DOUBLE("PCM Playback Switch", AD1816A_VOICE_ATT, 15, 7, 1, 1),
892*4882a593Smuzhiyun AD1816A_DOUBLE_TLV("PCM Playback Volume", AD1816A_VOICE_ATT, 8, 0, 63, 1,
893*4882a593Smuzhiyun 		   db_scale_6bit),
894*4882a593Smuzhiyun AD1816A_DOUBLE("Line Playback Switch", AD1816A_LINE_GAIN_ATT, 15, 7, 1, 1),
895*4882a593Smuzhiyun AD1816A_DOUBLE_TLV("Line Playback Volume", AD1816A_LINE_GAIN_ATT, 8, 0, 31, 1,
896*4882a593Smuzhiyun 		   db_scale_5bit_12db_max),
897*4882a593Smuzhiyun AD1816A_DOUBLE("CD Playback Switch", AD1816A_CD_GAIN_ATT, 15, 7, 1, 1),
898*4882a593Smuzhiyun AD1816A_DOUBLE_TLV("CD Playback Volume", AD1816A_CD_GAIN_ATT, 8, 0, 31, 1,
899*4882a593Smuzhiyun 		   db_scale_5bit_12db_max),
900*4882a593Smuzhiyun AD1816A_DOUBLE("Synth Playback Switch", AD1816A_SYNTH_GAIN_ATT, 15, 7, 1, 1),
901*4882a593Smuzhiyun AD1816A_DOUBLE_TLV("Synth Playback Volume", AD1816A_SYNTH_GAIN_ATT, 8, 0, 31, 1,
902*4882a593Smuzhiyun 		   db_scale_5bit_12db_max),
903*4882a593Smuzhiyun AD1816A_DOUBLE("FM Playback Switch", AD1816A_FM_ATT, 15, 7, 1, 1),
904*4882a593Smuzhiyun AD1816A_DOUBLE_TLV("FM Playback Volume", AD1816A_FM_ATT, 8, 0, 63, 1,
905*4882a593Smuzhiyun 		   db_scale_6bit),
906*4882a593Smuzhiyun AD1816A_SINGLE("Mic Playback Switch", AD1816A_MIC_GAIN_ATT, 15, 1, 1),
907*4882a593Smuzhiyun AD1816A_SINGLE_TLV("Mic Playback Volume", AD1816A_MIC_GAIN_ATT, 8, 31, 1,
908*4882a593Smuzhiyun 		   db_scale_5bit_12db_max),
909*4882a593Smuzhiyun AD1816A_SINGLE("Mic Boost", AD1816A_MIC_GAIN_ATT, 14, 1, 0),
910*4882a593Smuzhiyun AD1816A_DOUBLE("Video Playback Switch", AD1816A_VID_GAIN_ATT, 15, 7, 1, 1),
911*4882a593Smuzhiyun AD1816A_DOUBLE_TLV("Video Playback Volume", AD1816A_VID_GAIN_ATT, 8, 0, 31, 1,
912*4882a593Smuzhiyun 		   db_scale_5bit_12db_max),
913*4882a593Smuzhiyun AD1816A_SINGLE("Phone Capture Switch", AD1816A_PHONE_IN_GAIN_ATT, 15, 1, 1),
914*4882a593Smuzhiyun AD1816A_SINGLE_TLV("Phone Capture Volume", AD1816A_PHONE_IN_GAIN_ATT, 0, 15, 1,
915*4882a593Smuzhiyun 		   db_scale_4bit),
916*4882a593Smuzhiyun AD1816A_SINGLE("Phone Playback Switch", AD1816A_PHONE_OUT_ATT, 7, 1, 1),
917*4882a593Smuzhiyun AD1816A_SINGLE_TLV("Phone Playback Volume", AD1816A_PHONE_OUT_ATT, 0, 31, 1,
918*4882a593Smuzhiyun 		   db_scale_5bit),
919*4882a593Smuzhiyun {
920*4882a593Smuzhiyun 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
921*4882a593Smuzhiyun 	.name = "Capture Source",
922*4882a593Smuzhiyun 	.info = snd_ad1816a_info_mux,
923*4882a593Smuzhiyun 	.get = snd_ad1816a_get_mux,
924*4882a593Smuzhiyun 	.put = snd_ad1816a_put_mux,
925*4882a593Smuzhiyun },
926*4882a593Smuzhiyun AD1816A_DOUBLE("Capture Switch", AD1816A_ADC_PGA, 15, 7, 1, 1),
927*4882a593Smuzhiyun AD1816A_DOUBLE_TLV("Capture Volume", AD1816A_ADC_PGA, 8, 0, 15, 0,
928*4882a593Smuzhiyun 		   db_scale_rec_gain),
929*4882a593Smuzhiyun AD1816A_SINGLE("3D Control - Switch", AD1816A_3D_PHAT_CTRL, 15, 1, 1),
930*4882a593Smuzhiyun AD1816A_SINGLE("3D Control - Level", AD1816A_3D_PHAT_CTRL, 0, 15, 0),
931*4882a593Smuzhiyun };
932*4882a593Smuzhiyun 
snd_ad1816a_mixer(struct snd_ad1816a * chip)933*4882a593Smuzhiyun int snd_ad1816a_mixer(struct snd_ad1816a *chip)
934*4882a593Smuzhiyun {
935*4882a593Smuzhiyun 	struct snd_card *card;
936*4882a593Smuzhiyun 	unsigned int idx;
937*4882a593Smuzhiyun 	int err;
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	if (snd_BUG_ON(!chip || !chip->card))
940*4882a593Smuzhiyun 		return -EINVAL;
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun 	card = chip->card;
943*4882a593Smuzhiyun 
944*4882a593Smuzhiyun 	strcpy(card->mixername, snd_ad1816a_chip_id(chip));
945*4882a593Smuzhiyun 
946*4882a593Smuzhiyun 	for (idx = 0; idx < ARRAY_SIZE(snd_ad1816a_controls); idx++) {
947*4882a593Smuzhiyun 		if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_ad1816a_controls[idx], chip))) < 0)
948*4882a593Smuzhiyun 			return err;
949*4882a593Smuzhiyun 	}
950*4882a593Smuzhiyun 	return 0;
951*4882a593Smuzhiyun }
952