1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * motu-protocol-v2.c - a part of driver for MOTU FireWire series
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "motu.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define V2_CLOCK_STATUS_OFFSET 0x0b14
11*4882a593Smuzhiyun #define V2_CLOCK_RATE_MASK 0x00000038
12*4882a593Smuzhiyun #define V2_CLOCK_RATE_SHIFT 3
13*4882a593Smuzhiyun #define V2_CLOCK_SRC_MASK 0x00000007
14*4882a593Smuzhiyun #define V2_CLOCK_SRC_SHIFT 0
15*4882a593Smuzhiyun #define V2_CLOCK_FETCH_ENABLE 0x02000000
16*4882a593Smuzhiyun #define V2_CLOCK_MODEL_SPECIFIC 0x04000000
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define V2_IN_OUT_CONF_OFFSET 0x0c04
19*4882a593Smuzhiyun #define V2_OPT_OUT_IFACE_MASK 0x00000c00
20*4882a593Smuzhiyun #define V2_OPT_OUT_IFACE_SHIFT 10
21*4882a593Smuzhiyun #define V2_OPT_IN_IFACE_MASK 0x00000300
22*4882a593Smuzhiyun #define V2_OPT_IN_IFACE_SHIFT 8
23*4882a593Smuzhiyun #define V2_OPT_IFACE_MODE_NONE 0
24*4882a593Smuzhiyun #define V2_OPT_IFACE_MODE_ADAT 1
25*4882a593Smuzhiyun #define V2_OPT_IFACE_MODE_SPDIF 2
26*4882a593Smuzhiyun
get_clock_rate(u32 data,unsigned int * rate)27*4882a593Smuzhiyun static int get_clock_rate(u32 data, unsigned int *rate)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun unsigned int index = (data & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT;
30*4882a593Smuzhiyun if (index >= ARRAY_SIZE(snd_motu_clock_rates))
31*4882a593Smuzhiyun return -EIO;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun *rate = snd_motu_clock_rates[index];
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return 0;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
snd_motu_protocol_v2_get_clock_rate(struct snd_motu * motu,unsigned int * rate)38*4882a593Smuzhiyun int snd_motu_protocol_v2_get_clock_rate(struct snd_motu *motu,
39*4882a593Smuzhiyun unsigned int *rate)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun __be32 reg;
42*4882a593Smuzhiyun int err;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
45*4882a593Smuzhiyun sizeof(reg));
46*4882a593Smuzhiyun if (err < 0)
47*4882a593Smuzhiyun return err;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return get_clock_rate(be32_to_cpu(reg), rate);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
snd_motu_protocol_v2_set_clock_rate(struct snd_motu * motu,unsigned int rate)52*4882a593Smuzhiyun int snd_motu_protocol_v2_set_clock_rate(struct snd_motu *motu,
53*4882a593Smuzhiyun unsigned int rate)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun __be32 reg;
56*4882a593Smuzhiyun u32 data;
57*4882a593Smuzhiyun int i;
58*4882a593Smuzhiyun int err;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
61*4882a593Smuzhiyun if (snd_motu_clock_rates[i] == rate)
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun if (i == ARRAY_SIZE(snd_motu_clock_rates))
65*4882a593Smuzhiyun return -EINVAL;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
68*4882a593Smuzhiyun sizeof(reg));
69*4882a593Smuzhiyun if (err < 0)
70*4882a593Smuzhiyun return err;
71*4882a593Smuzhiyun data = be32_to_cpu(reg);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun data &= ~V2_CLOCK_RATE_MASK;
74*4882a593Smuzhiyun data |= i << V2_CLOCK_RATE_SHIFT;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun reg = cpu_to_be32(data);
77*4882a593Smuzhiyun return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
78*4882a593Smuzhiyun sizeof(reg));
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
detect_clock_source_optical_model(struct snd_motu * motu,u32 data,enum snd_motu_clock_source * src)81*4882a593Smuzhiyun static int detect_clock_source_optical_model(struct snd_motu *motu, u32 data,
82*4882a593Smuzhiyun enum snd_motu_clock_source *src)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun switch (data) {
85*4882a593Smuzhiyun case 0:
86*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
87*4882a593Smuzhiyun break;
88*4882a593Smuzhiyun case 1:
89*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
90*4882a593Smuzhiyun break;
91*4882a593Smuzhiyun case 2:
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun __be32 reg;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun // To check the configuration of optical interface.
96*4882a593Smuzhiyun int err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®, sizeof(reg));
97*4882a593Smuzhiyun if (err < 0)
98*4882a593Smuzhiyun return err;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) == V2_OPT_IFACE_MODE_SPDIF)
101*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
102*4882a593Smuzhiyun else
103*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
104*4882a593Smuzhiyun break;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun case 3:
107*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_SPH;
108*4882a593Smuzhiyun break;
109*4882a593Smuzhiyun case 4:
110*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
111*4882a593Smuzhiyun break;
112*4882a593Smuzhiyun case 5:
113*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
114*4882a593Smuzhiyun break;
115*4882a593Smuzhiyun default:
116*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_UNKNOWN;
117*4882a593Smuzhiyun break;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
v2_detect_clock_source(struct snd_motu * motu,u32 data,enum snd_motu_clock_source * src)123*4882a593Smuzhiyun static int v2_detect_clock_source(struct snd_motu *motu, u32 data,
124*4882a593Smuzhiyun enum snd_motu_clock_source *src)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun switch (data) {
127*4882a593Smuzhiyun case 0:
128*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun case 2:
131*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun case 3:
134*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_SPH;
135*4882a593Smuzhiyun break;
136*4882a593Smuzhiyun case 4:
137*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun default:
140*4882a593Smuzhiyun *src = SND_MOTU_CLOCK_SOURCE_UNKNOWN;
141*4882a593Smuzhiyun break;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
get_clock_source(struct snd_motu * motu,u32 data,enum snd_motu_clock_source * src)147*4882a593Smuzhiyun static int get_clock_source(struct snd_motu *motu, u32 data,
148*4882a593Smuzhiyun enum snd_motu_clock_source *src)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun data &= V2_CLOCK_SRC_MASK;
151*4882a593Smuzhiyun if (motu->spec == &snd_motu_spec_828mk2 ||
152*4882a593Smuzhiyun motu->spec == &snd_motu_spec_traveler)
153*4882a593Smuzhiyun return detect_clock_source_optical_model(motu, data, src);
154*4882a593Smuzhiyun else
155*4882a593Smuzhiyun return v2_detect_clock_source(motu, data, src);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
snd_motu_protocol_v2_get_clock_source(struct snd_motu * motu,enum snd_motu_clock_source * src)158*4882a593Smuzhiyun int snd_motu_protocol_v2_get_clock_source(struct snd_motu *motu,
159*4882a593Smuzhiyun enum snd_motu_clock_source *src)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun __be32 reg;
162*4882a593Smuzhiyun int err;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
165*4882a593Smuzhiyun sizeof(reg));
166*4882a593Smuzhiyun if (err < 0)
167*4882a593Smuzhiyun return err;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return get_clock_source(motu, be32_to_cpu(reg), src);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun // Expected for Traveler and 896HD, which implements Altera Cyclone EP1C3.
switch_fetching_mode_cyclone(struct snd_motu * motu,u32 * data,bool enable)173*4882a593Smuzhiyun static int switch_fetching_mode_cyclone(struct snd_motu *motu, u32 *data,
174*4882a593Smuzhiyun bool enable)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun *data |= V2_CLOCK_MODEL_SPECIFIC;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun return 0;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun // For UltraLite and 8pre, which implements Xilinx Spartan XC3S200.
switch_fetching_mode_spartan(struct snd_motu * motu,u32 * data,bool enable)182*4882a593Smuzhiyun static int switch_fetching_mode_spartan(struct snd_motu *motu, u32 *data,
183*4882a593Smuzhiyun bool enable)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun unsigned int rate;
186*4882a593Smuzhiyun enum snd_motu_clock_source src;
187*4882a593Smuzhiyun int err;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun err = get_clock_source(motu, *data, &src);
190*4882a593Smuzhiyun if (err < 0)
191*4882a593Smuzhiyun return err;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun err = get_clock_rate(*data, &rate);
194*4882a593Smuzhiyun if (err < 0)
195*4882a593Smuzhiyun return err;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000)
198*4882a593Smuzhiyun *data |= V2_CLOCK_MODEL_SPECIFIC;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return 0;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
snd_motu_protocol_v2_switch_fetching_mode(struct snd_motu * motu,bool enable)203*4882a593Smuzhiyun int snd_motu_protocol_v2_switch_fetching_mode(struct snd_motu *motu,
204*4882a593Smuzhiyun bool enable)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun if (motu->spec == &snd_motu_spec_828mk2) {
207*4882a593Smuzhiyun // 828mkII implements Altera ACEX 1K EP1K30. Nothing to do.
208*4882a593Smuzhiyun return 0;
209*4882a593Smuzhiyun } else {
210*4882a593Smuzhiyun __be32 reg;
211*4882a593Smuzhiyun u32 data;
212*4882a593Smuzhiyun int err;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET,
215*4882a593Smuzhiyun ®, sizeof(reg));
216*4882a593Smuzhiyun if (err < 0)
217*4882a593Smuzhiyun return err;
218*4882a593Smuzhiyun data = be32_to_cpu(reg);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC);
221*4882a593Smuzhiyun if (enable)
222*4882a593Smuzhiyun data |= V2_CLOCK_FETCH_ENABLE;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun if (motu->spec == &snd_motu_spec_traveler)
225*4882a593Smuzhiyun err = switch_fetching_mode_cyclone(motu, &data, enable);
226*4882a593Smuzhiyun else
227*4882a593Smuzhiyun err = switch_fetching_mode_spartan(motu, &data, enable);
228*4882a593Smuzhiyun if (err < 0)
229*4882a593Smuzhiyun return err;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun reg = cpu_to_be32(data);
232*4882a593Smuzhiyun return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET,
233*4882a593Smuzhiyun ®, sizeof(reg));
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
detect_packet_formats_828mk2(struct snd_motu * motu,u32 data)237*4882a593Smuzhiyun static int detect_packet_formats_828mk2(struct snd_motu *motu, u32 data)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) ==
240*4882a593Smuzhiyun V2_OPT_IFACE_MODE_ADAT) {
241*4882a593Smuzhiyun motu->tx_packet_formats.pcm_chunks[0] += 8;
242*4882a593Smuzhiyun motu->tx_packet_formats.pcm_chunks[1] += 4;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (((data & V2_OPT_OUT_IFACE_MASK) >> V2_OPT_OUT_IFACE_SHIFT) ==
246*4882a593Smuzhiyun V2_OPT_IFACE_MODE_ADAT) {
247*4882a593Smuzhiyun motu->rx_packet_formats.pcm_chunks[0] += 8;
248*4882a593Smuzhiyun motu->rx_packet_formats.pcm_chunks[1] += 4;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun return 0;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
detect_packet_formats_traveler(struct snd_motu * motu,u32 data)254*4882a593Smuzhiyun static int detect_packet_formats_traveler(struct snd_motu *motu, u32 data)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) ==
257*4882a593Smuzhiyun V2_OPT_IFACE_MODE_ADAT) {
258*4882a593Smuzhiyun motu->tx_packet_formats.pcm_chunks[0] += 8;
259*4882a593Smuzhiyun motu->tx_packet_formats.pcm_chunks[1] += 4;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun if (((data & V2_OPT_OUT_IFACE_MASK) >> V2_OPT_OUT_IFACE_SHIFT) ==
263*4882a593Smuzhiyun V2_OPT_IFACE_MODE_ADAT) {
264*4882a593Smuzhiyun motu->rx_packet_formats.pcm_chunks[0] += 8;
265*4882a593Smuzhiyun motu->rx_packet_formats.pcm_chunks[1] += 4;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun return 0;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
detect_packet_formats_8pre(struct snd_motu * motu,u32 data)271*4882a593Smuzhiyun static int detect_packet_formats_8pre(struct snd_motu *motu, u32 data)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun if (((data & V2_OPT_IN_IFACE_MASK) >> V2_OPT_IN_IFACE_SHIFT) ==
274*4882a593Smuzhiyun V2_OPT_IFACE_MODE_ADAT) {
275*4882a593Smuzhiyun motu->tx_packet_formats.pcm_chunks[0] += 8;
276*4882a593Smuzhiyun motu->tx_packet_formats.pcm_chunks[1] += 8;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (((data & V2_OPT_OUT_IFACE_MASK) >> V2_OPT_OUT_IFACE_SHIFT) ==
280*4882a593Smuzhiyun V2_OPT_IFACE_MODE_ADAT) {
281*4882a593Smuzhiyun motu->rx_packet_formats.pcm_chunks[0] += 8;
282*4882a593Smuzhiyun motu->rx_packet_formats.pcm_chunks[1] += 8;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun return 0;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
snd_motu_protocol_v2_cache_packet_formats(struct snd_motu * motu)288*4882a593Smuzhiyun int snd_motu_protocol_v2_cache_packet_formats(struct snd_motu *motu)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun __be32 reg;
291*4882a593Smuzhiyun u32 data;
292*4882a593Smuzhiyun int err;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun motu->tx_packet_formats.pcm_byte_offset = 10;
295*4882a593Smuzhiyun motu->rx_packet_formats.pcm_byte_offset = 10;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun motu->tx_packet_formats.msg_chunks = 2;
298*4882a593Smuzhiyun motu->rx_packet_formats.msg_chunks = 2;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
301*4882a593Smuzhiyun sizeof(reg));
302*4882a593Smuzhiyun if (err < 0)
303*4882a593Smuzhiyun return err;
304*4882a593Smuzhiyun data = be32_to_cpu(reg);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun memcpy(motu->tx_packet_formats.pcm_chunks,
307*4882a593Smuzhiyun motu->spec->tx_fixed_pcm_chunks,
308*4882a593Smuzhiyun sizeof(motu->tx_packet_formats.pcm_chunks));
309*4882a593Smuzhiyun memcpy(motu->rx_packet_formats.pcm_chunks,
310*4882a593Smuzhiyun motu->spec->rx_fixed_pcm_chunks,
311*4882a593Smuzhiyun sizeof(motu->rx_packet_formats.pcm_chunks));
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun if (motu->spec == &snd_motu_spec_828mk2)
314*4882a593Smuzhiyun return detect_packet_formats_828mk2(motu, data);
315*4882a593Smuzhiyun else if (motu->spec == &snd_motu_spec_traveler)
316*4882a593Smuzhiyun return detect_packet_formats_traveler(motu, data);
317*4882a593Smuzhiyun else if (motu->spec == &snd_motu_spec_8pre)
318*4882a593Smuzhiyun return detect_packet_formats_8pre(motu, data);
319*4882a593Smuzhiyun else
320*4882a593Smuzhiyun return 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun const struct snd_motu_spec snd_motu_spec_828mk2 = {
324*4882a593Smuzhiyun .name = "828mk2",
325*4882a593Smuzhiyun .protocol_version = SND_MOTU_PROTOCOL_V2,
326*4882a593Smuzhiyun .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
327*4882a593Smuzhiyun SND_MOTU_SPEC_TX_MIDI_2ND_Q,
328*4882a593Smuzhiyun .tx_fixed_pcm_chunks = {14, 14, 0},
329*4882a593Smuzhiyun .rx_fixed_pcm_chunks = {14, 14, 0},
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun const struct snd_motu_spec snd_motu_spec_traveler = {
333*4882a593Smuzhiyun .name = "Traveler",
334*4882a593Smuzhiyun .protocol_version = SND_MOTU_PROTOCOL_V2,
335*4882a593Smuzhiyun .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
336*4882a593Smuzhiyun SND_MOTU_SPEC_TX_MIDI_2ND_Q,
337*4882a593Smuzhiyun .tx_fixed_pcm_chunks = {14, 14, 8},
338*4882a593Smuzhiyun .rx_fixed_pcm_chunks = {14, 14, 8},
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun const struct snd_motu_spec snd_motu_spec_ultralite = {
342*4882a593Smuzhiyun .name = "UltraLite",
343*4882a593Smuzhiyun .protocol_version = SND_MOTU_PROTOCOL_V2,
344*4882a593Smuzhiyun .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
345*4882a593Smuzhiyun SND_MOTU_SPEC_TX_MIDI_2ND_Q,
346*4882a593Smuzhiyun .tx_fixed_pcm_chunks = {14, 14, 0},
347*4882a593Smuzhiyun .rx_fixed_pcm_chunks = {14, 14, 0},
348*4882a593Smuzhiyun };
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun const struct snd_motu_spec snd_motu_spec_8pre = {
351*4882a593Smuzhiyun .name = "8pre",
352*4882a593Smuzhiyun .protocol_version = SND_MOTU_PROTOCOL_V2,
353*4882a593Smuzhiyun .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
354*4882a593Smuzhiyun SND_MOTU_SPEC_TX_MIDI_2ND_Q,
355*4882a593Smuzhiyun // Two dummy chunks always in the end of data block.
356*4882a593Smuzhiyun .tx_fixed_pcm_chunks = {10, 10, 0},
357*4882a593Smuzhiyun .rx_fixed_pcm_chunks = {6, 6, 0},
358*4882a593Smuzhiyun };
359