xref: /OK3568_Linux_fs/kernel/sound/firewire/fireworks/fireworks.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * fireworks.h - a part of driver for Fireworks based devices
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2009-2010 Clemens Ladisch
6*4882a593Smuzhiyun  * Copyright (c) 2013-2014 Takashi Sakamoto
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #ifndef SOUND_FIREWORKS_H_INCLUDED
9*4882a593Smuzhiyun #define SOUND_FIREWORKS_H_INCLUDED
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/compat.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/firewire.h>
14*4882a593Smuzhiyun #include <linux/firewire-constants.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/sched/signal.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <sound/core.h>
22*4882a593Smuzhiyun #include <sound/initval.h>
23*4882a593Smuzhiyun #include <sound/pcm.h>
24*4882a593Smuzhiyun #include <sound/info.h>
25*4882a593Smuzhiyun #include <sound/rawmidi.h>
26*4882a593Smuzhiyun #include <sound/pcm_params.h>
27*4882a593Smuzhiyun #include <sound/firewire.h>
28*4882a593Smuzhiyun #include <sound/hwdep.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #include "../packets-buffer.h"
31*4882a593Smuzhiyun #include "../iso-resources.h"
32*4882a593Smuzhiyun #include "../amdtp-am824.h"
33*4882a593Smuzhiyun #include "../cmp.h"
34*4882a593Smuzhiyun #include "../lib.h"
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define SND_EFW_MAX_MIDI_OUT_PORTS	2
37*4882a593Smuzhiyun #define SND_EFW_MAX_MIDI_IN_PORTS	2
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define SND_EFW_MULTIPLIER_MODES	3
40*4882a593Smuzhiyun #define HWINFO_NAME_SIZE_BYTES		32
41*4882a593Smuzhiyun #define HWINFO_MAX_CAPS_GROUPS		8
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun  * This should be greater than maximum bytes for EFW response content.
45*4882a593Smuzhiyun  * Currently response against command for isochronous channel mapping is
46*4882a593Smuzhiyun  * confirmed to be the maximum one. But for flexibility, use maximum data
47*4882a593Smuzhiyun  * payload for asynchronous primary packets at S100 (Cable base rate) in
48*4882a593Smuzhiyun  * IEEE Std 1394-1995.
49*4882a593Smuzhiyun  */
50*4882a593Smuzhiyun #define SND_EFW_RESPONSE_MAXIMUM_BYTES	0x200U
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun extern unsigned int snd_efw_resp_buf_size;
53*4882a593Smuzhiyun extern bool snd_efw_resp_buf_debug;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun struct snd_efw_phys_grp {
56*4882a593Smuzhiyun 	u8 type;	/* see enum snd_efw_grp_type */
57*4882a593Smuzhiyun 	u8 count;
58*4882a593Smuzhiyun } __packed;
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun struct snd_efw {
61*4882a593Smuzhiyun 	struct snd_card *card;
62*4882a593Smuzhiyun 	struct fw_unit *unit;
63*4882a593Smuzhiyun 	int card_index;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	struct mutex mutex;
66*4882a593Smuzhiyun 	spinlock_t lock;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	bool registered;
69*4882a593Smuzhiyun 	struct delayed_work dwork;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	/* for transaction */
72*4882a593Smuzhiyun 	u32 seqnum;
73*4882a593Smuzhiyun 	bool resp_addr_changable;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	/* for quirks */
76*4882a593Smuzhiyun 	bool is_af9;
77*4882a593Smuzhiyun 	bool is_fireworks3;
78*4882a593Smuzhiyun 	u32 firmware_version;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	unsigned int midi_in_ports;
81*4882a593Smuzhiyun 	unsigned int midi_out_ports;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	unsigned int supported_sampling_rate;
84*4882a593Smuzhiyun 	unsigned int pcm_capture_channels[SND_EFW_MULTIPLIER_MODES];
85*4882a593Smuzhiyun 	unsigned int pcm_playback_channels[SND_EFW_MULTIPLIER_MODES];
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	struct amdtp_stream tx_stream;
88*4882a593Smuzhiyun 	struct amdtp_stream rx_stream;
89*4882a593Smuzhiyun 	struct cmp_connection out_conn;
90*4882a593Smuzhiyun 	struct cmp_connection in_conn;
91*4882a593Smuzhiyun 	unsigned int substreams_counter;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	/* hardware metering parameters */
94*4882a593Smuzhiyun 	unsigned int phys_out;
95*4882a593Smuzhiyun 	unsigned int phys_in;
96*4882a593Smuzhiyun 	unsigned int phys_out_grp_count;
97*4882a593Smuzhiyun 	unsigned int phys_in_grp_count;
98*4882a593Smuzhiyun 	struct snd_efw_phys_grp phys_out_grps[HWINFO_MAX_CAPS_GROUPS];
99*4882a593Smuzhiyun 	struct snd_efw_phys_grp phys_in_grps[HWINFO_MAX_CAPS_GROUPS];
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	/* for uapi */
102*4882a593Smuzhiyun 	int dev_lock_count;
103*4882a593Smuzhiyun 	bool dev_lock_changed;
104*4882a593Smuzhiyun 	wait_queue_head_t hwdep_wait;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	/* response queue */
107*4882a593Smuzhiyun 	u8 *resp_buf;
108*4882a593Smuzhiyun 	u8 *pull_ptr;
109*4882a593Smuzhiyun 	u8 *push_ptr;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	struct amdtp_domain domain;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun int snd_efw_transaction_cmd(struct fw_unit *unit,
115*4882a593Smuzhiyun 			    const void *cmd, unsigned int size);
116*4882a593Smuzhiyun int snd_efw_transaction_run(struct fw_unit *unit,
117*4882a593Smuzhiyun 			    const void *cmd, unsigned int cmd_size,
118*4882a593Smuzhiyun 			    void *resp, unsigned int resp_size);
119*4882a593Smuzhiyun int snd_efw_transaction_register(void);
120*4882a593Smuzhiyun void snd_efw_transaction_unregister(void);
121*4882a593Smuzhiyun void snd_efw_transaction_bus_reset(struct fw_unit *unit);
122*4882a593Smuzhiyun void snd_efw_transaction_add_instance(struct snd_efw *efw);
123*4882a593Smuzhiyun void snd_efw_transaction_remove_instance(struct snd_efw *efw);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun struct snd_efw_hwinfo {
126*4882a593Smuzhiyun 	u32 flags;
127*4882a593Smuzhiyun 	u32 guid_hi;
128*4882a593Smuzhiyun 	u32 guid_lo;
129*4882a593Smuzhiyun 	u32 type;
130*4882a593Smuzhiyun 	u32 version;
131*4882a593Smuzhiyun 	char vendor_name[HWINFO_NAME_SIZE_BYTES];
132*4882a593Smuzhiyun 	char model_name[HWINFO_NAME_SIZE_BYTES];
133*4882a593Smuzhiyun 	u32 supported_clocks;
134*4882a593Smuzhiyun 	u32 amdtp_rx_pcm_channels;
135*4882a593Smuzhiyun 	u32 amdtp_tx_pcm_channels;
136*4882a593Smuzhiyun 	u32 phys_out;
137*4882a593Smuzhiyun 	u32 phys_in;
138*4882a593Smuzhiyun 	u32 phys_out_grp_count;
139*4882a593Smuzhiyun 	struct snd_efw_phys_grp phys_out_grps[HWINFO_MAX_CAPS_GROUPS];
140*4882a593Smuzhiyun 	u32 phys_in_grp_count;
141*4882a593Smuzhiyun 	struct snd_efw_phys_grp phys_in_grps[HWINFO_MAX_CAPS_GROUPS];
142*4882a593Smuzhiyun 	u32 midi_out_ports;
143*4882a593Smuzhiyun 	u32 midi_in_ports;
144*4882a593Smuzhiyun 	u32 max_sample_rate;
145*4882a593Smuzhiyun 	u32 min_sample_rate;
146*4882a593Smuzhiyun 	u32 dsp_version;
147*4882a593Smuzhiyun 	u32 arm_version;
148*4882a593Smuzhiyun 	u32 mixer_playback_channels;
149*4882a593Smuzhiyun 	u32 mixer_capture_channels;
150*4882a593Smuzhiyun 	u32 fpga_version;
151*4882a593Smuzhiyun 	u32 amdtp_rx_pcm_channels_2x;
152*4882a593Smuzhiyun 	u32 amdtp_tx_pcm_channels_2x;
153*4882a593Smuzhiyun 	u32 amdtp_rx_pcm_channels_4x;
154*4882a593Smuzhiyun 	u32 amdtp_tx_pcm_channels_4x;
155*4882a593Smuzhiyun 	u32 reserved[16];
156*4882a593Smuzhiyun } __packed;
157*4882a593Smuzhiyun enum snd_efw_grp_type {
158*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_ANALOG			= 0,
159*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_SPDIF			= 1,
160*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_ADAT			= 2,
161*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_SPDIF_OR_ADAT		= 3,
162*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_ANALOG_MIRRORING	= 4,
163*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_HEADPHONES		= 5,
164*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_I2S			= 6,
165*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_GUITAR			= 7,
166*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_PIEZO_GUITAR		= 8,
167*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_GUITAR_STRING		= 9,
168*4882a593Smuzhiyun 	SND_EFW_CH_TYPE_DUMMY
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun struct snd_efw_phys_meters {
171*4882a593Smuzhiyun 	u32 status;	/* guitar state/midi signal/clock input detect */
172*4882a593Smuzhiyun 	u32 reserved0;
173*4882a593Smuzhiyun 	u32 reserved1;
174*4882a593Smuzhiyun 	u32 reserved2;
175*4882a593Smuzhiyun 	u32 reserved3;
176*4882a593Smuzhiyun 	u32 out_meters;
177*4882a593Smuzhiyun 	u32 in_meters;
178*4882a593Smuzhiyun 	u32 reserved4;
179*4882a593Smuzhiyun 	u32 reserved5;
180*4882a593Smuzhiyun 	u32 values[];
181*4882a593Smuzhiyun } __packed;
182*4882a593Smuzhiyun enum snd_efw_clock_source {
183*4882a593Smuzhiyun 	SND_EFW_CLOCK_SOURCE_INTERNAL	= 0,
184*4882a593Smuzhiyun 	SND_EFW_CLOCK_SOURCE_SYTMATCH	= 1,
185*4882a593Smuzhiyun 	SND_EFW_CLOCK_SOURCE_WORDCLOCK	= 2,
186*4882a593Smuzhiyun 	SND_EFW_CLOCK_SOURCE_SPDIF	= 3,
187*4882a593Smuzhiyun 	SND_EFW_CLOCK_SOURCE_ADAT_1	= 4,
188*4882a593Smuzhiyun 	SND_EFW_CLOCK_SOURCE_ADAT_2	= 5,
189*4882a593Smuzhiyun 	SND_EFW_CLOCK_SOURCE_CONTINUOUS	= 6	/* internal variable clock */
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun enum snd_efw_transport_mode {
192*4882a593Smuzhiyun 	SND_EFW_TRANSPORT_MODE_WINDOWS	= 0,
193*4882a593Smuzhiyun 	SND_EFW_TRANSPORT_MODE_IEC61883	= 1,
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun int snd_efw_command_set_resp_addr(struct snd_efw *efw,
196*4882a593Smuzhiyun 				  u16 addr_high, u32 addr_low);
197*4882a593Smuzhiyun int snd_efw_command_set_tx_mode(struct snd_efw *efw,
198*4882a593Smuzhiyun 				enum snd_efw_transport_mode mode);
199*4882a593Smuzhiyun int snd_efw_command_get_hwinfo(struct snd_efw *efw,
200*4882a593Smuzhiyun 			       struct snd_efw_hwinfo *hwinfo);
201*4882a593Smuzhiyun int snd_efw_command_get_phys_meters(struct snd_efw *efw,
202*4882a593Smuzhiyun 				    struct snd_efw_phys_meters *meters,
203*4882a593Smuzhiyun 				    unsigned int len);
204*4882a593Smuzhiyun int snd_efw_command_get_clock_source(struct snd_efw *efw,
205*4882a593Smuzhiyun 				     enum snd_efw_clock_source *source);
206*4882a593Smuzhiyun int snd_efw_command_get_sampling_rate(struct snd_efw *efw, unsigned int *rate);
207*4882a593Smuzhiyun int snd_efw_command_set_sampling_rate(struct snd_efw *efw, unsigned int rate);
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun int snd_efw_stream_init_duplex(struct snd_efw *efw);
210*4882a593Smuzhiyun int snd_efw_stream_reserve_duplex(struct snd_efw *efw, unsigned int rate,
211*4882a593Smuzhiyun 				  unsigned int frames_per_period,
212*4882a593Smuzhiyun 				  unsigned int frames_per_buffer);
213*4882a593Smuzhiyun int snd_efw_stream_start_duplex(struct snd_efw *efw);
214*4882a593Smuzhiyun void snd_efw_stream_stop_duplex(struct snd_efw *efw);
215*4882a593Smuzhiyun void snd_efw_stream_update_duplex(struct snd_efw *efw);
216*4882a593Smuzhiyun void snd_efw_stream_destroy_duplex(struct snd_efw *efw);
217*4882a593Smuzhiyun void snd_efw_stream_lock_changed(struct snd_efw *efw);
218*4882a593Smuzhiyun int snd_efw_stream_lock_try(struct snd_efw *efw);
219*4882a593Smuzhiyun void snd_efw_stream_lock_release(struct snd_efw *efw);
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun void snd_efw_proc_init(struct snd_efw *efw);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun int snd_efw_create_midi_devices(struct snd_efw *efw);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun int snd_efw_create_pcm_devices(struct snd_efw *efw);
226*4882a593Smuzhiyun int snd_efw_get_multiplier_mode(unsigned int sampling_rate, unsigned int *mode);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun int snd_efw_create_hwdep_device(struct snd_efw *efw);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun #define SND_EFW_DEV_ENTRY(vendor, model) \
231*4882a593Smuzhiyun { \
232*4882a593Smuzhiyun 	.match_flags	= IEEE1394_MATCH_VENDOR_ID | \
233*4882a593Smuzhiyun 			  IEEE1394_MATCH_MODEL_ID, \
234*4882a593Smuzhiyun 	.vendor_id	= vendor,\
235*4882a593Smuzhiyun 	.model_id	= model \
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun #endif
239