xref: /OK3568_Linux_fs/kernel/sound/firewire/fireface/ff-protocol-latter.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // ff-protocol-latter - a part of driver for RME Fireface series
3*4882a593Smuzhiyun //
4*4882a593Smuzhiyun // Copyright (c) 2019 Takashi Sakamoto
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // Licensed under the terms of the GNU General Public License, version 2.
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include "ff.h"
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define LATTER_STF		0xffff00000004ULL
13*4882a593Smuzhiyun #define LATTER_ISOC_CHANNELS	0xffff00000008ULL
14*4882a593Smuzhiyun #define LATTER_ISOC_START	0xffff0000000cULL
15*4882a593Smuzhiyun #define LATTER_FETCH_MODE	0xffff00000010ULL
16*4882a593Smuzhiyun #define LATTER_SYNC_STATUS	0x0000801c0000ULL
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun // The content of sync status register differs between models.
19*4882a593Smuzhiyun //
20*4882a593Smuzhiyun // Fireface UCX:
21*4882a593Smuzhiyun //  0xf0000000: (unidentified)
22*4882a593Smuzhiyun //  0x0f000000: effective rate of sampling clock
23*4882a593Smuzhiyun //  0x00f00000: detected rate of word clock on BNC interface
24*4882a593Smuzhiyun //  0x000f0000: detected rate of ADAT or S/PDIF on optical interface
25*4882a593Smuzhiyun //  0x0000f000: detected rate of S/PDIF on coaxial interface
26*4882a593Smuzhiyun //  0x00000e00: effective source of sampling clock
27*4882a593Smuzhiyun //    0x00000e00: Internal
28*4882a593Smuzhiyun //    0x00000800: (unidentified)
29*4882a593Smuzhiyun //    0x00000600: Word clock on BNC interface
30*4882a593Smuzhiyun //    0x00000400: ADAT on optical interface
31*4882a593Smuzhiyun //    0x00000200: S/PDIF on coaxial or optical interface
32*4882a593Smuzhiyun //  0x00000100: Optical interface is used for ADAT signal
33*4882a593Smuzhiyun //  0x00000080: (unidentified)
34*4882a593Smuzhiyun //  0x00000040: Synchronized to word clock on BNC interface
35*4882a593Smuzhiyun //  0x00000020: Synchronized to ADAT or S/PDIF on optical interface
36*4882a593Smuzhiyun //  0x00000010: Synchronized to S/PDIF on coaxial interface
37*4882a593Smuzhiyun //  0x00000008: (unidentified)
38*4882a593Smuzhiyun //  0x00000004: Lock word clock on BNC interface
39*4882a593Smuzhiyun //  0x00000002: Lock ADAT or S/PDIF on optical interface
40*4882a593Smuzhiyun //  0x00000001: Lock S/PDIF on coaxial interface
41*4882a593Smuzhiyun //
42*4882a593Smuzhiyun // Fireface 802 (and perhaps UFX):
43*4882a593Smuzhiyun //   0xf0000000: effective rate of sampling clock
44*4882a593Smuzhiyun //   0x0f000000: detected rate of ADAT-B on 2nd optical interface
45*4882a593Smuzhiyun //   0x00f00000: detected rate of ADAT-A on 1st optical interface
46*4882a593Smuzhiyun //   0x000f0000: detected rate of AES/EBU on XLR or coaxial interface
47*4882a593Smuzhiyun //   0x0000f000: detected rate of word clock on BNC interface
48*4882a593Smuzhiyun //   0x00000e00: effective source of sampling clock
49*4882a593Smuzhiyun //     0x00000e00: internal
50*4882a593Smuzhiyun //     0x00000800: ADAT-B
51*4882a593Smuzhiyun //     0x00000600: ADAT-A
52*4882a593Smuzhiyun //     0x00000400: AES/EBU
53*4882a593Smuzhiyun //     0x00000200: Word clock
54*4882a593Smuzhiyun //   0x00000080: Synchronized to ADAT-B on 2nd optical interface
55*4882a593Smuzhiyun //   0x00000040: Synchronized to ADAT-A on 1st optical interface
56*4882a593Smuzhiyun //   0x00000020: Synchronized to AES/EBU on XLR or 2nd optical interface
57*4882a593Smuzhiyun //   0x00000010: Synchronized to word clock on BNC interface
58*4882a593Smuzhiyun //   0x00000008: Lock ADAT-B on 2nd optical interface
59*4882a593Smuzhiyun //   0x00000004: Lock ADAT-A on 1st optical interface
60*4882a593Smuzhiyun //   0x00000002: Lock AES/EBU on XLR or 2nd optical interface
61*4882a593Smuzhiyun //   0x00000001: Lock word clock on BNC interface
62*4882a593Smuzhiyun //
63*4882a593Smuzhiyun // The pattern for rate bits:
64*4882a593Smuzhiyun //   0x00: 32.0 kHz
65*4882a593Smuzhiyun //   0x01: 44.1 kHz
66*4882a593Smuzhiyun //   0x02: 48.0 kHz
67*4882a593Smuzhiyun //   0x04: 64.0 kHz
68*4882a593Smuzhiyun //   0x05: 88.2 kHz
69*4882a593Smuzhiyun //   0x06: 96.0 kHz
70*4882a593Smuzhiyun //   0x08: 128.0 kHz
71*4882a593Smuzhiyun //   0x09: 176.4 kHz
72*4882a593Smuzhiyun //   0x0a: 192.0 kHz
parse_clock_bits(u32 data,unsigned int * rate,enum snd_ff_clock_src * src,enum snd_ff_unit_version unit_version)73*4882a593Smuzhiyun static int parse_clock_bits(u32 data, unsigned int *rate,
74*4882a593Smuzhiyun 			    enum snd_ff_clock_src *src,
75*4882a593Smuzhiyun 			    enum snd_ff_unit_version unit_version)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	static const struct {
78*4882a593Smuzhiyun 		unsigned int rate;
79*4882a593Smuzhiyun 		u32 flag;
80*4882a593Smuzhiyun 	} *rate_entry, rate_entries[] = {
81*4882a593Smuzhiyun 		{ 32000,	0x00, },
82*4882a593Smuzhiyun 		{ 44100,	0x01, },
83*4882a593Smuzhiyun 		{ 48000,	0x02, },
84*4882a593Smuzhiyun 		{ 64000,	0x04, },
85*4882a593Smuzhiyun 		{ 88200,	0x05, },
86*4882a593Smuzhiyun 		{ 96000,	0x06, },
87*4882a593Smuzhiyun 		{ 128000,	0x08, },
88*4882a593Smuzhiyun 		{ 176400,	0x09, },
89*4882a593Smuzhiyun 		{ 192000,	0x0a, },
90*4882a593Smuzhiyun 	};
91*4882a593Smuzhiyun 	static const struct {
92*4882a593Smuzhiyun 		enum snd_ff_clock_src src;
93*4882a593Smuzhiyun 		u32 flag;
94*4882a593Smuzhiyun 	} *clk_entry, *clk_entries, ucx_clk_entries[] = {
95*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_SPDIF,	0x00000200, },
96*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_ADAT1,	0x00000400, },
97*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_WORD,	0x00000600, },
98*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_INTERNAL,	0x00000e00, },
99*4882a593Smuzhiyun 	}, ufx_ff802_clk_entries[] = {
100*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_WORD,	0x00000200, },
101*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_SPDIF,	0x00000400, },
102*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_ADAT1,	0x00000600, },
103*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_ADAT2,	0x00000800, },
104*4882a593Smuzhiyun 		{ SND_FF_CLOCK_SRC_INTERNAL,	0x00000e00, },
105*4882a593Smuzhiyun 	};
106*4882a593Smuzhiyun 	u32 rate_bits;
107*4882a593Smuzhiyun 	unsigned int clk_entry_count;
108*4882a593Smuzhiyun 	int i;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	if (unit_version == SND_FF_UNIT_VERSION_UCX) {
111*4882a593Smuzhiyun 		rate_bits = (data & 0x0f000000) >> 24;
112*4882a593Smuzhiyun 		clk_entries = ucx_clk_entries;
113*4882a593Smuzhiyun 		clk_entry_count = ARRAY_SIZE(ucx_clk_entries);
114*4882a593Smuzhiyun 	} else {
115*4882a593Smuzhiyun 		rate_bits = (data & 0xf0000000) >> 28;
116*4882a593Smuzhiyun 		clk_entries = ufx_ff802_clk_entries;
117*4882a593Smuzhiyun 		clk_entry_count = ARRAY_SIZE(ufx_ff802_clk_entries);
118*4882a593Smuzhiyun 	}
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
121*4882a593Smuzhiyun 		rate_entry = rate_entries + i;
122*4882a593Smuzhiyun 		if (rate_bits == rate_entry->flag) {
123*4882a593Smuzhiyun 			*rate = rate_entry->rate;
124*4882a593Smuzhiyun 			break;
125*4882a593Smuzhiyun 		}
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun 	if (i == ARRAY_SIZE(rate_entries))
128*4882a593Smuzhiyun 		return -EIO;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	for (i = 0; i < clk_entry_count; ++i) {
131*4882a593Smuzhiyun 		clk_entry = clk_entries + i;
132*4882a593Smuzhiyun 		if ((data & 0x000e00) == clk_entry->flag) {
133*4882a593Smuzhiyun 			*src = clk_entry->src;
134*4882a593Smuzhiyun 			break;
135*4882a593Smuzhiyun 		}
136*4882a593Smuzhiyun 	}
137*4882a593Smuzhiyun 	if (i == clk_entry_count)
138*4882a593Smuzhiyun 		return -EIO;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
latter_get_clock(struct snd_ff * ff,unsigned int * rate,enum snd_ff_clock_src * src)143*4882a593Smuzhiyun static int latter_get_clock(struct snd_ff *ff, unsigned int *rate,
144*4882a593Smuzhiyun 			   enum snd_ff_clock_src *src)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	__le32 reg;
147*4882a593Smuzhiyun 	u32 data;
148*4882a593Smuzhiyun 	int err;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
151*4882a593Smuzhiyun 				 LATTER_SYNC_STATUS, &reg, sizeof(reg), 0);
152*4882a593Smuzhiyun 	if (err < 0)
153*4882a593Smuzhiyun 		return err;
154*4882a593Smuzhiyun 	data = le32_to_cpu(reg);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	return parse_clock_bits(data, rate, src, ff->unit_version);
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
latter_switch_fetching_mode(struct snd_ff * ff,bool enable)159*4882a593Smuzhiyun static int latter_switch_fetching_mode(struct snd_ff *ff, bool enable)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	u32 data;
162*4882a593Smuzhiyun 	__le32 reg;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	if (enable)
165*4882a593Smuzhiyun 		data = 0x00000000;
166*4882a593Smuzhiyun 	else
167*4882a593Smuzhiyun 		data = 0xffffffff;
168*4882a593Smuzhiyun 	reg = cpu_to_le32(data);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
171*4882a593Smuzhiyun 				  LATTER_FETCH_MODE, &reg, sizeof(reg), 0);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
latter_allocate_resources(struct snd_ff * ff,unsigned int rate)174*4882a593Smuzhiyun static int latter_allocate_resources(struct snd_ff *ff, unsigned int rate)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	enum snd_ff_stream_mode mode;
177*4882a593Smuzhiyun 	unsigned int code;
178*4882a593Smuzhiyun 	__le32 reg;
179*4882a593Smuzhiyun 	unsigned int count;
180*4882a593Smuzhiyun 	int i;
181*4882a593Smuzhiyun 	int err;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	// Set the number of data blocks transferred in a second.
184*4882a593Smuzhiyun 	if (rate % 48000 == 0)
185*4882a593Smuzhiyun 		code = 0x04;
186*4882a593Smuzhiyun 	else if (rate % 44100 == 0)
187*4882a593Smuzhiyun 		code = 0x02;
188*4882a593Smuzhiyun 	else if (rate % 32000 == 0)
189*4882a593Smuzhiyun 		code = 0x00;
190*4882a593Smuzhiyun 	else
191*4882a593Smuzhiyun 		return -EINVAL;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	if (rate >= 64000 && rate < 128000)
194*4882a593Smuzhiyun 		code |= 0x08;
195*4882a593Smuzhiyun 	else if (rate >= 128000)
196*4882a593Smuzhiyun 		code |= 0x10;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	reg = cpu_to_le32(code);
199*4882a593Smuzhiyun 	err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
200*4882a593Smuzhiyun 				 LATTER_STF, &reg, sizeof(reg), 0);
201*4882a593Smuzhiyun 	if (err < 0)
202*4882a593Smuzhiyun 		return err;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	// Confirm to shift transmission clock.
205*4882a593Smuzhiyun 	count = 0;
206*4882a593Smuzhiyun 	while (count++ < 10) {
207*4882a593Smuzhiyun 		unsigned int curr_rate;
208*4882a593Smuzhiyun 		enum snd_ff_clock_src src;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 		err = latter_get_clock(ff, &curr_rate, &src);
211*4882a593Smuzhiyun 		if (err < 0)
212*4882a593Smuzhiyun 			return err;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 		if (curr_rate == rate)
215*4882a593Smuzhiyun 			break;
216*4882a593Smuzhiyun 	}
217*4882a593Smuzhiyun 	if (count > 10)
218*4882a593Smuzhiyun 		return -ETIMEDOUT;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(amdtp_rate_table); ++i) {
221*4882a593Smuzhiyun 		if (rate == amdtp_rate_table[i])
222*4882a593Smuzhiyun 			break;
223*4882a593Smuzhiyun 	}
224*4882a593Smuzhiyun 	if (i == ARRAY_SIZE(amdtp_rate_table))
225*4882a593Smuzhiyun 		return -EINVAL;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	err = snd_ff_stream_get_multiplier_mode(i, &mode);
228*4882a593Smuzhiyun 	if (err < 0)
229*4882a593Smuzhiyun 		return err;
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	// Keep resources for in-stream.
232*4882a593Smuzhiyun 	ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
233*4882a593Smuzhiyun 	err = fw_iso_resources_allocate(&ff->tx_resources,
234*4882a593Smuzhiyun 			amdtp_stream_get_max_payload(&ff->tx_stream),
235*4882a593Smuzhiyun 			fw_parent_device(ff->unit)->max_speed);
236*4882a593Smuzhiyun 	if (err < 0)
237*4882a593Smuzhiyun 		return err;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	// Keep resources for out-stream.
240*4882a593Smuzhiyun 	ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
241*4882a593Smuzhiyun 	err = fw_iso_resources_allocate(&ff->rx_resources,
242*4882a593Smuzhiyun 			amdtp_stream_get_max_payload(&ff->rx_stream),
243*4882a593Smuzhiyun 			fw_parent_device(ff->unit)->max_speed);
244*4882a593Smuzhiyun 	if (err < 0)
245*4882a593Smuzhiyun 		fw_iso_resources_free(&ff->tx_resources);
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	return err;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
latter_begin_session(struct snd_ff * ff,unsigned int rate)250*4882a593Smuzhiyun static int latter_begin_session(struct snd_ff *ff, unsigned int rate)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	unsigned int generation = ff->rx_resources.generation;
253*4882a593Smuzhiyun 	unsigned int flag;
254*4882a593Smuzhiyun 	u32 data;
255*4882a593Smuzhiyun 	__le32 reg;
256*4882a593Smuzhiyun 	int err;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	if (ff->unit_version == SND_FF_UNIT_VERSION_UCX) {
259*4882a593Smuzhiyun 		// For Fireface UCX. Always use the maximum number of data
260*4882a593Smuzhiyun 		// channels in data block of packet.
261*4882a593Smuzhiyun 		if (rate >= 32000 && rate <= 48000)
262*4882a593Smuzhiyun 			flag = 0x92;
263*4882a593Smuzhiyun 		else if (rate >= 64000 && rate <= 96000)
264*4882a593Smuzhiyun 			flag = 0x8e;
265*4882a593Smuzhiyun 		else if (rate >= 128000 && rate <= 192000)
266*4882a593Smuzhiyun 			flag = 0x8c;
267*4882a593Smuzhiyun 		else
268*4882a593Smuzhiyun 			return -EINVAL;
269*4882a593Smuzhiyun 	} else {
270*4882a593Smuzhiyun 		// For Fireface UFX and 802. Due to bandwidth limitation on
271*4882a593Smuzhiyun 		// IEEE 1394a (400 Mbps), Analog 1-12 and AES are available
272*4882a593Smuzhiyun 		// without any ADAT at quadruple speed.
273*4882a593Smuzhiyun 		if (rate >= 32000 && rate <= 48000)
274*4882a593Smuzhiyun 			flag = 0x9e;
275*4882a593Smuzhiyun 		else if (rate >= 64000 && rate <= 96000)
276*4882a593Smuzhiyun 			flag = 0x96;
277*4882a593Smuzhiyun 		else if (rate >= 128000 && rate <= 192000)
278*4882a593Smuzhiyun 			flag = 0x8e;
279*4882a593Smuzhiyun 		else
280*4882a593Smuzhiyun 			return -EINVAL;
281*4882a593Smuzhiyun 	}
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	if (generation != fw_parent_device(ff->unit)->card->generation) {
284*4882a593Smuzhiyun 		err = fw_iso_resources_update(&ff->tx_resources);
285*4882a593Smuzhiyun 		if (err < 0)
286*4882a593Smuzhiyun 			return err;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 		err = fw_iso_resources_update(&ff->rx_resources);
289*4882a593Smuzhiyun 		if (err < 0)
290*4882a593Smuzhiyun 			return err;
291*4882a593Smuzhiyun 	}
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	data = (ff->tx_resources.channel << 8) | ff->rx_resources.channel;
294*4882a593Smuzhiyun 	reg = cpu_to_le32(data);
295*4882a593Smuzhiyun 	err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
296*4882a593Smuzhiyun 				 LATTER_ISOC_CHANNELS, &reg, sizeof(reg), 0);
297*4882a593Smuzhiyun 	if (err < 0)
298*4882a593Smuzhiyun 		return err;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	reg = cpu_to_le32(flag);
301*4882a593Smuzhiyun 	return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
302*4882a593Smuzhiyun 				  LATTER_ISOC_START, &reg, sizeof(reg), 0);
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun 
latter_finish_session(struct snd_ff * ff)305*4882a593Smuzhiyun static void latter_finish_session(struct snd_ff *ff)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun 	__le32 reg;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	reg = cpu_to_le32(0x00000000);
310*4882a593Smuzhiyun 	snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
311*4882a593Smuzhiyun 			   LATTER_ISOC_START, &reg, sizeof(reg), 0);
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
latter_dump_status(struct snd_ff * ff,struct snd_info_buffer * buffer)314*4882a593Smuzhiyun static void latter_dump_status(struct snd_ff *ff, struct snd_info_buffer *buffer)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun 	static const struct {
317*4882a593Smuzhiyun 		char *const label;
318*4882a593Smuzhiyun 		u32 locked_mask;
319*4882a593Smuzhiyun 		u32 synced_mask;
320*4882a593Smuzhiyun 	} *clk_entry, *clk_entries, ucx_clk_entries[] = {
321*4882a593Smuzhiyun 		{ "S/PDIF",	0x00000001, 0x00000010, },
322*4882a593Smuzhiyun 		{ "ADAT",	0x00000002, 0x00000020, },
323*4882a593Smuzhiyun 		{ "WDClk",	0x00000004, 0x00000040, },
324*4882a593Smuzhiyun 	}, ufx_ff802_clk_entries[] = {
325*4882a593Smuzhiyun 		{ "WDClk",	0x00000001, 0x00000010, },
326*4882a593Smuzhiyun 		{ "AES/EBU",	0x00000002, 0x00000020, },
327*4882a593Smuzhiyun 		{ "ADAT-A",	0x00000004, 0x00000040, },
328*4882a593Smuzhiyun 		{ "ADAT-B",	0x00000008, 0x00000080, },
329*4882a593Smuzhiyun 	};
330*4882a593Smuzhiyun 	__le32 reg;
331*4882a593Smuzhiyun 	u32 data;
332*4882a593Smuzhiyun 	unsigned int rate;
333*4882a593Smuzhiyun 	enum snd_ff_clock_src src;
334*4882a593Smuzhiyun 	const char *label;
335*4882a593Smuzhiyun 	unsigned int clk_entry_count;
336*4882a593Smuzhiyun 	int i;
337*4882a593Smuzhiyun 	int err;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
340*4882a593Smuzhiyun 				 LATTER_SYNC_STATUS, &reg, sizeof(reg), 0);
341*4882a593Smuzhiyun 	if (err < 0)
342*4882a593Smuzhiyun 		return;
343*4882a593Smuzhiyun 	data = le32_to_cpu(reg);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	snd_iprintf(buffer, "External source detection:\n");
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	if (ff->unit_version == SND_FF_UNIT_VERSION_UCX) {
348*4882a593Smuzhiyun 		clk_entries = ucx_clk_entries;
349*4882a593Smuzhiyun 		clk_entry_count = ARRAY_SIZE(ucx_clk_entries);
350*4882a593Smuzhiyun 	} else {
351*4882a593Smuzhiyun 		clk_entries = ufx_ff802_clk_entries;
352*4882a593Smuzhiyun 		clk_entry_count = ARRAY_SIZE(ufx_ff802_clk_entries);
353*4882a593Smuzhiyun 	}
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	for (i = 0; i < clk_entry_count; ++i) {
356*4882a593Smuzhiyun 		clk_entry = clk_entries + i;
357*4882a593Smuzhiyun 		snd_iprintf(buffer, "%s: ", clk_entry->label);
358*4882a593Smuzhiyun 		if (data & clk_entry->locked_mask) {
359*4882a593Smuzhiyun 			if (data & clk_entry->synced_mask)
360*4882a593Smuzhiyun 				snd_iprintf(buffer, "sync\n");
361*4882a593Smuzhiyun 			else
362*4882a593Smuzhiyun 				snd_iprintf(buffer, "lock\n");
363*4882a593Smuzhiyun 		} else {
364*4882a593Smuzhiyun 			snd_iprintf(buffer, "none\n");
365*4882a593Smuzhiyun 		}
366*4882a593Smuzhiyun 	}
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	err = parse_clock_bits(data, &rate, &src, ff->unit_version);
369*4882a593Smuzhiyun 	if (err < 0)
370*4882a593Smuzhiyun 		return;
371*4882a593Smuzhiyun 	label = snd_ff_proc_get_clk_label(src);
372*4882a593Smuzhiyun 	if (!label)
373*4882a593Smuzhiyun 		return;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	snd_iprintf(buffer, "Referred clock: %s %d\n", label, rate);
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun // NOTE: transactions are transferred within 0x00-0x7f in allocated range of
379*4882a593Smuzhiyun // address. This seems to be for check of discontinuity in receiver side.
380*4882a593Smuzhiyun //
381*4882a593Smuzhiyun // Like Fireface 400, drivers can select one of 4 options for lower 4 bytes of
382*4882a593Smuzhiyun // destination address by bit flags in quadlet register (little endian) at
383*4882a593Smuzhiyun // 0x'ffff'0000'0014:
384*4882a593Smuzhiyun //
385*4882a593Smuzhiyun // bit flags: offset of destination address
386*4882a593Smuzhiyun // - 0x00002000: 0x'....'....'0000'0000
387*4882a593Smuzhiyun // - 0x00004000: 0x'....'....'0000'0080
388*4882a593Smuzhiyun // - 0x00008000: 0x'....'....'0000'0100
389*4882a593Smuzhiyun // - 0x00010000: 0x'....'....'0000'0180
390*4882a593Smuzhiyun //
391*4882a593Smuzhiyun // Drivers can suppress the device to transfer asynchronous transactions by
392*4882a593Smuzhiyun // clear these bit flags.
393*4882a593Smuzhiyun //
394*4882a593Smuzhiyun // Actually, the register is write-only and includes the other settings such as
395*4882a593Smuzhiyun // input attenuation. This driver allocates for the first option
396*4882a593Smuzhiyun // (0x'....'....'0000'0000) and expects userspace application to configure the
397*4882a593Smuzhiyun // register for it.
latter_handle_midi_msg(struct snd_ff * ff,unsigned int offset,__le32 * buf,size_t length)398*4882a593Smuzhiyun static void latter_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
399*4882a593Smuzhiyun 				   __le32 *buf, size_t length)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun 	u32 data = le32_to_cpu(*buf);
402*4882a593Smuzhiyun 	unsigned int index = (data & 0x000000f0) >> 4;
403*4882a593Smuzhiyun 	u8 byte[3];
404*4882a593Smuzhiyun 	struct snd_rawmidi_substream *substream;
405*4882a593Smuzhiyun 	unsigned int len;
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	if (index >= ff->spec->midi_in_ports)
408*4882a593Smuzhiyun 		return;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	switch (data & 0x0000000f) {
411*4882a593Smuzhiyun 	case 0x00000008:
412*4882a593Smuzhiyun 	case 0x00000009:
413*4882a593Smuzhiyun 	case 0x0000000a:
414*4882a593Smuzhiyun 	case 0x0000000b:
415*4882a593Smuzhiyun 	case 0x0000000e:
416*4882a593Smuzhiyun 		len = 3;
417*4882a593Smuzhiyun 		break;
418*4882a593Smuzhiyun 	case 0x0000000c:
419*4882a593Smuzhiyun 	case 0x0000000d:
420*4882a593Smuzhiyun 		len = 2;
421*4882a593Smuzhiyun 		break;
422*4882a593Smuzhiyun 	default:
423*4882a593Smuzhiyun 		len = data & 0x00000003;
424*4882a593Smuzhiyun 		if (len == 0)
425*4882a593Smuzhiyun 			len = 3;
426*4882a593Smuzhiyun 		break;
427*4882a593Smuzhiyun 	}
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	byte[0] = (data & 0x0000ff00) >> 8;
430*4882a593Smuzhiyun 	byte[1] = (data & 0x00ff0000) >> 16;
431*4882a593Smuzhiyun 	byte[2] = (data & 0xff000000) >> 24;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	substream = READ_ONCE(ff->tx_midi_substreams[index]);
434*4882a593Smuzhiyun 	if (substream)
435*4882a593Smuzhiyun 		snd_rawmidi_receive(substream, byte, len);
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun /*
439*4882a593Smuzhiyun  * When return minus value, given argument is not MIDI status.
440*4882a593Smuzhiyun  * When return 0, given argument is a beginning of system exclusive.
441*4882a593Smuzhiyun  * When return the others, given argument is MIDI data.
442*4882a593Smuzhiyun  */
calculate_message_bytes(u8 status)443*4882a593Smuzhiyun static inline int calculate_message_bytes(u8 status)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun 	switch (status) {
446*4882a593Smuzhiyun 	case 0xf6:	/* Tune request. */
447*4882a593Smuzhiyun 	case 0xf8:	/* Timing clock. */
448*4882a593Smuzhiyun 	case 0xfa:	/* Start. */
449*4882a593Smuzhiyun 	case 0xfb:	/* Continue. */
450*4882a593Smuzhiyun 	case 0xfc:	/* Stop. */
451*4882a593Smuzhiyun 	case 0xfe:	/* Active sensing. */
452*4882a593Smuzhiyun 	case 0xff:	/* System reset. */
453*4882a593Smuzhiyun 		return 1;
454*4882a593Smuzhiyun 	case 0xf1:	/* MIDI time code quarter frame. */
455*4882a593Smuzhiyun 	case 0xf3:	/* Song select. */
456*4882a593Smuzhiyun 		return 2;
457*4882a593Smuzhiyun 	case 0xf2:	/* Song position pointer. */
458*4882a593Smuzhiyun 		return 3;
459*4882a593Smuzhiyun 	case 0xf0:	/* Exclusive. */
460*4882a593Smuzhiyun 		return 0;
461*4882a593Smuzhiyun 	case 0xf7:	/* End of exclusive. */
462*4882a593Smuzhiyun 		break;
463*4882a593Smuzhiyun 	case 0xf4:	/* Undefined. */
464*4882a593Smuzhiyun 	case 0xf5:	/* Undefined. */
465*4882a593Smuzhiyun 	case 0xf9:	/* Undefined. */
466*4882a593Smuzhiyun 	case 0xfd:	/* Undefined. */
467*4882a593Smuzhiyun 		break;
468*4882a593Smuzhiyun 	default:
469*4882a593Smuzhiyun 		switch (status & 0xf0) {
470*4882a593Smuzhiyun 		case 0x80:	/* Note on. */
471*4882a593Smuzhiyun 		case 0x90:	/* Note off. */
472*4882a593Smuzhiyun 		case 0xa0:	/* Polyphonic key pressure. */
473*4882a593Smuzhiyun 		case 0xb0:	/* Control change and Mode change. */
474*4882a593Smuzhiyun 		case 0xe0:	/* Pitch bend change. */
475*4882a593Smuzhiyun 			return 3;
476*4882a593Smuzhiyun 		case 0xc0:	/* Program change. */
477*4882a593Smuzhiyun 		case 0xd0:	/* Channel pressure. */
478*4882a593Smuzhiyun 			return 2;
479*4882a593Smuzhiyun 		default:
480*4882a593Smuzhiyun 		break;
481*4882a593Smuzhiyun 		}
482*4882a593Smuzhiyun 	break;
483*4882a593Smuzhiyun 	}
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	return -EINVAL;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun 
latter_fill_midi_msg(struct snd_ff * ff,struct snd_rawmidi_substream * substream,unsigned int port)488*4882a593Smuzhiyun static int latter_fill_midi_msg(struct snd_ff *ff,
489*4882a593Smuzhiyun 				struct snd_rawmidi_substream *substream,
490*4882a593Smuzhiyun 				unsigned int port)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun 	u32 data = {0};
493*4882a593Smuzhiyun 	u8 *buf = (u8 *)&data;
494*4882a593Smuzhiyun 	int consumed;
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	buf[0] = port << 4;
497*4882a593Smuzhiyun 	consumed = snd_rawmidi_transmit_peek(substream, buf + 1, 3);
498*4882a593Smuzhiyun 	if (consumed <= 0)
499*4882a593Smuzhiyun 		return consumed;
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	if (!ff->on_sysex[port]) {
502*4882a593Smuzhiyun 		if (buf[1] != 0xf0) {
503*4882a593Smuzhiyun 			if (consumed < calculate_message_bytes(buf[1]))
504*4882a593Smuzhiyun 				return 0;
505*4882a593Smuzhiyun 		} else {
506*4882a593Smuzhiyun 			// The beginning of exclusives.
507*4882a593Smuzhiyun 			ff->on_sysex[port] = true;
508*4882a593Smuzhiyun 		}
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 		buf[0] |= consumed;
511*4882a593Smuzhiyun 	} else {
512*4882a593Smuzhiyun 		if (buf[1] != 0xf7) {
513*4882a593Smuzhiyun 			if (buf[2] == 0xf7 || buf[3] == 0xf7) {
514*4882a593Smuzhiyun 				// Transfer end code at next time.
515*4882a593Smuzhiyun 				consumed -= 1;
516*4882a593Smuzhiyun 			}
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 			buf[0] |= consumed;
519*4882a593Smuzhiyun 		} else {
520*4882a593Smuzhiyun 			// The end of exclusives.
521*4882a593Smuzhiyun 			ff->on_sysex[port] = false;
522*4882a593Smuzhiyun 			consumed = 1;
523*4882a593Smuzhiyun 			buf[0] |= 0x0f;
524*4882a593Smuzhiyun 		}
525*4882a593Smuzhiyun 	}
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	ff->msg_buf[port][0] = cpu_to_le32(data);
528*4882a593Smuzhiyun 	ff->rx_bytes[port] = consumed;
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	return 1;
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun const struct snd_ff_protocol snd_ff_protocol_latter = {
534*4882a593Smuzhiyun 	.handle_midi_msg	= latter_handle_midi_msg,
535*4882a593Smuzhiyun 	.fill_midi_msg		= latter_fill_midi_msg,
536*4882a593Smuzhiyun 	.get_clock		= latter_get_clock,
537*4882a593Smuzhiyun 	.switch_fetching_mode	= latter_switch_fetching_mode,
538*4882a593Smuzhiyun 	.allocate_resources	= latter_allocate_resources,
539*4882a593Smuzhiyun 	.begin_session		= latter_begin_session,
540*4882a593Smuzhiyun 	.finish_session		= latter_finish_session,
541*4882a593Smuzhiyun 	.dump_status		= latter_dump_status,
542*4882a593Smuzhiyun };
543