1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * digi00x.h - a part of driver for Digidesign Digi 002/003 family 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2014-2015 Takashi Sakamoto 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef SOUND_DIGI00X_H_INCLUDED 9*4882a593Smuzhiyun #define SOUND_DIGI00X_H_INCLUDED 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/compat.h> 12*4882a593Smuzhiyun #include <linux/device.h> 13*4882a593Smuzhiyun #include <linux/firewire.h> 14*4882a593Smuzhiyun #include <linux/module.h> 15*4882a593Smuzhiyun #include <linux/mod_devicetable.h> 16*4882a593Smuzhiyun #include <linux/delay.h> 17*4882a593Smuzhiyun #include <linux/slab.h> 18*4882a593Smuzhiyun #include <linux/sched/signal.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <sound/core.h> 21*4882a593Smuzhiyun #include <sound/initval.h> 22*4882a593Smuzhiyun #include <sound/info.h> 23*4882a593Smuzhiyun #include <sound/pcm.h> 24*4882a593Smuzhiyun #include <sound/pcm_params.h> 25*4882a593Smuzhiyun #include <sound/firewire.h> 26*4882a593Smuzhiyun #include <sound/hwdep.h> 27*4882a593Smuzhiyun #include <sound/rawmidi.h> 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #include "../lib.h" 30*4882a593Smuzhiyun #include "../iso-resources.h" 31*4882a593Smuzhiyun #include "../amdtp-stream.h" 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct snd_dg00x { 34*4882a593Smuzhiyun struct snd_card *card; 35*4882a593Smuzhiyun struct fw_unit *unit; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct mutex mutex; 38*4882a593Smuzhiyun spinlock_t lock; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun bool registered; 41*4882a593Smuzhiyun struct delayed_work dwork; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct amdtp_stream tx_stream; 44*4882a593Smuzhiyun struct fw_iso_resources tx_resources; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct amdtp_stream rx_stream; 47*4882a593Smuzhiyun struct fw_iso_resources rx_resources; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun unsigned int substreams_counter; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* for uapi */ 52*4882a593Smuzhiyun int dev_lock_count; 53*4882a593Smuzhiyun bool dev_lock_changed; 54*4882a593Smuzhiyun wait_queue_head_t hwdep_wait; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* For asynchronous messages. */ 57*4882a593Smuzhiyun struct fw_address_handler async_handler; 58*4882a593Smuzhiyun u32 msg; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Console models have additional MIDI ports for control surface. */ 61*4882a593Smuzhiyun bool is_console; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct amdtp_domain domain; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define DG00X_ADDR_BASE 0xffffe0000000ull 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define DG00X_OFFSET_STREAMING_STATE 0x0000 69*4882a593Smuzhiyun #define DG00X_OFFSET_STREAMING_SET 0x0004 70*4882a593Smuzhiyun /* unknown but address in host space 0x0008 */ 71*4882a593Smuzhiyun /* For LSB of the address 0x000c */ 72*4882a593Smuzhiyun /* unknown 0x0010 */ 73*4882a593Smuzhiyun #define DG00X_OFFSET_MESSAGE_ADDR 0x0014 74*4882a593Smuzhiyun /* For LSB of the address 0x0018 */ 75*4882a593Smuzhiyun /* unknown 0x001c */ 76*4882a593Smuzhiyun /* unknown 0x0020 */ 77*4882a593Smuzhiyun /* not used 0x0024--0x00ff */ 78*4882a593Smuzhiyun #define DG00X_OFFSET_ISOC_CHANNELS 0x0100 79*4882a593Smuzhiyun /* unknown 0x0104 */ 80*4882a593Smuzhiyun /* unknown 0x0108 */ 81*4882a593Smuzhiyun /* unknown 0x010c */ 82*4882a593Smuzhiyun #define DG00X_OFFSET_LOCAL_RATE 0x0110 83*4882a593Smuzhiyun #define DG00X_OFFSET_EXTERNAL_RATE 0x0114 84*4882a593Smuzhiyun #define DG00X_OFFSET_CLOCK_SOURCE 0x0118 85*4882a593Smuzhiyun #define DG00X_OFFSET_OPT_IFACE_MODE 0x011c 86*4882a593Smuzhiyun /* unknown 0x0120 */ 87*4882a593Smuzhiyun /* Mixer control on/off 0x0124 */ 88*4882a593Smuzhiyun /* unknown 0x0128 */ 89*4882a593Smuzhiyun #define DG00X_OFFSET_DETECT_EXTERNAL 0x012c 90*4882a593Smuzhiyun /* unknown 0x0138 */ 91*4882a593Smuzhiyun #define DG00X_OFFSET_MMC 0x0400 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun enum snd_dg00x_rate { 94*4882a593Smuzhiyun SND_DG00X_RATE_44100 = 0, 95*4882a593Smuzhiyun SND_DG00X_RATE_48000, 96*4882a593Smuzhiyun SND_DG00X_RATE_88200, 97*4882a593Smuzhiyun SND_DG00X_RATE_96000, 98*4882a593Smuzhiyun SND_DG00X_RATE_COUNT, 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun enum snd_dg00x_clock { 102*4882a593Smuzhiyun SND_DG00X_CLOCK_INTERNAL = 0, 103*4882a593Smuzhiyun SND_DG00X_CLOCK_SPDIF, 104*4882a593Smuzhiyun SND_DG00X_CLOCK_ADAT, 105*4882a593Smuzhiyun SND_DG00X_CLOCK_WORD, 106*4882a593Smuzhiyun SND_DG00X_CLOCK_COUNT, 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun enum snd_dg00x_optical_mode { 110*4882a593Smuzhiyun SND_DG00X_OPT_IFACE_MODE_ADAT = 0, 111*4882a593Smuzhiyun SND_DG00X_OPT_IFACE_MODE_SPDIF, 112*4882a593Smuzhiyun SND_DG00X_OPT_IFACE_MODE_COUNT, 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define DOT_MIDI_IN_PORTS 1 116*4882a593Smuzhiyun #define DOT_MIDI_OUT_PORTS 2 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit, 119*4882a593Smuzhiyun enum amdtp_stream_direction dir); 120*4882a593Smuzhiyun int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate, 121*4882a593Smuzhiyun unsigned int pcm_channels); 122*4882a593Smuzhiyun void amdtp_dot_reset(struct amdtp_stream *s); 123*4882a593Smuzhiyun int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s, 124*4882a593Smuzhiyun struct snd_pcm_runtime *runtime); 125*4882a593Smuzhiyun void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port, 126*4882a593Smuzhiyun struct snd_rawmidi_substream *midi); 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun int snd_dg00x_transaction_register(struct snd_dg00x *dg00x); 129*4882a593Smuzhiyun int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x); 130*4882a593Smuzhiyun void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x); 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT]; 133*4882a593Smuzhiyun extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT]; 134*4882a593Smuzhiyun int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x, 135*4882a593Smuzhiyun unsigned int *rate); 136*4882a593Smuzhiyun int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x, 137*4882a593Smuzhiyun unsigned int *rate); 138*4882a593Smuzhiyun int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate); 139*4882a593Smuzhiyun int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x, 140*4882a593Smuzhiyun enum snd_dg00x_clock *clock); 141*4882a593Smuzhiyun int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x, 142*4882a593Smuzhiyun bool *detect); 143*4882a593Smuzhiyun int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x); 144*4882a593Smuzhiyun int snd_dg00x_stream_reserve_duplex(struct snd_dg00x *dg00x, unsigned int rate, 145*4882a593Smuzhiyun unsigned int frames_per_period, 146*4882a593Smuzhiyun unsigned int frames_per_buffer); 147*4882a593Smuzhiyun int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x); 148*4882a593Smuzhiyun void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x); 149*4882a593Smuzhiyun void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x); 150*4882a593Smuzhiyun void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x); 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x); 153*4882a593Smuzhiyun int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x); 154*4882a593Smuzhiyun void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x); 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun void snd_dg00x_proc_init(struct snd_dg00x *dg00x); 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x); 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x); 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x); 163*4882a593Smuzhiyun #endif 164