1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * digi00x-stream.c - a part of driver for Digidesign Digi 002/003 family
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2014-2015 Takashi Sakamoto
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "digi00x.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define CALLBACK_TIMEOUT 500
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT] = {
13*4882a593Smuzhiyun [SND_DG00X_RATE_44100] = 44100,
14*4882a593Smuzhiyun [SND_DG00X_RATE_48000] = 48000,
15*4882a593Smuzhiyun [SND_DG00X_RATE_88200] = 88200,
16*4882a593Smuzhiyun [SND_DG00X_RATE_96000] = 96000,
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* Multi Bit Linear Audio data channels for each sampling transfer frequency. */
20*4882a593Smuzhiyun const unsigned int
21*4882a593Smuzhiyun snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT] = {
22*4882a593Smuzhiyun /* Analog/ADAT/SPDIF */
23*4882a593Smuzhiyun [SND_DG00X_RATE_44100] = (8 + 8 + 2),
24*4882a593Smuzhiyun [SND_DG00X_RATE_48000] = (8 + 8 + 2),
25*4882a593Smuzhiyun /* Analog/SPDIF */
26*4882a593Smuzhiyun [SND_DG00X_RATE_88200] = (8 + 2),
27*4882a593Smuzhiyun [SND_DG00X_RATE_96000] = (8 + 2),
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
snd_dg00x_stream_get_local_rate(struct snd_dg00x * dg00x,unsigned int * rate)30*4882a593Smuzhiyun int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x, unsigned int *rate)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun u32 data;
33*4882a593Smuzhiyun __be32 reg;
34*4882a593Smuzhiyun int err;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST,
37*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_LOCAL_RATE,
38*4882a593Smuzhiyun ®, sizeof(reg), 0);
39*4882a593Smuzhiyun if (err < 0)
40*4882a593Smuzhiyun return err;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun data = be32_to_cpu(reg) & 0x0f;
43*4882a593Smuzhiyun if (data < ARRAY_SIZE(snd_dg00x_stream_rates))
44*4882a593Smuzhiyun *rate = snd_dg00x_stream_rates[data];
45*4882a593Smuzhiyun else
46*4882a593Smuzhiyun err = -EIO;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return err;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
snd_dg00x_stream_set_local_rate(struct snd_dg00x * dg00x,unsigned int rate)51*4882a593Smuzhiyun int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun __be32 reg;
54*4882a593Smuzhiyun unsigned int i;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(snd_dg00x_stream_rates); i++) {
57*4882a593Smuzhiyun if (rate == snd_dg00x_stream_rates[i])
58*4882a593Smuzhiyun break;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun if (i == ARRAY_SIZE(snd_dg00x_stream_rates))
61*4882a593Smuzhiyun return -EINVAL;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun reg = cpu_to_be32(i);
64*4882a593Smuzhiyun return snd_fw_transaction(dg00x->unit, TCODE_WRITE_QUADLET_REQUEST,
65*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_LOCAL_RATE,
66*4882a593Smuzhiyun ®, sizeof(reg), 0);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
snd_dg00x_stream_get_clock(struct snd_dg00x * dg00x,enum snd_dg00x_clock * clock)69*4882a593Smuzhiyun int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x,
70*4882a593Smuzhiyun enum snd_dg00x_clock *clock)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun __be32 reg;
73*4882a593Smuzhiyun int err;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST,
76*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_CLOCK_SOURCE,
77*4882a593Smuzhiyun ®, sizeof(reg), 0);
78*4882a593Smuzhiyun if (err < 0)
79*4882a593Smuzhiyun return err;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun *clock = be32_to_cpu(reg) & 0x0f;
82*4882a593Smuzhiyun if (*clock >= SND_DG00X_CLOCK_COUNT)
83*4882a593Smuzhiyun err = -EIO;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return err;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
snd_dg00x_stream_check_external_clock(struct snd_dg00x * dg00x,bool * detect)88*4882a593Smuzhiyun int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x, bool *detect)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun __be32 reg;
91*4882a593Smuzhiyun int err;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST,
94*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_DETECT_EXTERNAL,
95*4882a593Smuzhiyun ®, sizeof(reg), 0);
96*4882a593Smuzhiyun if (err >= 0)
97*4882a593Smuzhiyun *detect = be32_to_cpu(reg) > 0;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return err;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
snd_dg00x_stream_get_external_rate(struct snd_dg00x * dg00x,unsigned int * rate)102*4882a593Smuzhiyun int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x,
103*4882a593Smuzhiyun unsigned int *rate)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun u32 data;
106*4882a593Smuzhiyun __be32 reg;
107*4882a593Smuzhiyun int err;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST,
110*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_EXTERNAL_RATE,
111*4882a593Smuzhiyun ®, sizeof(reg), 0);
112*4882a593Smuzhiyun if (err < 0)
113*4882a593Smuzhiyun return err;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun data = be32_to_cpu(reg) & 0x0f;
116*4882a593Smuzhiyun if (data < ARRAY_SIZE(snd_dg00x_stream_rates))
117*4882a593Smuzhiyun *rate = snd_dg00x_stream_rates[data];
118*4882a593Smuzhiyun /* This means desync. */
119*4882a593Smuzhiyun else
120*4882a593Smuzhiyun err = -EBUSY;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return err;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
finish_session(struct snd_dg00x * dg00x)125*4882a593Smuzhiyun static void finish_session(struct snd_dg00x *dg00x)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun __be32 data;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun data = cpu_to_be32(0x00000003);
130*4882a593Smuzhiyun snd_fw_transaction(dg00x->unit, TCODE_WRITE_QUADLET_REQUEST,
131*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_STREAMING_SET,
132*4882a593Smuzhiyun &data, sizeof(data), 0);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun // Unregister isochronous channels for both direction.
135*4882a593Smuzhiyun data = 0;
136*4882a593Smuzhiyun snd_fw_transaction(dg00x->unit, TCODE_WRITE_QUADLET_REQUEST,
137*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_ISOC_CHANNELS,
138*4882a593Smuzhiyun &data, sizeof(data), 0);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun // Just after finishing the session, the device may lost transmitting
141*4882a593Smuzhiyun // functionality for a short time.
142*4882a593Smuzhiyun msleep(50);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
begin_session(struct snd_dg00x * dg00x)145*4882a593Smuzhiyun static int begin_session(struct snd_dg00x *dg00x)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun __be32 data;
148*4882a593Smuzhiyun u32 curr;
149*4882a593Smuzhiyun int err;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun // Register isochronous channels for both direction.
152*4882a593Smuzhiyun data = cpu_to_be32((dg00x->tx_resources.channel << 16) |
153*4882a593Smuzhiyun dg00x->rx_resources.channel);
154*4882a593Smuzhiyun err = snd_fw_transaction(dg00x->unit, TCODE_WRITE_QUADLET_REQUEST,
155*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_ISOC_CHANNELS,
156*4882a593Smuzhiyun &data, sizeof(data), 0);
157*4882a593Smuzhiyun if (err < 0)
158*4882a593Smuzhiyun return err;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST,
161*4882a593Smuzhiyun DG00X_ADDR_BASE + DG00X_OFFSET_STREAMING_STATE,
162*4882a593Smuzhiyun &data, sizeof(data), 0);
163*4882a593Smuzhiyun if (err < 0)
164*4882a593Smuzhiyun return err;
165*4882a593Smuzhiyun curr = be32_to_cpu(data);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun if (curr == 0)
168*4882a593Smuzhiyun curr = 2;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun curr--;
171*4882a593Smuzhiyun while (curr > 0) {
172*4882a593Smuzhiyun data = cpu_to_be32(curr);
173*4882a593Smuzhiyun err = snd_fw_transaction(dg00x->unit,
174*4882a593Smuzhiyun TCODE_WRITE_QUADLET_REQUEST,
175*4882a593Smuzhiyun DG00X_ADDR_BASE +
176*4882a593Smuzhiyun DG00X_OFFSET_STREAMING_SET,
177*4882a593Smuzhiyun &data, sizeof(data), 0);
178*4882a593Smuzhiyun if (err < 0)
179*4882a593Smuzhiyun break;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun msleep(20);
182*4882a593Smuzhiyun curr--;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun return err;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
keep_resources(struct snd_dg00x * dg00x,struct amdtp_stream * stream,unsigned int rate)188*4882a593Smuzhiyun static int keep_resources(struct snd_dg00x *dg00x, struct amdtp_stream *stream,
189*4882a593Smuzhiyun unsigned int rate)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct fw_iso_resources *resources;
192*4882a593Smuzhiyun int i;
193*4882a593Smuzhiyun int err;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun // Check sampling rate.
196*4882a593Smuzhiyun for (i = 0; i < SND_DG00X_RATE_COUNT; i++) {
197*4882a593Smuzhiyun if (snd_dg00x_stream_rates[i] == rate)
198*4882a593Smuzhiyun break;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun if (i == SND_DG00X_RATE_COUNT)
201*4882a593Smuzhiyun return -EINVAL;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (stream == &dg00x->tx_stream)
204*4882a593Smuzhiyun resources = &dg00x->tx_resources;
205*4882a593Smuzhiyun else
206*4882a593Smuzhiyun resources = &dg00x->rx_resources;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun err = amdtp_dot_set_parameters(stream, rate,
209*4882a593Smuzhiyun snd_dg00x_stream_pcm_channels[i]);
210*4882a593Smuzhiyun if (err < 0)
211*4882a593Smuzhiyun return err;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun return fw_iso_resources_allocate(resources,
214*4882a593Smuzhiyun amdtp_stream_get_max_payload(stream),
215*4882a593Smuzhiyun fw_parent_device(dg00x->unit)->max_speed);
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
init_stream(struct snd_dg00x * dg00x,struct amdtp_stream * s)218*4882a593Smuzhiyun static int init_stream(struct snd_dg00x *dg00x, struct amdtp_stream *s)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct fw_iso_resources *resources;
221*4882a593Smuzhiyun enum amdtp_stream_direction dir;
222*4882a593Smuzhiyun int err;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun if (s == &dg00x->tx_stream) {
225*4882a593Smuzhiyun resources = &dg00x->tx_resources;
226*4882a593Smuzhiyun dir = AMDTP_IN_STREAM;
227*4882a593Smuzhiyun } else {
228*4882a593Smuzhiyun resources = &dg00x->rx_resources;
229*4882a593Smuzhiyun dir = AMDTP_OUT_STREAM;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun err = fw_iso_resources_init(resources, dg00x->unit);
233*4882a593Smuzhiyun if (err < 0)
234*4882a593Smuzhiyun return err;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun err = amdtp_dot_init(s, dg00x->unit, dir);
237*4882a593Smuzhiyun if (err < 0)
238*4882a593Smuzhiyun fw_iso_resources_destroy(resources);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun return err;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
destroy_stream(struct snd_dg00x * dg00x,struct amdtp_stream * s)243*4882a593Smuzhiyun static void destroy_stream(struct snd_dg00x *dg00x, struct amdtp_stream *s)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun amdtp_stream_destroy(s);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun if (s == &dg00x->tx_stream)
248*4882a593Smuzhiyun fw_iso_resources_destroy(&dg00x->tx_resources);
249*4882a593Smuzhiyun else
250*4882a593Smuzhiyun fw_iso_resources_destroy(&dg00x->rx_resources);
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
snd_dg00x_stream_init_duplex(struct snd_dg00x * dg00x)253*4882a593Smuzhiyun int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun int err;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun err = init_stream(dg00x, &dg00x->rx_stream);
258*4882a593Smuzhiyun if (err < 0)
259*4882a593Smuzhiyun return err;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun err = init_stream(dg00x, &dg00x->tx_stream);
262*4882a593Smuzhiyun if (err < 0)
263*4882a593Smuzhiyun destroy_stream(dg00x, &dg00x->rx_stream);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun err = amdtp_domain_init(&dg00x->domain);
266*4882a593Smuzhiyun if (err < 0) {
267*4882a593Smuzhiyun destroy_stream(dg00x, &dg00x->rx_stream);
268*4882a593Smuzhiyun destroy_stream(dg00x, &dg00x->tx_stream);
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return err;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /*
275*4882a593Smuzhiyun * This function should be called before starting streams or after stopping
276*4882a593Smuzhiyun * streams.
277*4882a593Smuzhiyun */
snd_dg00x_stream_destroy_duplex(struct snd_dg00x * dg00x)278*4882a593Smuzhiyun void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun amdtp_domain_destroy(&dg00x->domain);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun destroy_stream(dg00x, &dg00x->rx_stream);
283*4882a593Smuzhiyun destroy_stream(dg00x, &dg00x->tx_stream);
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
snd_dg00x_stream_reserve_duplex(struct snd_dg00x * dg00x,unsigned int rate,unsigned int frames_per_period,unsigned int frames_per_buffer)286*4882a593Smuzhiyun int snd_dg00x_stream_reserve_duplex(struct snd_dg00x *dg00x, unsigned int rate,
287*4882a593Smuzhiyun unsigned int frames_per_period,
288*4882a593Smuzhiyun unsigned int frames_per_buffer)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun unsigned int curr_rate;
291*4882a593Smuzhiyun int err;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun err = snd_dg00x_stream_get_local_rate(dg00x, &curr_rate);
294*4882a593Smuzhiyun if (err < 0)
295*4882a593Smuzhiyun return err;
296*4882a593Smuzhiyun if (rate == 0)
297*4882a593Smuzhiyun rate = curr_rate;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (dg00x->substreams_counter == 0 || curr_rate != rate) {
300*4882a593Smuzhiyun amdtp_domain_stop(&dg00x->domain);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun finish_session(dg00x);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun fw_iso_resources_free(&dg00x->tx_resources);
305*4882a593Smuzhiyun fw_iso_resources_free(&dg00x->rx_resources);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun err = snd_dg00x_stream_set_local_rate(dg00x, rate);
308*4882a593Smuzhiyun if (err < 0)
309*4882a593Smuzhiyun return err;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun err = keep_resources(dg00x, &dg00x->rx_stream, rate);
312*4882a593Smuzhiyun if (err < 0)
313*4882a593Smuzhiyun return err;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun err = keep_resources(dg00x, &dg00x->tx_stream, rate);
316*4882a593Smuzhiyun if (err < 0) {
317*4882a593Smuzhiyun fw_iso_resources_free(&dg00x->rx_resources);
318*4882a593Smuzhiyun return err;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun err = amdtp_domain_set_events_per_period(&dg00x->domain,
322*4882a593Smuzhiyun frames_per_period, frames_per_buffer);
323*4882a593Smuzhiyun if (err < 0) {
324*4882a593Smuzhiyun fw_iso_resources_free(&dg00x->rx_resources);
325*4882a593Smuzhiyun fw_iso_resources_free(&dg00x->tx_resources);
326*4882a593Smuzhiyun return err;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return 0;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
snd_dg00x_stream_start_duplex(struct snd_dg00x * dg00x)333*4882a593Smuzhiyun int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun unsigned int generation = dg00x->rx_resources.generation;
336*4882a593Smuzhiyun int err = 0;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun if (dg00x->substreams_counter == 0)
339*4882a593Smuzhiyun return 0;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun if (amdtp_streaming_error(&dg00x->tx_stream) ||
342*4882a593Smuzhiyun amdtp_streaming_error(&dg00x->rx_stream)) {
343*4882a593Smuzhiyun amdtp_domain_stop(&dg00x->domain);
344*4882a593Smuzhiyun finish_session(dg00x);
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun if (generation != fw_parent_device(dg00x->unit)->card->generation) {
348*4882a593Smuzhiyun err = fw_iso_resources_update(&dg00x->tx_resources);
349*4882a593Smuzhiyun if (err < 0)
350*4882a593Smuzhiyun goto error;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun err = fw_iso_resources_update(&dg00x->rx_resources);
353*4882a593Smuzhiyun if (err < 0)
354*4882a593Smuzhiyun goto error;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun /*
358*4882a593Smuzhiyun * No packets are transmitted without receiving packets, reagardless of
359*4882a593Smuzhiyun * which source of clock is used.
360*4882a593Smuzhiyun */
361*4882a593Smuzhiyun if (!amdtp_stream_running(&dg00x->rx_stream)) {
362*4882a593Smuzhiyun int spd = fw_parent_device(dg00x->unit)->max_speed;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun err = begin_session(dg00x);
365*4882a593Smuzhiyun if (err < 0)
366*4882a593Smuzhiyun goto error;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun err = amdtp_domain_add_stream(&dg00x->domain, &dg00x->rx_stream,
369*4882a593Smuzhiyun dg00x->rx_resources.channel, spd);
370*4882a593Smuzhiyun if (err < 0)
371*4882a593Smuzhiyun goto error;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun err = amdtp_domain_add_stream(&dg00x->domain, &dg00x->tx_stream,
374*4882a593Smuzhiyun dg00x->tx_resources.channel, spd);
375*4882a593Smuzhiyun if (err < 0)
376*4882a593Smuzhiyun goto error;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun err = amdtp_domain_start(&dg00x->domain, 0);
379*4882a593Smuzhiyun if (err < 0)
380*4882a593Smuzhiyun goto error;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun if (!amdtp_stream_wait_callback(&dg00x->rx_stream,
383*4882a593Smuzhiyun CALLBACK_TIMEOUT) ||
384*4882a593Smuzhiyun !amdtp_stream_wait_callback(&dg00x->tx_stream,
385*4882a593Smuzhiyun CALLBACK_TIMEOUT)) {
386*4882a593Smuzhiyun err = -ETIMEDOUT;
387*4882a593Smuzhiyun goto error;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun return 0;
392*4882a593Smuzhiyun error:
393*4882a593Smuzhiyun amdtp_domain_stop(&dg00x->domain);
394*4882a593Smuzhiyun finish_session(dg00x);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun return err;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
snd_dg00x_stream_stop_duplex(struct snd_dg00x * dg00x)399*4882a593Smuzhiyun void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun if (dg00x->substreams_counter == 0) {
402*4882a593Smuzhiyun amdtp_domain_stop(&dg00x->domain);
403*4882a593Smuzhiyun finish_session(dg00x);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun fw_iso_resources_free(&dg00x->tx_resources);
406*4882a593Smuzhiyun fw_iso_resources_free(&dg00x->rx_resources);
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
snd_dg00x_stream_update_duplex(struct snd_dg00x * dg00x)410*4882a593Smuzhiyun void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun fw_iso_resources_update(&dg00x->tx_resources);
413*4882a593Smuzhiyun fw_iso_resources_update(&dg00x->rx_resources);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun amdtp_stream_update(&dg00x->tx_stream);
416*4882a593Smuzhiyun amdtp_stream_update(&dg00x->rx_stream);
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
snd_dg00x_stream_lock_changed(struct snd_dg00x * dg00x)419*4882a593Smuzhiyun void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun dg00x->dev_lock_changed = true;
422*4882a593Smuzhiyun wake_up(&dg00x->hwdep_wait);
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
snd_dg00x_stream_lock_try(struct snd_dg00x * dg00x)425*4882a593Smuzhiyun int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x)
426*4882a593Smuzhiyun {
427*4882a593Smuzhiyun int err;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun spin_lock_irq(&dg00x->lock);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun /* user land lock this */
432*4882a593Smuzhiyun if (dg00x->dev_lock_count < 0) {
433*4882a593Smuzhiyun err = -EBUSY;
434*4882a593Smuzhiyun goto end;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun /* this is the first time */
438*4882a593Smuzhiyun if (dg00x->dev_lock_count++ == 0)
439*4882a593Smuzhiyun snd_dg00x_stream_lock_changed(dg00x);
440*4882a593Smuzhiyun err = 0;
441*4882a593Smuzhiyun end:
442*4882a593Smuzhiyun spin_unlock_irq(&dg00x->lock);
443*4882a593Smuzhiyun return err;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
snd_dg00x_stream_lock_release(struct snd_dg00x * dg00x)446*4882a593Smuzhiyun void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun spin_lock_irq(&dg00x->lock);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun if (WARN_ON(dg00x->dev_lock_count <= 0))
451*4882a593Smuzhiyun goto end;
452*4882a593Smuzhiyun if (--dg00x->dev_lock_count == 0)
453*4882a593Smuzhiyun snd_dg00x_stream_lock_changed(dg00x);
454*4882a593Smuzhiyun end:
455*4882a593Smuzhiyun spin_unlock_irq(&dg00x->lock);
456*4882a593Smuzhiyun }
457