1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4*4882a593Smuzhiyun * Hannu Savolainen 1993-1996,
5*4882a593Smuzhiyun * Rob Hooft
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Routines for control of AdLib FM cards (OPL2/OPL3/OPL4 chips)
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Most if code is ported from OSS/Lite.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <sound/opl3.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/ioport.h>
19*4882a593Smuzhiyun #include <sound/minors.h>
20*4882a593Smuzhiyun #include "opl3_voice.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Hannu Savolainen 1993-1996, Rob Hooft");
23*4882a593Smuzhiyun MODULE_DESCRIPTION("Routines for control of AdLib FM cards (OPL2/OPL3/OPL4 chips)");
24*4882a593Smuzhiyun MODULE_LICENSE("GPL");
25*4882a593Smuzhiyun
snd_opl2_command(struct snd_opl3 * opl3,unsigned short cmd,unsigned char val)26*4882a593Smuzhiyun static void snd_opl2_command(struct snd_opl3 * opl3, unsigned short cmd, unsigned char val)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun unsigned long flags;
29*4882a593Smuzhiyun unsigned long port;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * The original 2-OP synth requires a quite long delay
33*4882a593Smuzhiyun * after writing to a register.
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun port = (cmd & OPL3_RIGHT) ? opl3->r_port : opl3->l_port;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun spin_lock_irqsave(&opl3->reg_lock, flags);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun outb((unsigned char) cmd, port);
41*4882a593Smuzhiyun udelay(10);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun outb((unsigned char) val, port + 1);
44*4882a593Smuzhiyun udelay(30);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun spin_unlock_irqrestore(&opl3->reg_lock, flags);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
snd_opl3_command(struct snd_opl3 * opl3,unsigned short cmd,unsigned char val)49*4882a593Smuzhiyun static void snd_opl3_command(struct snd_opl3 * opl3, unsigned short cmd, unsigned char val)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun unsigned long flags;
52*4882a593Smuzhiyun unsigned long port;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * The OPL-3 survives with just two INBs
56*4882a593Smuzhiyun * after writing to a register.
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun port = (cmd & OPL3_RIGHT) ? opl3->r_port : opl3->l_port;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun spin_lock_irqsave(&opl3->reg_lock, flags);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun outb((unsigned char) cmd, port);
64*4882a593Smuzhiyun inb(opl3->l_port);
65*4882a593Smuzhiyun inb(opl3->l_port);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun outb((unsigned char) val, port + 1);
68*4882a593Smuzhiyun inb(opl3->l_port);
69*4882a593Smuzhiyun inb(opl3->l_port);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun spin_unlock_irqrestore(&opl3->reg_lock, flags);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
snd_opl3_detect(struct snd_opl3 * opl3)74*4882a593Smuzhiyun static int snd_opl3_detect(struct snd_opl3 * opl3)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * This function returns 1 if the FM chip is present at the given I/O port
78*4882a593Smuzhiyun * The detection algorithm plays with the timer built in the FM chip and
79*4882a593Smuzhiyun * looks for a change in the status register.
80*4882a593Smuzhiyun *
81*4882a593Smuzhiyun * Note! The timers of the FM chip are not connected to AdLib (and compatible)
82*4882a593Smuzhiyun * boards.
83*4882a593Smuzhiyun *
84*4882a593Smuzhiyun * Note2! The chip is initialized if detected.
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun unsigned char stat1, stat2, signature;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Reset timers 1 and 2 */
90*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER1_MASK | OPL3_TIMER2_MASK);
91*4882a593Smuzhiyun /* Reset the IRQ of the FM chip */
92*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_IRQ_RESET);
93*4882a593Smuzhiyun signature = stat1 = inb(opl3->l_port); /* Status register */
94*4882a593Smuzhiyun if ((stat1 & 0xe0) != 0x00) { /* Should be 0x00 */
95*4882a593Smuzhiyun snd_printd("OPL3: stat1 = 0x%x\n", stat1);
96*4882a593Smuzhiyun return -ENODEV;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun /* Set timer1 to 0xff */
99*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER1, 0xff);
100*4882a593Smuzhiyun /* Unmask and start timer 1 */
101*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER2_MASK | OPL3_TIMER1_START);
102*4882a593Smuzhiyun /* Now we have to delay at least 80us */
103*4882a593Smuzhiyun udelay(200);
104*4882a593Smuzhiyun /* Read status after timers have expired */
105*4882a593Smuzhiyun stat2 = inb(opl3->l_port);
106*4882a593Smuzhiyun /* Stop the timers */
107*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER1_MASK | OPL3_TIMER2_MASK);
108*4882a593Smuzhiyun /* Reset the IRQ of the FM chip */
109*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_IRQ_RESET);
110*4882a593Smuzhiyun if ((stat2 & 0xe0) != 0xc0) { /* There is no YM3812 */
111*4882a593Smuzhiyun snd_printd("OPL3: stat2 = 0x%x\n", stat2);
112*4882a593Smuzhiyun return -ENODEV;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* If the toplevel code knows exactly the type of chip, don't try
116*4882a593Smuzhiyun to detect it. */
117*4882a593Smuzhiyun if (opl3->hardware != OPL3_HW_AUTO)
118*4882a593Smuzhiyun return 0;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* There is a FM chip on this address. Detect the type (OPL2 to OPL4) */
121*4882a593Smuzhiyun if (signature == 0x06) { /* OPL2 */
122*4882a593Smuzhiyun opl3->hardware = OPL3_HW_OPL2;
123*4882a593Smuzhiyun } else {
124*4882a593Smuzhiyun /*
125*4882a593Smuzhiyun * If we had an OPL4 chip, opl3->hardware would have been set
126*4882a593Smuzhiyun * by the OPL4 driver; so we can assume OPL3 here.
127*4882a593Smuzhiyun */
128*4882a593Smuzhiyun if (snd_BUG_ON(!opl3->r_port))
129*4882a593Smuzhiyun return -ENODEV;
130*4882a593Smuzhiyun opl3->hardware = OPL3_HW_OPL3;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun return 0;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun * AdLib timers
137*4882a593Smuzhiyun */
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun * Timer 1 - 80us
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun
snd_opl3_timer1_start(struct snd_timer * timer)143*4882a593Smuzhiyun static int snd_opl3_timer1_start(struct snd_timer * timer)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun unsigned long flags;
146*4882a593Smuzhiyun unsigned char tmp;
147*4882a593Smuzhiyun unsigned int ticks;
148*4882a593Smuzhiyun struct snd_opl3 *opl3;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun opl3 = snd_timer_chip(timer);
151*4882a593Smuzhiyun spin_lock_irqsave(&opl3->timer_lock, flags);
152*4882a593Smuzhiyun ticks = timer->sticks;
153*4882a593Smuzhiyun tmp = (opl3->timer_enable | OPL3_TIMER1_START) & ~OPL3_TIMER1_MASK;
154*4882a593Smuzhiyun opl3->timer_enable = tmp;
155*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER1, 256 - ticks); /* timer 1 count */
156*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp); /* enable timer 1 IRQ */
157*4882a593Smuzhiyun spin_unlock_irqrestore(&opl3->timer_lock, flags);
158*4882a593Smuzhiyun return 0;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
snd_opl3_timer1_stop(struct snd_timer * timer)161*4882a593Smuzhiyun static int snd_opl3_timer1_stop(struct snd_timer * timer)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun unsigned long flags;
164*4882a593Smuzhiyun unsigned char tmp;
165*4882a593Smuzhiyun struct snd_opl3 *opl3;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun opl3 = snd_timer_chip(timer);
168*4882a593Smuzhiyun spin_lock_irqsave(&opl3->timer_lock, flags);
169*4882a593Smuzhiyun tmp = (opl3->timer_enable | OPL3_TIMER1_MASK) & ~OPL3_TIMER1_START;
170*4882a593Smuzhiyun opl3->timer_enable = tmp;
171*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp); /* disable timer #1 */
172*4882a593Smuzhiyun spin_unlock_irqrestore(&opl3->timer_lock, flags);
173*4882a593Smuzhiyun return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /*
177*4882a593Smuzhiyun * Timer 2 - 320us
178*4882a593Smuzhiyun */
179*4882a593Smuzhiyun
snd_opl3_timer2_start(struct snd_timer * timer)180*4882a593Smuzhiyun static int snd_opl3_timer2_start(struct snd_timer * timer)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun unsigned long flags;
183*4882a593Smuzhiyun unsigned char tmp;
184*4882a593Smuzhiyun unsigned int ticks;
185*4882a593Smuzhiyun struct snd_opl3 *opl3;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun opl3 = snd_timer_chip(timer);
188*4882a593Smuzhiyun spin_lock_irqsave(&opl3->timer_lock, flags);
189*4882a593Smuzhiyun ticks = timer->sticks;
190*4882a593Smuzhiyun tmp = (opl3->timer_enable | OPL3_TIMER2_START) & ~OPL3_TIMER2_MASK;
191*4882a593Smuzhiyun opl3->timer_enable = tmp;
192*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER2, 256 - ticks); /* timer 1 count */
193*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp); /* enable timer 1 IRQ */
194*4882a593Smuzhiyun spin_unlock_irqrestore(&opl3->timer_lock, flags);
195*4882a593Smuzhiyun return 0;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
snd_opl3_timer2_stop(struct snd_timer * timer)198*4882a593Smuzhiyun static int snd_opl3_timer2_stop(struct snd_timer * timer)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun unsigned long flags;
201*4882a593Smuzhiyun unsigned char tmp;
202*4882a593Smuzhiyun struct snd_opl3 *opl3;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun opl3 = snd_timer_chip(timer);
205*4882a593Smuzhiyun spin_lock_irqsave(&opl3->timer_lock, flags);
206*4882a593Smuzhiyun tmp = (opl3->timer_enable | OPL3_TIMER2_MASK) & ~OPL3_TIMER2_START;
207*4882a593Smuzhiyun opl3->timer_enable = tmp;
208*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp); /* disable timer #1 */
209*4882a593Smuzhiyun spin_unlock_irqrestore(&opl3->timer_lock, flags);
210*4882a593Smuzhiyun return 0;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /*
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun */
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static const struct snd_timer_hardware snd_opl3_timer1 =
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun .flags = SNDRV_TIMER_HW_STOP,
220*4882a593Smuzhiyun .resolution = 80000,
221*4882a593Smuzhiyun .ticks = 256,
222*4882a593Smuzhiyun .start = snd_opl3_timer1_start,
223*4882a593Smuzhiyun .stop = snd_opl3_timer1_stop,
224*4882a593Smuzhiyun };
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun static const struct snd_timer_hardware snd_opl3_timer2 =
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun .flags = SNDRV_TIMER_HW_STOP,
229*4882a593Smuzhiyun .resolution = 320000,
230*4882a593Smuzhiyun .ticks = 256,
231*4882a593Smuzhiyun .start = snd_opl3_timer2_start,
232*4882a593Smuzhiyun .stop = snd_opl3_timer2_stop,
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun
snd_opl3_timer1_init(struct snd_opl3 * opl3,int timer_no)235*4882a593Smuzhiyun static int snd_opl3_timer1_init(struct snd_opl3 * opl3, int timer_no)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun struct snd_timer *timer = NULL;
238*4882a593Smuzhiyun struct snd_timer_id tid;
239*4882a593Smuzhiyun int err;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun tid.dev_class = SNDRV_TIMER_CLASS_CARD;
242*4882a593Smuzhiyun tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
243*4882a593Smuzhiyun tid.card = opl3->card->number;
244*4882a593Smuzhiyun tid.device = timer_no;
245*4882a593Smuzhiyun tid.subdevice = 0;
246*4882a593Smuzhiyun if ((err = snd_timer_new(opl3->card, "AdLib timer #1", &tid, &timer)) >= 0) {
247*4882a593Smuzhiyun strcpy(timer->name, "AdLib timer #1");
248*4882a593Smuzhiyun timer->private_data = opl3;
249*4882a593Smuzhiyun timer->hw = snd_opl3_timer1;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun opl3->timer1 = timer;
252*4882a593Smuzhiyun return err;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
snd_opl3_timer2_init(struct snd_opl3 * opl3,int timer_no)255*4882a593Smuzhiyun static int snd_opl3_timer2_init(struct snd_opl3 * opl3, int timer_no)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun struct snd_timer *timer = NULL;
258*4882a593Smuzhiyun struct snd_timer_id tid;
259*4882a593Smuzhiyun int err;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun tid.dev_class = SNDRV_TIMER_CLASS_CARD;
262*4882a593Smuzhiyun tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
263*4882a593Smuzhiyun tid.card = opl3->card->number;
264*4882a593Smuzhiyun tid.device = timer_no;
265*4882a593Smuzhiyun tid.subdevice = 0;
266*4882a593Smuzhiyun if ((err = snd_timer_new(opl3->card, "AdLib timer #2", &tid, &timer)) >= 0) {
267*4882a593Smuzhiyun strcpy(timer->name, "AdLib timer #2");
268*4882a593Smuzhiyun timer->private_data = opl3;
269*4882a593Smuzhiyun timer->hw = snd_opl3_timer2;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun opl3->timer2 = timer;
272*4882a593Smuzhiyun return err;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /*
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun */
278*4882a593Smuzhiyun
snd_opl3_interrupt(struct snd_hwdep * hw)279*4882a593Smuzhiyun void snd_opl3_interrupt(struct snd_hwdep * hw)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun unsigned char status;
282*4882a593Smuzhiyun struct snd_opl3 *opl3;
283*4882a593Smuzhiyun struct snd_timer *timer;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if (hw == NULL)
286*4882a593Smuzhiyun return;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun opl3 = hw->private_data;
289*4882a593Smuzhiyun status = inb(opl3->l_port);
290*4882a593Smuzhiyun #if 0
291*4882a593Smuzhiyun snd_printk(KERN_DEBUG "AdLib IRQ status = 0x%x\n", status);
292*4882a593Smuzhiyun #endif
293*4882a593Smuzhiyun if (!(status & 0x80))
294*4882a593Smuzhiyun return;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun if (status & 0x40) {
297*4882a593Smuzhiyun timer = opl3->timer1;
298*4882a593Smuzhiyun snd_timer_interrupt(timer, timer->sticks);
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun if (status & 0x20) {
301*4882a593Smuzhiyun timer = opl3->timer2;
302*4882a593Smuzhiyun snd_timer_interrupt(timer, timer->sticks);
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun EXPORT_SYMBOL(snd_opl3_interrupt);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /*
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun */
311*4882a593Smuzhiyun
snd_opl3_free(struct snd_opl3 * opl3)312*4882a593Smuzhiyun static int snd_opl3_free(struct snd_opl3 *opl3)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun if (snd_BUG_ON(!opl3))
315*4882a593Smuzhiyun return -ENXIO;
316*4882a593Smuzhiyun if (opl3->private_free)
317*4882a593Smuzhiyun opl3->private_free(opl3);
318*4882a593Smuzhiyun snd_opl3_clear_patches(opl3);
319*4882a593Smuzhiyun release_and_free_resource(opl3->res_l_port);
320*4882a593Smuzhiyun release_and_free_resource(opl3->res_r_port);
321*4882a593Smuzhiyun kfree(opl3);
322*4882a593Smuzhiyun return 0;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
snd_opl3_dev_free(struct snd_device * device)325*4882a593Smuzhiyun static int snd_opl3_dev_free(struct snd_device *device)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun struct snd_opl3 *opl3 = device->device_data;
328*4882a593Smuzhiyun return snd_opl3_free(opl3);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
snd_opl3_new(struct snd_card * card,unsigned short hardware,struct snd_opl3 ** ropl3)331*4882a593Smuzhiyun int snd_opl3_new(struct snd_card *card,
332*4882a593Smuzhiyun unsigned short hardware,
333*4882a593Smuzhiyun struct snd_opl3 **ropl3)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun static const struct snd_device_ops ops = {
336*4882a593Smuzhiyun .dev_free = snd_opl3_dev_free,
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun struct snd_opl3 *opl3;
339*4882a593Smuzhiyun int err;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun *ropl3 = NULL;
342*4882a593Smuzhiyun opl3 = kzalloc(sizeof(*opl3), GFP_KERNEL);
343*4882a593Smuzhiyun if (!opl3)
344*4882a593Smuzhiyun return -ENOMEM;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun opl3->card = card;
347*4882a593Smuzhiyun opl3->hardware = hardware;
348*4882a593Smuzhiyun spin_lock_init(&opl3->reg_lock);
349*4882a593Smuzhiyun spin_lock_init(&opl3->timer_lock);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun if ((err = snd_device_new(card, SNDRV_DEV_CODEC, opl3, &ops)) < 0) {
352*4882a593Smuzhiyun snd_opl3_free(opl3);
353*4882a593Smuzhiyun return err;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun *ropl3 = opl3;
357*4882a593Smuzhiyun return 0;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun EXPORT_SYMBOL(snd_opl3_new);
361*4882a593Smuzhiyun
snd_opl3_init(struct snd_opl3 * opl3)362*4882a593Smuzhiyun int snd_opl3_init(struct snd_opl3 *opl3)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun if (! opl3->command) {
365*4882a593Smuzhiyun printk(KERN_ERR "snd_opl3_init: command not defined!\n");
366*4882a593Smuzhiyun return -EINVAL;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_TEST, OPL3_ENABLE_WAVE_SELECT);
370*4882a593Smuzhiyun /* Melodic mode */
371*4882a593Smuzhiyun opl3->command(opl3, OPL3_LEFT | OPL3_REG_PERCUSSION, 0x00);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun switch (opl3->hardware & OPL3_HW_MASK) {
374*4882a593Smuzhiyun case OPL3_HW_OPL2:
375*4882a593Smuzhiyun opl3->max_voices = MAX_OPL2_VOICES;
376*4882a593Smuzhiyun break;
377*4882a593Smuzhiyun case OPL3_HW_OPL3:
378*4882a593Smuzhiyun case OPL3_HW_OPL4:
379*4882a593Smuzhiyun opl3->max_voices = MAX_OPL3_VOICES;
380*4882a593Smuzhiyun /* Enter OPL3 mode */
381*4882a593Smuzhiyun opl3->command(opl3, OPL3_RIGHT | OPL3_REG_MODE, OPL3_OPL3_ENABLE);
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun return 0;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun EXPORT_SYMBOL(snd_opl3_init);
387*4882a593Smuzhiyun
snd_opl3_create(struct snd_card * card,unsigned long l_port,unsigned long r_port,unsigned short hardware,int integrated,struct snd_opl3 ** ropl3)388*4882a593Smuzhiyun int snd_opl3_create(struct snd_card *card,
389*4882a593Smuzhiyun unsigned long l_port,
390*4882a593Smuzhiyun unsigned long r_port,
391*4882a593Smuzhiyun unsigned short hardware,
392*4882a593Smuzhiyun int integrated,
393*4882a593Smuzhiyun struct snd_opl3 ** ropl3)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun struct snd_opl3 *opl3;
396*4882a593Smuzhiyun int err;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun *ropl3 = NULL;
399*4882a593Smuzhiyun if ((err = snd_opl3_new(card, hardware, &opl3)) < 0)
400*4882a593Smuzhiyun return err;
401*4882a593Smuzhiyun if (! integrated) {
402*4882a593Smuzhiyun if ((opl3->res_l_port = request_region(l_port, 2, "OPL2/3 (left)")) == NULL) {
403*4882a593Smuzhiyun snd_printk(KERN_ERR "opl3: can't grab left port 0x%lx\n", l_port);
404*4882a593Smuzhiyun snd_device_free(card, opl3);
405*4882a593Smuzhiyun return -EBUSY;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun if (r_port != 0 &&
408*4882a593Smuzhiyun (opl3->res_r_port = request_region(r_port, 2, "OPL2/3 (right)")) == NULL) {
409*4882a593Smuzhiyun snd_printk(KERN_ERR "opl3: can't grab right port 0x%lx\n", r_port);
410*4882a593Smuzhiyun snd_device_free(card, opl3);
411*4882a593Smuzhiyun return -EBUSY;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun opl3->l_port = l_port;
415*4882a593Smuzhiyun opl3->r_port = r_port;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun switch (opl3->hardware) {
418*4882a593Smuzhiyun /* some hardware doesn't support timers */
419*4882a593Smuzhiyun case OPL3_HW_OPL3_SV:
420*4882a593Smuzhiyun case OPL3_HW_OPL3_CS:
421*4882a593Smuzhiyun case OPL3_HW_OPL3_FM801:
422*4882a593Smuzhiyun opl3->command = &snd_opl3_command;
423*4882a593Smuzhiyun break;
424*4882a593Smuzhiyun default:
425*4882a593Smuzhiyun opl3->command = &snd_opl2_command;
426*4882a593Smuzhiyun if ((err = snd_opl3_detect(opl3)) < 0) {
427*4882a593Smuzhiyun snd_printd("OPL2/3 chip not detected at 0x%lx/0x%lx\n",
428*4882a593Smuzhiyun opl3->l_port, opl3->r_port);
429*4882a593Smuzhiyun snd_device_free(card, opl3);
430*4882a593Smuzhiyun return err;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun /* detect routine returns correct hardware type */
433*4882a593Smuzhiyun switch (opl3->hardware & OPL3_HW_MASK) {
434*4882a593Smuzhiyun case OPL3_HW_OPL3:
435*4882a593Smuzhiyun case OPL3_HW_OPL4:
436*4882a593Smuzhiyun opl3->command = &snd_opl3_command;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun snd_opl3_init(opl3);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun *ropl3 = opl3;
443*4882a593Smuzhiyun return 0;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun EXPORT_SYMBOL(snd_opl3_create);
447*4882a593Smuzhiyun
snd_opl3_timer_new(struct snd_opl3 * opl3,int timer1_dev,int timer2_dev)448*4882a593Smuzhiyun int snd_opl3_timer_new(struct snd_opl3 * opl3, int timer1_dev, int timer2_dev)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun int err;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun if (timer1_dev >= 0)
453*4882a593Smuzhiyun if ((err = snd_opl3_timer1_init(opl3, timer1_dev)) < 0)
454*4882a593Smuzhiyun return err;
455*4882a593Smuzhiyun if (timer2_dev >= 0) {
456*4882a593Smuzhiyun if ((err = snd_opl3_timer2_init(opl3, timer2_dev)) < 0) {
457*4882a593Smuzhiyun snd_device_free(opl3->card, opl3->timer1);
458*4882a593Smuzhiyun opl3->timer1 = NULL;
459*4882a593Smuzhiyun return err;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun return 0;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun EXPORT_SYMBOL(snd_opl3_timer_new);
466*4882a593Smuzhiyun
snd_opl3_hwdep_new(struct snd_opl3 * opl3,int device,int seq_device,struct snd_hwdep ** rhwdep)467*4882a593Smuzhiyun int snd_opl3_hwdep_new(struct snd_opl3 * opl3,
468*4882a593Smuzhiyun int device, int seq_device,
469*4882a593Smuzhiyun struct snd_hwdep ** rhwdep)
470*4882a593Smuzhiyun {
471*4882a593Smuzhiyun struct snd_hwdep *hw;
472*4882a593Smuzhiyun struct snd_card *card = opl3->card;
473*4882a593Smuzhiyun int err;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun if (rhwdep)
476*4882a593Smuzhiyun *rhwdep = NULL;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun /* create hardware dependent device (direct FM) */
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun if ((err = snd_hwdep_new(card, "OPL2/OPL3", device, &hw)) < 0) {
481*4882a593Smuzhiyun snd_device_free(card, opl3);
482*4882a593Smuzhiyun return err;
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun hw->private_data = opl3;
485*4882a593Smuzhiyun hw->exclusive = 1;
486*4882a593Smuzhiyun #ifdef CONFIG_SND_OSSEMUL
487*4882a593Smuzhiyun if (device == 0)
488*4882a593Smuzhiyun hw->oss_type = SNDRV_OSS_DEVICE_TYPE_DMFM;
489*4882a593Smuzhiyun #endif
490*4882a593Smuzhiyun strcpy(hw->name, hw->id);
491*4882a593Smuzhiyun switch (opl3->hardware & OPL3_HW_MASK) {
492*4882a593Smuzhiyun case OPL3_HW_OPL2:
493*4882a593Smuzhiyun strcpy(hw->name, "OPL2 FM");
494*4882a593Smuzhiyun hw->iface = SNDRV_HWDEP_IFACE_OPL2;
495*4882a593Smuzhiyun break;
496*4882a593Smuzhiyun case OPL3_HW_OPL3:
497*4882a593Smuzhiyun strcpy(hw->name, "OPL3 FM");
498*4882a593Smuzhiyun hw->iface = SNDRV_HWDEP_IFACE_OPL3;
499*4882a593Smuzhiyun break;
500*4882a593Smuzhiyun case OPL3_HW_OPL4:
501*4882a593Smuzhiyun strcpy(hw->name, "OPL4 FM");
502*4882a593Smuzhiyun hw->iface = SNDRV_HWDEP_IFACE_OPL4;
503*4882a593Smuzhiyun break;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /* operators - only ioctl */
507*4882a593Smuzhiyun hw->ops.open = snd_opl3_open;
508*4882a593Smuzhiyun hw->ops.ioctl = snd_opl3_ioctl;
509*4882a593Smuzhiyun hw->ops.write = snd_opl3_write;
510*4882a593Smuzhiyun hw->ops.release = snd_opl3_release;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun opl3->hwdep = hw;
513*4882a593Smuzhiyun opl3->seq_dev_num = seq_device;
514*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_SEQUENCER)
515*4882a593Smuzhiyun if (snd_seq_device_new(card, seq_device, SNDRV_SEQ_DEV_ID_OPL3,
516*4882a593Smuzhiyun sizeof(struct snd_opl3 *), &opl3->seq_dev) >= 0) {
517*4882a593Smuzhiyun strcpy(opl3->seq_dev->name, hw->name);
518*4882a593Smuzhiyun *(struct snd_opl3 **)SNDRV_SEQ_DEVICE_ARGPTR(opl3->seq_dev) = opl3;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun #endif
521*4882a593Smuzhiyun if (rhwdep)
522*4882a593Smuzhiyun *rhwdep = hw;
523*4882a593Smuzhiyun return 0;
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun EXPORT_SYMBOL(snd_opl3_hwdep_new);
527