1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Register definitions for Atmel AC97C 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2005-2009 Atmel Corporation 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __SOUND_ATMEL_AC97C_H 8*4882a593Smuzhiyun #define __SOUND_ATMEL_AC97C_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define AC97C_MR 0x08 11*4882a593Smuzhiyun #define AC97C_ICA 0x10 12*4882a593Smuzhiyun #define AC97C_OCA 0x14 13*4882a593Smuzhiyun #define AC97C_CARHR 0x20 14*4882a593Smuzhiyun #define AC97C_CATHR 0x24 15*4882a593Smuzhiyun #define AC97C_CASR 0x28 16*4882a593Smuzhiyun #define AC97C_CAMR 0x2c 17*4882a593Smuzhiyun #define AC97C_CORHR 0x40 18*4882a593Smuzhiyun #define AC97C_COTHR 0x44 19*4882a593Smuzhiyun #define AC97C_COSR 0x48 20*4882a593Smuzhiyun #define AC97C_COMR 0x4c 21*4882a593Smuzhiyun #define AC97C_SR 0x50 22*4882a593Smuzhiyun #define AC97C_IER 0x54 23*4882a593Smuzhiyun #define AC97C_IDR 0x58 24*4882a593Smuzhiyun #define AC97C_IMR 0x5c 25*4882a593Smuzhiyun #define AC97C_VERSION 0xfc 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AC97C_CATPR PDC_TPR 28*4882a593Smuzhiyun #define AC97C_CATCR PDC_TCR 29*4882a593Smuzhiyun #define AC97C_CATNPR PDC_TNPR 30*4882a593Smuzhiyun #define AC97C_CATNCR PDC_TNCR 31*4882a593Smuzhiyun #define AC97C_CARPR PDC_RPR 32*4882a593Smuzhiyun #define AC97C_CARCR PDC_RCR 33*4882a593Smuzhiyun #define AC97C_CARNPR PDC_RNPR 34*4882a593Smuzhiyun #define AC97C_CARNCR PDC_RNCR 35*4882a593Smuzhiyun #define AC97C_PTCR PDC_PTCR 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AC97C_MR_ENA (1 << 0) 38*4882a593Smuzhiyun #define AC97C_MR_WRST (1 << 1) 39*4882a593Smuzhiyun #define AC97C_MR_VRA (1 << 2) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define AC97C_CSR_TXRDY (1 << 0) 42*4882a593Smuzhiyun #define AC97C_CSR_TXEMPTY (1 << 1) 43*4882a593Smuzhiyun #define AC97C_CSR_UNRUN (1 << 2) 44*4882a593Smuzhiyun #define AC97C_CSR_RXRDY (1 << 4) 45*4882a593Smuzhiyun #define AC97C_CSR_OVRUN (1 << 5) 46*4882a593Smuzhiyun #define AC97C_CSR_ENDTX (1 << 10) 47*4882a593Smuzhiyun #define AC97C_CSR_ENDRX (1 << 14) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define AC97C_CMR_SIZE_20 (0 << 16) 50*4882a593Smuzhiyun #define AC97C_CMR_SIZE_18 (1 << 16) 51*4882a593Smuzhiyun #define AC97C_CMR_SIZE_16 (2 << 16) 52*4882a593Smuzhiyun #define AC97C_CMR_SIZE_10 (3 << 16) 53*4882a593Smuzhiyun #define AC97C_CMR_CEM_LITTLE (1 << 18) 54*4882a593Smuzhiyun #define AC97C_CMR_CEM_BIG (0 << 18) 55*4882a593Smuzhiyun #define AC97C_CMR_CENA (1 << 21) 56*4882a593Smuzhiyun #define AC97C_CMR_DMAEN (1 << 22) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define AC97C_SR_CAEVT (1 << 3) 59*4882a593Smuzhiyun #define AC97C_SR_COEVT (1 << 2) 60*4882a593Smuzhiyun #define AC97C_SR_WKUP (1 << 1) 61*4882a593Smuzhiyun #define AC97C_SR_SOF (1 << 0) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define AC97C_CH_MASK(slot) \ 64*4882a593Smuzhiyun (0x7 << (3 * (AC97_SLOT_##slot - 3))) 65*4882a593Smuzhiyun #define AC97C_CH_ASSIGN(slot, channel) \ 66*4882a593Smuzhiyun (AC97C_CHANNEL_##channel << (3 * (AC97_SLOT_##slot - 3))) 67*4882a593Smuzhiyun #define AC97C_CHANNEL_NONE 0x0 68*4882a593Smuzhiyun #define AC97C_CHANNEL_A 0x1 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* __SOUND_ATMEL_AC97C_H */ 71