1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Apple Onboard Audio driver for Onyx codec (header) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __SND_AOA_CODEC_ONYX_H 8*4882a593Smuzhiyun #define __SND_AOA_CODEC_ONYX_H 9*4882a593Smuzhiyun #include <stddef.h> 10*4882a593Smuzhiyun #include <linux/i2c.h> 11*4882a593Smuzhiyun #include <asm/pmac_low_i2c.h> 12*4882a593Smuzhiyun #include <asm/prom.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* PCM3052 register definitions */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* the attenuation registers take values from 17*4882a593Smuzhiyun * -1 (0dB) to -127 (-63.0 dB) or others (muted) */ 18*4882a593Smuzhiyun #define ONYX_REG_DAC_ATTEN_LEFT 65 19*4882a593Smuzhiyun #define FIRSTREGISTER ONYX_REG_DAC_ATTEN_LEFT 20*4882a593Smuzhiyun #define ONYX_REG_DAC_ATTEN_RIGHT 66 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define ONYX_REG_CONTROL 67 23*4882a593Smuzhiyun # define ONYX_MRST (1<<7) 24*4882a593Smuzhiyun # define ONYX_SRST (1<<6) 25*4882a593Smuzhiyun # define ONYX_ADPSV (1<<5) 26*4882a593Smuzhiyun # define ONYX_DAPSV (1<<4) 27*4882a593Smuzhiyun # define ONYX_SILICONVERSION (1<<0) 28*4882a593Smuzhiyun /* all others reserved */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define ONYX_REG_DAC_CONTROL 68 31*4882a593Smuzhiyun # define ONYX_OVR1 (1<<6) 32*4882a593Smuzhiyun # define ONYX_MUTE_RIGHT (1<<1) 33*4882a593Smuzhiyun # define ONYX_MUTE_LEFT (1<<0) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define ONYX_REG_DAC_DEEMPH 69 36*4882a593Smuzhiyun # define ONYX_DIGDEEMPH_SHIFT 5 37*4882a593Smuzhiyun # define ONYX_DIGDEEMPH_MASK (3<<ONYX_DIGDEEMPH_SHIFT) 38*4882a593Smuzhiyun # define ONYX_DIGDEEMPH_CTRL (1<<4) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define ONYX_REG_DAC_FILTER 70 41*4882a593Smuzhiyun # define ONYX_ROLLOFF_FAST (1<<5) 42*4882a593Smuzhiyun # define ONYX_DAC_FILTER_ALWAYS (1<<2) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define ONYX_REG_DAC_OUTPHASE 71 45*4882a593Smuzhiyun # define ONYX_OUTPHASE_INVERTED (1<<0) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define ONYX_REG_ADC_CONTROL 72 48*4882a593Smuzhiyun # define ONYX_ADC_INPUT_MIC (1<<5) 49*4882a593Smuzhiyun /* 8 + input gain in dB, valid range for input gain is -4 .. 20 dB */ 50*4882a593Smuzhiyun # define ONYX_ADC_PGA_GAIN_MASK 0x1f 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define ONYX_REG_ADC_HPF_BYPASS 75 53*4882a593Smuzhiyun # define ONYX_HPF_DISABLE (1<<3) 54*4882a593Smuzhiyun # define ONYX_ADC_HPF_ALWAYS (1<<2) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define ONYX_REG_DIG_INFO1 77 57*4882a593Smuzhiyun # define ONYX_MASK_DIN_TO_BPZ (1<<7) 58*4882a593Smuzhiyun /* bits 1-5 control channel bits 1-5 */ 59*4882a593Smuzhiyun # define ONYX_DIGOUT_DISABLE (1<<0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define ONYX_REG_DIG_INFO2 78 62*4882a593Smuzhiyun /* controls channel bits 8-15 */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define ONYX_REG_DIG_INFO3 79 65*4882a593Smuzhiyun /* control channel bits 24-29, high 2 bits reserved */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define ONYX_REG_DIG_INFO4 80 68*4882a593Smuzhiyun # define ONYX_VALIDL (1<<7) 69*4882a593Smuzhiyun # define ONYX_VALIDR (1<<6) 70*4882a593Smuzhiyun # define ONYX_SPDIF_ENABLE (1<<5) 71*4882a593Smuzhiyun /* lower 4 bits control bits 32-35 of channel control and word length */ 72*4882a593Smuzhiyun # define ONYX_WORDLEN_MASK (0xF) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* __SND_AOA_CODEC_ONYX_H */ 75