1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/ { 5*4882a593Smuzhiyun compatible = "jcore,j2-soc"; 6*4882a593Smuzhiyun model = "J2 FPGA SoC on Mimas v2 board"; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <1>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun interrupt-parent = <&aic>; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpus { 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <0>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpu@0 { 18*4882a593Smuzhiyun device_type = "cpu"; 19*4882a593Smuzhiyun compatible = "jcore,j2"; 20*4882a593Smuzhiyun reg = <0>; 21*4882a593Smuzhiyun clock-frequency = <50000000>; 22*4882a593Smuzhiyun d-cache-size = <8192>; 23*4882a593Smuzhiyun i-cache-size = <8192>; 24*4882a593Smuzhiyun d-cache-block-size = <16>; 25*4882a593Smuzhiyun i-cache-block-size = <16>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun memory@10000000 { 30*4882a593Smuzhiyun device_type = "memory"; 31*4882a593Smuzhiyun reg = <0x10000000 0x4000000>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun aliases { 35*4882a593Smuzhiyun serial0 = &uart0; 36*4882a593Smuzhiyun spi0 = &spi0; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun chosen { 40*4882a593Smuzhiyun stdout-path = "serial0"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun soc@abcd0000 { 44*4882a593Smuzhiyun compatible = "simple-bus"; 45*4882a593Smuzhiyun ranges = <0 0xabcd0000 0x100000>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <1>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun aic: interrupt-controller@200 { 51*4882a593Smuzhiyun compatible = "jcore,aic1"; 52*4882a593Smuzhiyun reg = <0x200 0x10>; 53*4882a593Smuzhiyun interrupt-controller; 54*4882a593Smuzhiyun #interrupt-cells = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun cache-controller@c0 { 58*4882a593Smuzhiyun compatible = "jcore,cache"; 59*4882a593Smuzhiyun reg = <0xc0 4>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun timer@200 { 63*4882a593Smuzhiyun compatible = "jcore,pit"; 64*4882a593Smuzhiyun reg = <0x200 0x30>; 65*4882a593Smuzhiyun interrupts = <0x48>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun spi0: spi@40 { 69*4882a593Smuzhiyun compatible = "jcore,spi2"; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #address-cells = <1>; 72*4882a593Smuzhiyun #size-cells = <0>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun spi-max-frequency = <25000000>; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun reg = <0x40 0x8>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun sdcard@0 { 79*4882a593Smuzhiyun compatible = "mmc-spi-slot"; 80*4882a593Smuzhiyun reg = <0>; 81*4882a593Smuzhiyun spi-max-frequency = <25000000>; 82*4882a593Smuzhiyun voltage-ranges = <3200 3400>; 83*4882a593Smuzhiyun mode = <0>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun uart0: serial@100 { 88*4882a593Smuzhiyun clock-frequency = <125000000>; 89*4882a593Smuzhiyun compatible = "xlnx,xps-uartlite-1.00.a"; 90*4882a593Smuzhiyun current-speed = <19200>; 91*4882a593Smuzhiyun device_type = "serial"; 92*4882a593Smuzhiyun interrupts = <0x12>; 93*4882a593Smuzhiyun port-number = <0>; 94*4882a593Smuzhiyun reg = <0x100 0x10>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun}; 98