1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Digsy MTC board Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 Semihalf 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on the CM5200 by M. Balakowicz 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/include/ "mpc5200b.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun&gpt0 { gpio-controller; fsl,has-wdt; }; 13*4882a593Smuzhiyun&gpt1 { gpio-controller; }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "intercontrol,digsy-mtc"; 17*4882a593Smuzhiyun compatible = "intercontrol,digsy-mtc"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun memory@0 { 20*4882a593Smuzhiyun reg = <0x00000000 0x02000000>; // 32MB 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun soc5200@f0000000 { 24*4882a593Smuzhiyun rtc@800 { 25*4882a593Smuzhiyun status = "disabled"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun spi@f00 { 29*4882a593Smuzhiyun msp430@0 { 30*4882a593Smuzhiyun compatible = "spidev"; 31*4882a593Smuzhiyun spi-max-frequency = <32000>; 32*4882a593Smuzhiyun reg = <0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun psc@2000 { // PSC1 37*4882a593Smuzhiyun status = "disabled"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun psc@2200 { // PSC2 41*4882a593Smuzhiyun status = "disabled"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun psc@2400 { // PSC3 45*4882a593Smuzhiyun status = "disabled"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun psc@2600 { // PSC4 49*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun psc@2800 { // PSC5 53*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun psc@2c00 { // PSC6 57*4882a593Smuzhiyun status = "disabled"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun ethernet@3000 { 61*4882a593Smuzhiyun phy-handle = <&phy0>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun mdio@3000 { 65*4882a593Smuzhiyun phy0: ethernet-phy@0 { 66*4882a593Smuzhiyun reg = <0>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun i2c@3d00 { 71*4882a593Smuzhiyun eeprom@50 { 72*4882a593Smuzhiyun compatible = "atmel,24c08"; 73*4882a593Smuzhiyun reg = <0x50>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun rtc@56 { 77*4882a593Smuzhiyun compatible = "microcrystal,rv3029"; 78*4882a593Smuzhiyun reg = <0x56>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun rtc@68 { 82*4882a593Smuzhiyun compatible = "dallas,ds1339"; 83*4882a593Smuzhiyun reg = <0x68>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun i2c@3d40 { 88*4882a593Smuzhiyun status = "disabled"; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun pci@f0000d00 { 93*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 94*4882a593Smuzhiyun interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 95*4882a593Smuzhiyun 0xc000 0 0 2 &mpc5200_pic 0 0 3 96*4882a593Smuzhiyun 0xc000 0 0 3 &mpc5200_pic 0 0 3 97*4882a593Smuzhiyun 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 98*4882a593Smuzhiyun clock-frequency = <0>; // From boot loader 99*4882a593Smuzhiyun interrupts = <2 8 0 2 9 0 2 10 0>; 100*4882a593Smuzhiyun bus-range = <0 0>; 101*4882a593Smuzhiyun ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 102*4882a593Smuzhiyun 0x02000000 0 0x90000000 0x90000000 0 0x10000000 103*4882a593Smuzhiyun 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun localbus { 107*4882a593Smuzhiyun ranges = <0 0 0xff000000 0x1000000 108*4882a593Smuzhiyun 4 0 0x60000000 0x0001000>; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun // 16-bit flash device at LocalPlus Bus CS0 111*4882a593Smuzhiyun flash@0,0 { 112*4882a593Smuzhiyun compatible = "cfi-flash"; 113*4882a593Smuzhiyun reg = <0 0 0x1000000>; 114*4882a593Smuzhiyun bank-width = <2>; 115*4882a593Smuzhiyun device-width = <2>; 116*4882a593Smuzhiyun #size-cells = <1>; 117*4882a593Smuzhiyun #address-cells = <1>; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun partition@0 { 120*4882a593Smuzhiyun label = "kernel"; 121*4882a593Smuzhiyun reg = <0x0 0x00200000>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun partition@200000 { 124*4882a593Smuzhiyun label = "root"; 125*4882a593Smuzhiyun reg = <0x00200000 0x00300000>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun partition@500000 { 128*4882a593Smuzhiyun label = "user"; 129*4882a593Smuzhiyun reg = <0x00500000 0x00a00000>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun partition@f00000 { 132*4882a593Smuzhiyun label = "u-boot"; 133*4882a593Smuzhiyun reg = <0x00f00000 0x100000>; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun can@4,0 { 138*4882a593Smuzhiyun compatible = "nxp,sja1000"; 139*4882a593Smuzhiyun reg = <4 0x000 0x80>; 140*4882a593Smuzhiyun nxp,external-clock-frequency = <24000000>; 141*4882a593Smuzhiyun interrupts = <1 2 3>; // Level-low 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun can@4,100 { 145*4882a593Smuzhiyun compatible = "nxp,sja1000"; 146*4882a593Smuzhiyun reg = <4 0x100 0x80>; 147*4882a593Smuzhiyun nxp,external-clock-frequency = <24000000>; 148*4882a593Smuzhiyun interrupts = <1 2 3>; // Level-low 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun serial@4,200 { 152*4882a593Smuzhiyun compatible = "nxp,sc28l92"; 153*4882a593Smuzhiyun reg = <4 0x200 0x10>; 154*4882a593Smuzhiyun interrupts = <1 3 3>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun}; 158