1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 5*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/mips-gic.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */ 8*4882a593Smuzhiyun/memreserve/ 0x00001000 0x000ef000; /* YAMON */ 9*4882a593Smuzhiyun/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun compatible = "mti,malta"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun cpu_intc: interrupt-controller { 17*4882a593Smuzhiyun compatible = "mti,cpu-interrupt-controller"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun interrupt-controller; 20*4882a593Smuzhiyun #interrupt-cells = <1>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun gic: interrupt-controller@1bdc0000 { 24*4882a593Smuzhiyun compatible = "mti,gic"; 25*4882a593Smuzhiyun reg = <0x1bdc0000 0x20000>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun interrupt-controller; 28*4882a593Smuzhiyun #interrupt-cells = <3>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * Declare the interrupt-parent even though the mti,gic 32*4882a593Smuzhiyun * binding doesn't require it, such that the kernel can 33*4882a593Smuzhiyun * figure out that cpu_intc is the root interrupt 34*4882a593Smuzhiyun * controller & should be probed first. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun interrupt-parent = <&cpu_intc>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun timer { 39*4882a593Smuzhiyun compatible = "mti,gic-timer"; 40*4882a593Smuzhiyun interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun i8259: interrupt-controller@20 { 45*4882a593Smuzhiyun compatible = "intel,i8259"; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun interrupt-controller; 48*4882a593Smuzhiyun #interrupt-cells = <1>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun interrupt-parent = <&gic>; 51*4882a593Smuzhiyun interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun flash@1e000000 { 55*4882a593Smuzhiyun compatible = "intel,dt28f160", "cfi-flash"; 56*4882a593Smuzhiyun reg = <0x1e000000 0x400000>; 57*4882a593Smuzhiyun bank-width = <4>; 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <1>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun partitions { 62*4882a593Smuzhiyun compatible = "fixed-partitions"; 63*4882a593Smuzhiyun #address-cells = <1>; 64*4882a593Smuzhiyun #size-cells = <1>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun yamon@0 { 67*4882a593Smuzhiyun label = "YAMON"; 68*4882a593Smuzhiyun reg = <0x0 0x100000>; 69*4882a593Smuzhiyun read-only; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun user-fs@100000 { 73*4882a593Smuzhiyun label = "User FS"; 74*4882a593Smuzhiyun reg = <0x100000 0x2e0000>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun board-config@3e0000 { 78*4882a593Smuzhiyun label = "Board Config"; 79*4882a593Smuzhiyun reg = <0x3e0000 0x20000>; 80*4882a593Smuzhiyun read-only; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun fpga_regs: system-controller@1f000000 { 86*4882a593Smuzhiyun compatible = "mti,malta-fpga", "syscon", "simple-mfd"; 87*4882a593Smuzhiyun reg = <0x1f000000 0x1000>; 88*4882a593Smuzhiyun native-endian; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun lcd@410 { 91*4882a593Smuzhiyun compatible = "mti,malta-lcd"; 92*4882a593Smuzhiyun offset = <0x410>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun reboot { 96*4882a593Smuzhiyun compatible = "syscon-reboot"; 97*4882a593Smuzhiyun regmap = <&fpga_regs>; 98*4882a593Smuzhiyun offset = <0x500>; 99*4882a593Smuzhiyun mask = <0x42>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun isa { 104*4882a593Smuzhiyun compatible = "isa"; 105*4882a593Smuzhiyun #address-cells = <2>; 106*4882a593Smuzhiyun #size-cells = <1>; 107*4882a593Smuzhiyun ranges = <1 0 0 0x1000>; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun rtc@70 { 110*4882a593Smuzhiyun compatible = "motorola,mc146818"; 111*4882a593Smuzhiyun reg = <1 0x70 0x8>; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun interrupt-parent = <&i8259>; 114*4882a593Smuzhiyun interrupts = <8>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun}; 118