1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun compatible = "gnu,gdbsim"; 5*4882a593Smuzhiyun #address-cells = <1>; 6*4882a593Smuzhiyun #size-cells = <1>; 7*4882a593Smuzhiyun interrupt-parent = <&h8intc>; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun bootargs = "earlyprintk=h8300-sim"; 11*4882a593Smuzhiyun stdout-path = <&sci0>; 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun serial0 = &sci0; 15*4882a593Smuzhiyun serial1 = &sci1; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun xclk: oscillator { 19*4882a593Smuzhiyun #clock-cells = <0>; 20*4882a593Smuzhiyun compatible = "fixed-clock"; 21*4882a593Smuzhiyun clock-frequency = <33333333>; 22*4882a593Smuzhiyun clock-output-names = "xtal"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun pllclk: pllclk { 25*4882a593Smuzhiyun compatible = "renesas,h8s2678-pll-clock"; 26*4882a593Smuzhiyun clocks = <&xclk>; 27*4882a593Smuzhiyun #clock-cells = <0>; 28*4882a593Smuzhiyun reg = <0xfee03b 2>, <0xfee045 2>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun core_clk: core_clk { 31*4882a593Smuzhiyun compatible = "renesas,h8300-div-clock"; 32*4882a593Smuzhiyun clocks = <&pllclk>; 33*4882a593Smuzhiyun #clock-cells = <0>; 34*4882a593Smuzhiyun reg = <0xfee03b 2>; 35*4882a593Smuzhiyun renesas,width = <3>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun fclk: fclk { 38*4882a593Smuzhiyun compatible = "fixed-factor-clock"; 39*4882a593Smuzhiyun clocks = <&core_clk>; 40*4882a593Smuzhiyun #clock-cells = <0>; 41*4882a593Smuzhiyun clock-div = <1>; 42*4882a593Smuzhiyun clock-mult = <1>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun memory@400000 { 46*4882a593Smuzhiyun device_type = "memory"; 47*4882a593Smuzhiyun reg = <0x400000 0x800000>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun cpus { 51*4882a593Smuzhiyun #address-cells = <1>; 52*4882a593Smuzhiyun #size-cells = <0>; 53*4882a593Smuzhiyun cpu@0 { 54*4882a593Smuzhiyun compatible = "renesas,h8300"; 55*4882a593Smuzhiyun clock-frequency = <33333333>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun h8intc: interrupt-controller@fffe00 { 60*4882a593Smuzhiyun compatible = "renesas,h8s-intc", "renesas,h8300-intc"; 61*4882a593Smuzhiyun #interrupt-cells = <2>; 62*4882a593Smuzhiyun interrupt-controller; 63*4882a593Smuzhiyun reg = <0xfffe00 24>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun bsc: memory-controller@fffec0 { 67*4882a593Smuzhiyun compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; 68*4882a593Smuzhiyun reg = <0xfffec0 24>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun tpu: timer@ffffe0 { 72*4882a593Smuzhiyun compatible = "renesas,tpu"; 73*4882a593Smuzhiyun reg = <0xffffe0 16>, <0xfffff0 12>; 74*4882a593Smuzhiyun clocks = <&fclk>; 75*4882a593Smuzhiyun clock-names = "fck"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun timer8: timer@ffffb0 { 79*4882a593Smuzhiyun compatible = "renesas,8bit-timer"; 80*4882a593Smuzhiyun reg = <0xffffb0 10>; 81*4882a593Smuzhiyun interrupts = <72 0>; 82*4882a593Smuzhiyun clocks = <&fclk>; 83*4882a593Smuzhiyun clock-names = "fck"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun sci0: serial@ffff78 { 87*4882a593Smuzhiyun compatible = "renesas,sci"; 88*4882a593Smuzhiyun reg = <0xffff78 8>; 89*4882a593Smuzhiyun interrupts = <88 0>, <89 0>, <90 0>, <91 0>; 90*4882a593Smuzhiyun clocks = <&fclk>; 91*4882a593Smuzhiyun clock-names = "fck"; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun sci1: serial@ffff80 { 94*4882a593Smuzhiyun compatible = "renesas,sci"; 95*4882a593Smuzhiyun reg = <0xffff80 8>; 96*4882a593Smuzhiyun interrupts = <92 0>, <93 0>, <94 0>, <95 0>; 97*4882a593Smuzhiyun clocks = <&fclk>; 98*4882a593Smuzhiyun clock-names = "fck"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101