1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DT_CS35L32_H 3*4882a593Smuzhiyun #define __DT_CS35L32_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define CS35L32_BOOST_MGR_AUTO 0 6*4882a593Smuzhiyun #define CS35L32_BOOST_MGR_AUTO_AUDIO 1 7*4882a593Smuzhiyun #define CS35L32_BOOST_MGR_BYPASS 2 8*4882a593Smuzhiyun #define CS35L32_BOOST_MGR_FIXED 3 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CS35L32_DATA_CFG_LR_VP 0 11*4882a593Smuzhiyun #define CS35L32_DATA_CFG_LR_STAT 1 12*4882a593Smuzhiyun #define CS35L32_DATA_CFG_LR 2 13*4882a593Smuzhiyun #define CS35L32_DATA_CFG_LR_VPSTAT 3 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CS35L32_BATT_THRESH_3_1V 0 16*4882a593Smuzhiyun #define CS35L32_BATT_THRESH_3_2V 1 17*4882a593Smuzhiyun #define CS35L32_BATT_THRESH_3_3V 2 18*4882a593Smuzhiyun #define CS35L32_BATT_THRESH_3_4V 3 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CS35L32_BATT_RECOV_3_1V 0 21*4882a593Smuzhiyun #define CS35L32_BATT_RECOV_3_2V 1 22*4882a593Smuzhiyun #define CS35L32_BATT_RECOV_3_3V 2 23*4882a593Smuzhiyun #define CS35L32_BATT_RECOV_3_4V 3 24*4882a593Smuzhiyun #define CS35L32_BATT_RECOV_3_5V 4 25*4882a593Smuzhiyun #define CS35L32_BATT_RECOV_3_6V 5 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #endif /* __DT_CS35L32_H */ 28