1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Realtek RTD1195 reset controllers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017 Andreas Färber 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef DT_BINDINGS_RESET_RTD1195_H 8*4882a593Smuzhiyun #define DT_BINDINGS_RESET_RTD1195_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* soft reset 1 */ 11*4882a593Smuzhiyun #define RTD1195_RSTN_MISC 0 12*4882a593Smuzhiyun #define RTD1195_RSTN_RNG 1 13*4882a593Smuzhiyun #define RTD1195_RSTN_USB3_POW 2 14*4882a593Smuzhiyun #define RTD1195_RSTN_GSPI 3 15*4882a593Smuzhiyun #define RTD1195_RSTN_USB3_P0_MDIO 4 16*4882a593Smuzhiyun #define RTD1195_RSTN_VE_H265 5 17*4882a593Smuzhiyun #define RTD1195_RSTN_USB 6 18*4882a593Smuzhiyun #define RTD1195_RSTN_USB_PHY0 8 19*4882a593Smuzhiyun #define RTD1195_RSTN_USB_PHY1 9 20*4882a593Smuzhiyun #define RTD1195_RSTN_HDMIRX 11 21*4882a593Smuzhiyun #define RTD1195_RSTN_HDMI 12 22*4882a593Smuzhiyun #define RTD1195_RSTN_ETN 14 23*4882a593Smuzhiyun #define RTD1195_RSTN_AIO 15 24*4882a593Smuzhiyun #define RTD1195_RSTN_GPU 16 25*4882a593Smuzhiyun #define RTD1195_RSTN_VE_H264 17 26*4882a593Smuzhiyun #define RTD1195_RSTN_VE_JPEG 18 27*4882a593Smuzhiyun #define RTD1195_RSTN_TVE 19 28*4882a593Smuzhiyun #define RTD1195_RSTN_VO 20 29*4882a593Smuzhiyun #define RTD1195_RSTN_LVDS 21 30*4882a593Smuzhiyun #define RTD1195_RSTN_SE 22 31*4882a593Smuzhiyun #define RTD1195_RSTN_DCU 23 32*4882a593Smuzhiyun #define RTD1195_RSTN_DC_PHY 24 33*4882a593Smuzhiyun #define RTD1195_RSTN_CP 25 34*4882a593Smuzhiyun #define RTD1195_RSTN_MD 26 35*4882a593Smuzhiyun #define RTD1195_RSTN_TP 27 36*4882a593Smuzhiyun #define RTD1195_RSTN_AE 28 37*4882a593Smuzhiyun #define RTD1195_RSTN_NF 29 38*4882a593Smuzhiyun #define RTD1195_RSTN_MIPI 30 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* soft reset 2 */ 41*4882a593Smuzhiyun #define RTD1195_RSTN_ACPU 0 42*4882a593Smuzhiyun #define RTD1195_RSTN_VCPU 1 43*4882a593Smuzhiyun #define RTD1195_RSTN_PCR 9 44*4882a593Smuzhiyun #define RTD1195_RSTN_CR 10 45*4882a593Smuzhiyun #define RTD1195_RSTN_EMMC 11 46*4882a593Smuzhiyun #define RTD1195_RSTN_SDIO 12 47*4882a593Smuzhiyun #define RTD1195_RSTN_I2C_5 18 48*4882a593Smuzhiyun #define RTD1195_RSTN_RTC 20 49*4882a593Smuzhiyun #define RTD1195_RSTN_I2C_4 23 50*4882a593Smuzhiyun #define RTD1195_RSTN_I2C_3 24 51*4882a593Smuzhiyun #define RTD1195_RSTN_I2C_2 25 52*4882a593Smuzhiyun #define RTD1195_RSTN_I2C_1 26 53*4882a593Smuzhiyun #define RTD1195_RSTN_UR1 28 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* soft reset 3 */ 56*4882a593Smuzhiyun #define RTD1195_RSTN_SB2 0 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* iso soft reset */ 59*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_VFD 0 60*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_IR 1 61*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_CEC0 2 62*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_CEC1 3 63*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_DP 4 64*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_CBUSTX 5 65*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_CBUSRX 6 66*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_EFUSE 7 67*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_UR0 8 68*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_GMAC 9 69*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_GPHY 10 70*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_I2C_0 11 71*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_I2C_6 12 72*4882a593Smuzhiyun #define RTD1195_ISO_RSTN_CBUS 13 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75