1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2020 NXP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef DT_BINDING_RESET_IMX8MP_H 7*4882a593Smuzhiyun #define DT_BINDING_RESET_IMX8MP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX8MP_RESET_A53_CORE_POR_RESET0 0 10*4882a593Smuzhiyun #define IMX8MP_RESET_A53_CORE_POR_RESET1 1 11*4882a593Smuzhiyun #define IMX8MP_RESET_A53_CORE_POR_RESET2 2 12*4882a593Smuzhiyun #define IMX8MP_RESET_A53_CORE_POR_RESET3 3 13*4882a593Smuzhiyun #define IMX8MP_RESET_A53_CORE_RESET0 4 14*4882a593Smuzhiyun #define IMX8MP_RESET_A53_CORE_RESET1 5 15*4882a593Smuzhiyun #define IMX8MP_RESET_A53_CORE_RESET2 6 16*4882a593Smuzhiyun #define IMX8MP_RESET_A53_CORE_RESET3 7 17*4882a593Smuzhiyun #define IMX8MP_RESET_A53_DBG_RESET0 8 18*4882a593Smuzhiyun #define IMX8MP_RESET_A53_DBG_RESET1 9 19*4882a593Smuzhiyun #define IMX8MP_RESET_A53_DBG_RESET2 10 20*4882a593Smuzhiyun #define IMX8MP_RESET_A53_DBG_RESET3 11 21*4882a593Smuzhiyun #define IMX8MP_RESET_A53_ETM_RESET0 12 22*4882a593Smuzhiyun #define IMX8MP_RESET_A53_ETM_RESET1 13 23*4882a593Smuzhiyun #define IMX8MP_RESET_A53_ETM_RESET2 14 24*4882a593Smuzhiyun #define IMX8MP_RESET_A53_ETM_RESET3 15 25*4882a593Smuzhiyun #define IMX8MP_RESET_A53_SOC_DBG_RESET 16 26*4882a593Smuzhiyun #define IMX8MP_RESET_A53_L2RESET 17 27*4882a593Smuzhiyun #define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 28*4882a593Smuzhiyun #define IMX8MP_RESET_OTG1_PHY_RESET 19 29*4882a593Smuzhiyun #define IMX8MP_RESET_OTG2_PHY_RESET 20 30*4882a593Smuzhiyun #define IMX8MP_RESET_SUPERMIX_RESET 21 31*4882a593Smuzhiyun #define IMX8MP_RESET_AUDIOMIX_RESET 22 32*4882a593Smuzhiyun #define IMX8MP_RESET_MLMIX_RESET 23 33*4882a593Smuzhiyun #define IMX8MP_RESET_PCIEPHY 24 34*4882a593Smuzhiyun #define IMX8MP_RESET_PCIEPHY_PERST 25 35*4882a593Smuzhiyun #define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 36*4882a593Smuzhiyun #define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 37*4882a593Smuzhiyun #define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 38*4882a593Smuzhiyun #define IMX8MP_RESET_MEDIA_RESET 29 39*4882a593Smuzhiyun #define IMX8MP_RESET_GPU2D_RESET 30 40*4882a593Smuzhiyun #define IMX8MP_RESET_GPU3D_RESET 31 41*4882a593Smuzhiyun #define IMX8MP_RESET_GPU_RESET 32 42*4882a593Smuzhiyun #define IMX8MP_RESET_VPU_RESET 33 43*4882a593Smuzhiyun #define IMX8MP_RESET_VPU_G1_RESET 34 44*4882a593Smuzhiyun #define IMX8MP_RESET_VPU_G2_RESET 35 45*4882a593Smuzhiyun #define IMX8MP_RESET_VPUVC8KE_RESET 36 46*4882a593Smuzhiyun #define IMX8MP_RESET_NOC_RESET 37 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define IMX8MP_RESET_NUM 38 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51