1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017 Impinj, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef DT_BINDING_RESET_IMX7_H 9*4882a593Smuzhiyun #define DT_BINDING_RESET_IMX7_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define IMX7_RESET_A7_CORE_POR_RESET0 0 12*4882a593Smuzhiyun #define IMX7_RESET_A7_CORE_POR_RESET1 1 13*4882a593Smuzhiyun #define IMX7_RESET_A7_CORE_RESET0 2 14*4882a593Smuzhiyun #define IMX7_RESET_A7_CORE_RESET1 3 15*4882a593Smuzhiyun #define IMX7_RESET_A7_DBG_RESET0 4 16*4882a593Smuzhiyun #define IMX7_RESET_A7_DBG_RESET1 5 17*4882a593Smuzhiyun #define IMX7_RESET_A7_ETM_RESET0 6 18*4882a593Smuzhiyun #define IMX7_RESET_A7_ETM_RESET1 7 19*4882a593Smuzhiyun #define IMX7_RESET_A7_SOC_DBG_RESET 8 20*4882a593Smuzhiyun #define IMX7_RESET_A7_L2RESET 9 21*4882a593Smuzhiyun #define IMX7_RESET_SW_M4C_RST 10 22*4882a593Smuzhiyun #define IMX7_RESET_SW_M4P_RST 11 23*4882a593Smuzhiyun #define IMX7_RESET_EIM_RST 12 24*4882a593Smuzhiyun #define IMX7_RESET_HSICPHY_PORT_RST 13 25*4882a593Smuzhiyun #define IMX7_RESET_USBPHY1_POR 14 26*4882a593Smuzhiyun #define IMX7_RESET_USBPHY1_PORT_RST 15 27*4882a593Smuzhiyun #define IMX7_RESET_USBPHY2_POR 16 28*4882a593Smuzhiyun #define IMX7_RESET_USBPHY2_PORT_RST 17 29*4882a593Smuzhiyun #define IMX7_RESET_MIPI_PHY_MRST 18 30*4882a593Smuzhiyun #define IMX7_RESET_MIPI_PHY_SRST 19 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN 34*4882a593Smuzhiyun * and PCIEPHY_G_RST 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define IMX7_RESET_PCIEPHY 20 37*4882a593Smuzhiyun #define IMX7_RESET_PCIEPHY_PERST 21 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it 41*4882a593Smuzhiyun * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht 42*4882a593Smuzhiyun * of as one 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 45*4882a593Smuzhiyun #define IMX7_RESET_DDRC_PRST 23 46*4882a593Smuzhiyun #define IMX7_RESET_DDRC_CORE_RST 24 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define IMX7_RESET_NUM 26 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54