1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H 5*4882a593Smuzhiyun #define _DT_BINDINGS_POWER_QCOM_RPMPD_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* SDM845 Power Domain Indexes */ 8*4882a593Smuzhiyun #define SDM845_EBI 0 9*4882a593Smuzhiyun #define SDM845_MX 1 10*4882a593Smuzhiyun #define SDM845_MX_AO 2 11*4882a593Smuzhiyun #define SDM845_CX 3 12*4882a593Smuzhiyun #define SDM845_CX_AO 4 13*4882a593Smuzhiyun #define SDM845_LMX 5 14*4882a593Smuzhiyun #define SDM845_LCX 6 15*4882a593Smuzhiyun #define SDM845_GFX 7 16*4882a593Smuzhiyun #define SDM845_MSS 8 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* SM8150 Power Domain Indexes */ 19*4882a593Smuzhiyun #define SM8150_MSS 0 20*4882a593Smuzhiyun #define SM8150_EBI 1 21*4882a593Smuzhiyun #define SM8150_LMX 2 22*4882a593Smuzhiyun #define SM8150_LCX 3 23*4882a593Smuzhiyun #define SM8150_GFX 4 24*4882a593Smuzhiyun #define SM8150_MX 5 25*4882a593Smuzhiyun #define SM8150_MX_AO 6 26*4882a593Smuzhiyun #define SM8150_CX 7 27*4882a593Smuzhiyun #define SM8150_CX_AO 8 28*4882a593Smuzhiyun #define SM8150_MMCX 9 29*4882a593Smuzhiyun #define SM8150_MMCX_AO 10 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SM8250 Power Domain Indexes */ 32*4882a593Smuzhiyun #define SM8250_CX 0 33*4882a593Smuzhiyun #define SM8250_CX_AO 1 34*4882a593Smuzhiyun #define SM8250_EBI 2 35*4882a593Smuzhiyun #define SM8250_GFX 3 36*4882a593Smuzhiyun #define SM8250_LCX 4 37*4882a593Smuzhiyun #define SM8250_LMX 5 38*4882a593Smuzhiyun #define SM8250_MMCX 6 39*4882a593Smuzhiyun #define SM8250_MMCX_AO 7 40*4882a593Smuzhiyun #define SM8250_MX 8 41*4882a593Smuzhiyun #define SM8250_MX_AO 9 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* SC7180 Power Domain Indexes */ 44*4882a593Smuzhiyun #define SC7180_CX 0 45*4882a593Smuzhiyun #define SC7180_CX_AO 1 46*4882a593Smuzhiyun #define SC7180_GFX 2 47*4882a593Smuzhiyun #define SC7180_MX 3 48*4882a593Smuzhiyun #define SC7180_MX_AO 4 49*4882a593Smuzhiyun #define SC7180_LMX 5 50*4882a593Smuzhiyun #define SC7180_LCX 6 51*4882a593Smuzhiyun #define SC7180_MSS 7 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* SDM845 Power Domain performance levels */ 54*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_RETENTION 16 55*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 56*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 57*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_SVS 128 58*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_SVS_L0 144 59*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_SVS_L1 192 60*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_SVS_L2 224 61*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_NOM 256 62*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_NOM_L1 320 63*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_NOM_L2 336 64*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_TURBO 384 65*4882a593Smuzhiyun #define RPMH_REGULATOR_LEVEL_TURBO_L1 416 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* MSM8976 Power Domain Indexes */ 68*4882a593Smuzhiyun #define MSM8976_VDDCX 0 69*4882a593Smuzhiyun #define MSM8976_VDDCX_AO 1 70*4882a593Smuzhiyun #define MSM8976_VDDCX_VFL 2 71*4882a593Smuzhiyun #define MSM8976_VDDMX 3 72*4882a593Smuzhiyun #define MSM8976_VDDMX_AO 4 73*4882a593Smuzhiyun #define MSM8976_VDDMX_VFL 5 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* MSM8996 Power Domain Indexes */ 76*4882a593Smuzhiyun #define MSM8996_VDDCX 0 77*4882a593Smuzhiyun #define MSM8996_VDDCX_AO 1 78*4882a593Smuzhiyun #define MSM8996_VDDCX_VFC 2 79*4882a593Smuzhiyun #define MSM8996_VDDMX 3 80*4882a593Smuzhiyun #define MSM8996_VDDMX_AO 4 81*4882a593Smuzhiyun #define MSM8996_VDDSSCX 5 82*4882a593Smuzhiyun #define MSM8996_VDDSSCX_VFC 6 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* MSM8998 Power Domain Indexes */ 85*4882a593Smuzhiyun #define MSM8998_VDDCX 0 86*4882a593Smuzhiyun #define MSM8998_VDDCX_AO 1 87*4882a593Smuzhiyun #define MSM8998_VDDCX_VFL 2 88*4882a593Smuzhiyun #define MSM8998_VDDMX 3 89*4882a593Smuzhiyun #define MSM8998_VDDMX_AO 4 90*4882a593Smuzhiyun #define MSM8998_VDDMX_VFL 5 91*4882a593Smuzhiyun #define MSM8998_SSCCX 6 92*4882a593Smuzhiyun #define MSM8998_SSCCX_VFL 7 93*4882a593Smuzhiyun #define MSM8998_SSCMX 8 94*4882a593Smuzhiyun #define MSM8998_SSCMX_VFL 9 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* QCS404 Power Domains */ 97*4882a593Smuzhiyun #define QCS404_VDDMX 0 98*4882a593Smuzhiyun #define QCS404_VDDMX_AO 1 99*4882a593Smuzhiyun #define QCS404_VDDMX_VFL 2 100*4882a593Smuzhiyun #define QCS404_LPICX 3 101*4882a593Smuzhiyun #define QCS404_LPICX_VFL 4 102*4882a593Smuzhiyun #define QCS404_LPIMX 5 103*4882a593Smuzhiyun #define QCS404_LPIMX_VFL 6 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* RPM SMD Power Domain performance levels */ 106*4882a593Smuzhiyun #define RPM_SMD_LEVEL_RETENTION 16 107*4882a593Smuzhiyun #define RPM_SMD_LEVEL_RETENTION_PLUS 32 108*4882a593Smuzhiyun #define RPM_SMD_LEVEL_MIN_SVS 48 109*4882a593Smuzhiyun #define RPM_SMD_LEVEL_LOW_SVS 64 110*4882a593Smuzhiyun #define RPM_SMD_LEVEL_SVS 128 111*4882a593Smuzhiyun #define RPM_SMD_LEVEL_SVS_PLUS 192 112*4882a593Smuzhiyun #define RPM_SMD_LEVEL_NOM 256 113*4882a593Smuzhiyun #define RPM_SMD_LEVEL_NOM_PLUS 320 114*4882a593Smuzhiyun #define RPM_SMD_LEVEL_TURBO 384 115*4882a593Smuzhiyun #define RPM_SMD_LEVEL_TURBO_NO_CPR 416 116*4882a593Smuzhiyun #define RPM_SMD_LEVEL_TURBO_HIGH 448 117*4882a593Smuzhiyun #define RPM_SMD_LEVEL_BINNING 512 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #endif 120