1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 Amlogic, Inc. 4*4882a593Smuzhiyun * Author: Jianxin Pan <jianxin.pan@amlogic.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_MESON_A1_POWER_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_MESON_A1_POWER_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define PWRC_DSPA_ID 8 11*4882a593Smuzhiyun #define PWRC_DSPB_ID 9 12*4882a593Smuzhiyun #define PWRC_UART_ID 10 13*4882a593Smuzhiyun #define PWRC_DMC_ID 11 14*4882a593Smuzhiyun #define PWRC_I2C_ID 12 15*4882a593Smuzhiyun #define PWRC_PSRAM_ID 13 16*4882a593Smuzhiyun #define PWRC_ACODEC_ID 14 17*4882a593Smuzhiyun #define PWRC_AUDIO_ID 15 18*4882a593Smuzhiyun #define PWRC_OTP_ID 16 19*4882a593Smuzhiyun #define PWRC_DMA_ID 17 20*4882a593Smuzhiyun #define PWRC_SD_EMMC_ID 18 21*4882a593Smuzhiyun #define PWRC_RAMA_ID 19 22*4882a593Smuzhiyun #define PWRC_RAMB_ID 20 23*4882a593Smuzhiyun #define PWRC_IR_ID 21 24*4882a593Smuzhiyun #define PWRC_SPICC_ID 22 25*4882a593Smuzhiyun #define PWRC_SPIFC_ID 23 26*4882a593Smuzhiyun #define PWRC_USB_ID 24 27*4882a593Smuzhiyun #define PWRC_NIC_ID 25 28*4882a593Smuzhiyun #define PWRC_PDMIN_ID 26 29*4882a593Smuzhiyun #define PWRC_RSA_ID 27 30*4882a593Smuzhiyun #define PWRC_MAX_ID 28 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif 33