1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Samsung's Exynos pinctrl bindings 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6*4882a593Smuzhiyun * http://www.samsung.com 7*4882a593Smuzhiyun * Author: Krzysztof Kozlowski <krzk@kernel.org> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 11*4882a593Smuzhiyun #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define EXYNOS_PIN_PULL_NONE 0 14*4882a593Smuzhiyun #define EXYNOS_PIN_PULL_DOWN 1 15*4882a593Smuzhiyun #define EXYNOS_PIN_PULL_UP 3 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define S3C64XX_PIN_PULL_NONE 0 18*4882a593Smuzhiyun #define S3C64XX_PIN_PULL_DOWN 1 19*4882a593Smuzhiyun #define S3C64XX_PIN_PULL_UP 2 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Pin function in power down mode */ 22*4882a593Smuzhiyun #define EXYNOS_PIN_PDN_OUT0 0 23*4882a593Smuzhiyun #define EXYNOS_PIN_PDN_OUT1 1 24*4882a593Smuzhiyun #define EXYNOS_PIN_PDN_INPUT 2 25*4882a593Smuzhiyun #define EXYNOS_PIN_PDN_PREV 3 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ 28*4882a593Smuzhiyun #define EXYNOS4_PIN_DRV_LV1 0 29*4882a593Smuzhiyun #define EXYNOS4_PIN_DRV_LV2 2 30*4882a593Smuzhiyun #define EXYNOS4_PIN_DRV_LV3 1 31*4882a593Smuzhiyun #define EXYNOS4_PIN_DRV_LV4 3 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Drive strengths for Exynos5260 */ 34*4882a593Smuzhiyun #define EXYNOS5260_PIN_DRV_LV1 0 35*4882a593Smuzhiyun #define EXYNOS5260_PIN_DRV_LV2 1 36*4882a593Smuzhiyun #define EXYNOS5260_PIN_DRV_LV4 2 37*4882a593Smuzhiyun #define EXYNOS5260_PIN_DRV_LV6 3 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ 40*4882a593Smuzhiyun #define EXYNOS5420_PIN_DRV_LV1 0 41*4882a593Smuzhiyun #define EXYNOS5420_PIN_DRV_LV2 1 42*4882a593Smuzhiyun #define EXYNOS5420_PIN_DRV_LV3 2 43*4882a593Smuzhiyun #define EXYNOS5420_PIN_DRV_LV4 3 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Drive strengths for Exynos5433 */ 46*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_FAST_SR1 0 47*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_FAST_SR2 1 48*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_FAST_SR3 2 49*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_FAST_SR4 3 50*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_FAST_SR5 4 51*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_FAST_SR6 5 52*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_SLOW_SR1 8 53*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_SLOW_SR2 9 54*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa 55*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb 56*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc 57*4882a593Smuzhiyun #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_INPUT 0 60*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_OUTPUT 1 61*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_2 2 62*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_3 3 63*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_4 4 64*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_5 5 65*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_6 6 66*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_EINT 0xf 67*4882a593Smuzhiyun #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Drive strengths for Exynos7 FSYS1 block */ 70*4882a593Smuzhiyun #define EXYNOS7_FSYS1_PIN_DRV_LV1 0 71*4882a593Smuzhiyun #define EXYNOS7_FSYS1_PIN_DRV_LV2 4 72*4882a593Smuzhiyun #define EXYNOS7_FSYS1_PIN_DRV_LV3 2 73*4882a593Smuzhiyun #define EXYNOS7_FSYS1_PIN_DRV_LV4 6 74*4882a593Smuzhiyun #define EXYNOS7_FSYS1_PIN_DRV_LV5 1 75*4882a593Smuzhiyun #define EXYNOS7_FSYS1_PIN_DRV_LV6 5 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ 78