1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device Tree constants for the Texas Instruments DP83869 PHY 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Dan Murphy <dmurphy@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright: (C) 2019 Texas Instruments, Inc. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _DT_BINDINGS_TI_DP83869_H 11*4882a593Smuzhiyun #define _DT_BINDINGS_TI_DP83869_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* PHY CTRL bits */ 14*4882a593Smuzhiyun #define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 15*4882a593Smuzhiyun #define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 16*4882a593Smuzhiyun #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 17*4882a593Smuzhiyun #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* IO_MUX_CFG - Clock output selection */ 20*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 21*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 22*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 23*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 24*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 25*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 26*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 27*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 28*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 29*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 30*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa 31*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb 32*4882a593Smuzhiyun #define DP83869_CLK_O_SEL_REF_CLK 0xc 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define DP83869_RGMII_COPPER_ETHERNET 0x00 35*4882a593Smuzhiyun #define DP83869_RGMII_1000_BASE 0x01 36*4882a593Smuzhiyun #define DP83869_RGMII_100_BASE 0x02 37*4882a593Smuzhiyun #define DP83869_RGMII_SGMII_BRIDGE 0x03 38*4882a593Smuzhiyun #define DP83869_1000M_MEDIA_CONVERT 0x04 39*4882a593Smuzhiyun #define DP83869_100M_MEDIA_CONVERT 0x05 40*4882a593Smuzhiyun #define DP83869_SGMII_COPPER_ETHERNET 0x06 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif 43