1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device Tree constants for the Texas Instruments DP83867 PHY 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Dan Murphy <dmurphy@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright: (C) 2015 Texas Instruments, Inc. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _DT_BINDINGS_TI_DP83867_H 11*4882a593Smuzhiyun #define _DT_BINDINGS_TI_DP83867_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* PHY CTRL bits */ 14*4882a593Smuzhiyun #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 15*4882a593Smuzhiyun #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 16*4882a593Smuzhiyun #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 17*4882a593Smuzhiyun #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* RGMIIDCTL internal delay for rx and tx */ 20*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_250_PS 0x0 21*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_500_PS 0x1 22*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_750_PS 0x2 23*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_1_NS 0x3 24*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_1_25_NS 0x4 25*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_1_50_NS 0x5 26*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_1_75_NS 0x6 27*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_2_00_NS 0x7 28*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_2_25_NS 0x8 29*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_2_50_NS 0x9 30*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_2_75_NS 0xa 31*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_3_00_NS 0xb 32*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_3_25_NS 0xc 33*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_3_50_NS 0xd 34*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_3_75_NS 0xe 35*4882a593Smuzhiyun #define DP83867_RGMIIDCTL_4_00_NS 0xf 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* IO_MUX_CFG - Clock output selection */ 38*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 39*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 40*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 41*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 42*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 43*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 44*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 45*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 46*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 47*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 48*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 49*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 50*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_REF_CLK 0xC 51*4882a593Smuzhiyun /* Special flag to indicate clock should be off */ 52*4882a593Smuzhiyun #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF 53*4882a593Smuzhiyun #endif 54