1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H 3*4882a593Smuzhiyun #define DT_BINDINGS_MEMORY_TEGRA30_MC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define TEGRA_SWGROUP_PTC 0 6*4882a593Smuzhiyun #define TEGRA_SWGROUP_DC 1 7*4882a593Smuzhiyun #define TEGRA_SWGROUP_DCB 2 8*4882a593Smuzhiyun #define TEGRA_SWGROUP_EPP 3 9*4882a593Smuzhiyun #define TEGRA_SWGROUP_G2 4 10*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPE 5 11*4882a593Smuzhiyun #define TEGRA_SWGROUP_VI 6 12*4882a593Smuzhiyun #define TEGRA_SWGROUP_AFI 7 13*4882a593Smuzhiyun #define TEGRA_SWGROUP_AVPC 8 14*4882a593Smuzhiyun #define TEGRA_SWGROUP_NV 9 15*4882a593Smuzhiyun #define TEGRA_SWGROUP_NV2 10 16*4882a593Smuzhiyun #define TEGRA_SWGROUP_HDA 11 17*4882a593Smuzhiyun #define TEGRA_SWGROUP_HC 12 18*4882a593Smuzhiyun #define TEGRA_SWGROUP_PPCS 13 19*4882a593Smuzhiyun #define TEGRA_SWGROUP_SATA 14 20*4882a593Smuzhiyun #define TEGRA_SWGROUP_VDE 15 21*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORELP 16 22*4882a593Smuzhiyun #define TEGRA_SWGROUP_MPCORE 17 23*4882a593Smuzhiyun #define TEGRA_SWGROUP_ISP 18 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define TEGRA30_MC_RESET_AFI 0 26*4882a593Smuzhiyun #define TEGRA30_MC_RESET_AVPC 1 27*4882a593Smuzhiyun #define TEGRA30_MC_RESET_DC 2 28*4882a593Smuzhiyun #define TEGRA30_MC_RESET_DCB 3 29*4882a593Smuzhiyun #define TEGRA30_MC_RESET_EPP 4 30*4882a593Smuzhiyun #define TEGRA30_MC_RESET_2D 5 31*4882a593Smuzhiyun #define TEGRA30_MC_RESET_HC 6 32*4882a593Smuzhiyun #define TEGRA30_MC_RESET_HDA 7 33*4882a593Smuzhiyun #define TEGRA30_MC_RESET_ISP 8 34*4882a593Smuzhiyun #define TEGRA30_MC_RESET_MPCORE 9 35*4882a593Smuzhiyun #define TEGRA30_MC_RESET_MPCORELP 10 36*4882a593Smuzhiyun #define TEGRA30_MC_RESET_MPE 11 37*4882a593Smuzhiyun #define TEGRA30_MC_RESET_3D 12 38*4882a593Smuzhiyun #define TEGRA30_MC_RESET_3D2 13 39*4882a593Smuzhiyun #define TEGRA30_MC_RESET_PPCS 14 40*4882a593Smuzhiyun #define TEGRA30_MC_RESET_SATA 15 41*4882a593Smuzhiyun #define TEGRA30_MC_RESET_VDE 16 42*4882a593Smuzhiyun #define TEGRA30_MC_RESET_VI 17 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif 45