1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ 4*4882a593Smuzhiyun #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define ASPEED_SCU_IC_VGA_CURSOR_CHANGE 0 7*4882a593Smuzhiyun #define ASPEED_SCU_IC_VGA_SCRATCH_REG_CHANGE 1 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI 2 10*4882a593Smuzhiyun #define ASPEED_AST2500_SCU_IC_PCIE_RESET_HI_TO_LO 3 11*4882a593Smuzhiyun #define ASPEED_AST2500_SCU_IC_LPC_RESET_LO_TO_HI 4 12*4882a593Smuzhiyun #define ASPEED_AST2500_SCU_IC_LPC_RESET_HI_TO_LO 5 13*4882a593Smuzhiyun #define ASPEED_AST2500_SCU_IC_ISSUE_MSI 6 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI 2 16*4882a593Smuzhiyun #define ASPEED_AST2600_SCU_IC0_PCIE_PERST_HI_TO_LO 3 17*4882a593Smuzhiyun #define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_LO_TO_HI 4 18*4882a593Smuzhiyun #define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_HI_TO_LO 5 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0 21*4882a593Smuzhiyun #define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */ 24