1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree binding constants for Samsung S3C64xx clock controller. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Let each exported clock get a unique index, which is used on DT-enabled 13*4882a593Smuzhiyun * platforms to lookup the clock from a clock specifier. These indices are 14*4882a593Smuzhiyun * therefore considered an ABI and so must not be changed. This implies 15*4882a593Smuzhiyun * that new clocks should be added either in free spaces between clock groups 16*4882a593Smuzhiyun * or at the end. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Core clocks. */ 20*4882a593Smuzhiyun #define CLK27M 1 21*4882a593Smuzhiyun #define CLK48M 2 22*4882a593Smuzhiyun #define FOUT_APLL 3 23*4882a593Smuzhiyun #define FOUT_MPLL 4 24*4882a593Smuzhiyun #define FOUT_EPLL 5 25*4882a593Smuzhiyun #define ARMCLK 6 26*4882a593Smuzhiyun #define HCLKX2 7 27*4882a593Smuzhiyun #define HCLK 8 28*4882a593Smuzhiyun #define PCLK 9 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* HCLK bus clocks. */ 31*4882a593Smuzhiyun #define HCLK_3DSE 16 32*4882a593Smuzhiyun #define HCLK_UHOST 17 33*4882a593Smuzhiyun #define HCLK_SECUR 18 34*4882a593Smuzhiyun #define HCLK_SDMA1 19 35*4882a593Smuzhiyun #define HCLK_SDMA0 20 36*4882a593Smuzhiyun #define HCLK_IROM 21 37*4882a593Smuzhiyun #define HCLK_DDR1 22 38*4882a593Smuzhiyun #define HCLK_MEM1 23 39*4882a593Smuzhiyun #define HCLK_MEM0 24 40*4882a593Smuzhiyun #define HCLK_USB 25 41*4882a593Smuzhiyun #define HCLK_HSMMC2 26 42*4882a593Smuzhiyun #define HCLK_HSMMC1 27 43*4882a593Smuzhiyun #define HCLK_HSMMC0 28 44*4882a593Smuzhiyun #define HCLK_MDP 29 45*4882a593Smuzhiyun #define HCLK_DHOST 30 46*4882a593Smuzhiyun #define HCLK_IHOST 31 47*4882a593Smuzhiyun #define HCLK_DMA1 32 48*4882a593Smuzhiyun #define HCLK_DMA0 33 49*4882a593Smuzhiyun #define HCLK_JPEG 34 50*4882a593Smuzhiyun #define HCLK_CAMIF 35 51*4882a593Smuzhiyun #define HCLK_SCALER 36 52*4882a593Smuzhiyun #define HCLK_2D 37 53*4882a593Smuzhiyun #define HCLK_TV 38 54*4882a593Smuzhiyun #define HCLK_POST0 39 55*4882a593Smuzhiyun #define HCLK_ROT 40 56*4882a593Smuzhiyun #define HCLK_LCD 41 57*4882a593Smuzhiyun #define HCLK_TZIC 42 58*4882a593Smuzhiyun #define HCLK_INTC 43 59*4882a593Smuzhiyun #define HCLK_MFC 44 60*4882a593Smuzhiyun #define HCLK_DDR0 45 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* PCLK bus clocks. */ 63*4882a593Smuzhiyun #define PCLK_IIC1 48 64*4882a593Smuzhiyun #define PCLK_IIS2 49 65*4882a593Smuzhiyun #define PCLK_SKEY 50 66*4882a593Smuzhiyun #define PCLK_CHIPID 51 67*4882a593Smuzhiyun #define PCLK_SPI1 52 68*4882a593Smuzhiyun #define PCLK_SPI0 53 69*4882a593Smuzhiyun #define PCLK_HSIRX 54 70*4882a593Smuzhiyun #define PCLK_HSITX 55 71*4882a593Smuzhiyun #define PCLK_GPIO 56 72*4882a593Smuzhiyun #define PCLK_IIC0 57 73*4882a593Smuzhiyun #define PCLK_IIS1 58 74*4882a593Smuzhiyun #define PCLK_IIS0 59 75*4882a593Smuzhiyun #define PCLK_AC97 60 76*4882a593Smuzhiyun #define PCLK_TZPC 61 77*4882a593Smuzhiyun #define PCLK_TSADC 62 78*4882a593Smuzhiyun #define PCLK_KEYPAD 63 79*4882a593Smuzhiyun #define PCLK_IRDA 64 80*4882a593Smuzhiyun #define PCLK_PCM1 65 81*4882a593Smuzhiyun #define PCLK_PCM0 66 82*4882a593Smuzhiyun #define PCLK_PWM 67 83*4882a593Smuzhiyun #define PCLK_RTC 68 84*4882a593Smuzhiyun #define PCLK_WDT 69 85*4882a593Smuzhiyun #define PCLK_UART3 70 86*4882a593Smuzhiyun #define PCLK_UART2 71 87*4882a593Smuzhiyun #define PCLK_UART1 72 88*4882a593Smuzhiyun #define PCLK_UART0 73 89*4882a593Smuzhiyun #define PCLK_MFC 74 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Special clocks. */ 92*4882a593Smuzhiyun #define SCLK_UHOST 80 93*4882a593Smuzhiyun #define SCLK_MMC2_48 81 94*4882a593Smuzhiyun #define SCLK_MMC1_48 82 95*4882a593Smuzhiyun #define SCLK_MMC0_48 83 96*4882a593Smuzhiyun #define SCLK_MMC2 84 97*4882a593Smuzhiyun #define SCLK_MMC1 85 98*4882a593Smuzhiyun #define SCLK_MMC0 86 99*4882a593Smuzhiyun #define SCLK_SPI1_48 87 100*4882a593Smuzhiyun #define SCLK_SPI0_48 88 101*4882a593Smuzhiyun #define SCLK_SPI1 89 102*4882a593Smuzhiyun #define SCLK_SPI0 90 103*4882a593Smuzhiyun #define SCLK_DAC27 91 104*4882a593Smuzhiyun #define SCLK_TV27 92 105*4882a593Smuzhiyun #define SCLK_SCALER27 93 106*4882a593Smuzhiyun #define SCLK_SCALER 94 107*4882a593Smuzhiyun #define SCLK_LCD27 95 108*4882a593Smuzhiyun #define SCLK_LCD 96 109*4882a593Smuzhiyun #define SCLK_FIMC 97 110*4882a593Smuzhiyun #define SCLK_POST0_27 98 111*4882a593Smuzhiyun #define SCLK_AUDIO2 99 112*4882a593Smuzhiyun #define SCLK_POST0 100 113*4882a593Smuzhiyun #define SCLK_AUDIO1 101 114*4882a593Smuzhiyun #define SCLK_AUDIO0 102 115*4882a593Smuzhiyun #define SCLK_SECUR 103 116*4882a593Smuzhiyun #define SCLK_IRDA 104 117*4882a593Smuzhiyun #define SCLK_UART 105 118*4882a593Smuzhiyun #define SCLK_MFC 106 119*4882a593Smuzhiyun #define SCLK_CAM 107 120*4882a593Smuzhiyun #define SCLK_JPEG 108 121*4882a593Smuzhiyun #define SCLK_ONENAND 109 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* MEM0 bus clocks - S3C6410-specific. */ 124*4882a593Smuzhiyun #define MEM0_CFCON 112 125*4882a593Smuzhiyun #define MEM0_ONENAND1 113 126*4882a593Smuzhiyun #define MEM0_ONENAND0 114 127*4882a593Smuzhiyun #define MEM0_NFCON 115 128*4882a593Smuzhiyun #define MEM0_SROM 116 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* Muxes. */ 131*4882a593Smuzhiyun #define MOUT_APLL 128 132*4882a593Smuzhiyun #define MOUT_MPLL 129 133*4882a593Smuzhiyun #define MOUT_EPLL 130 134*4882a593Smuzhiyun #define MOUT_MFC 131 135*4882a593Smuzhiyun #define MOUT_AUDIO0 132 136*4882a593Smuzhiyun #define MOUT_AUDIO1 133 137*4882a593Smuzhiyun #define MOUT_UART 134 138*4882a593Smuzhiyun #define MOUT_SPI0 135 139*4882a593Smuzhiyun #define MOUT_SPI1 136 140*4882a593Smuzhiyun #define MOUT_MMC0 137 141*4882a593Smuzhiyun #define MOUT_MMC1 138 142*4882a593Smuzhiyun #define MOUT_MMC2 139 143*4882a593Smuzhiyun #define MOUT_UHOST 140 144*4882a593Smuzhiyun #define MOUT_IRDA 141 145*4882a593Smuzhiyun #define MOUT_LCD 142 146*4882a593Smuzhiyun #define MOUT_SCALER 143 147*4882a593Smuzhiyun #define MOUT_DAC27 144 148*4882a593Smuzhiyun #define MOUT_TV27 145 149*4882a593Smuzhiyun #define MOUT_AUDIO2 146 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* Dividers. */ 152*4882a593Smuzhiyun #define DOUT_MPLL 160 153*4882a593Smuzhiyun #define DOUT_SECUR 161 154*4882a593Smuzhiyun #define DOUT_CAM 162 155*4882a593Smuzhiyun #define DOUT_JPEG 163 156*4882a593Smuzhiyun #define DOUT_MFC 164 157*4882a593Smuzhiyun #define DOUT_MMC0 165 158*4882a593Smuzhiyun #define DOUT_MMC1 166 159*4882a593Smuzhiyun #define DOUT_MMC2 167 160*4882a593Smuzhiyun #define DOUT_LCD 168 161*4882a593Smuzhiyun #define DOUT_SCALER 169 162*4882a593Smuzhiyun #define DOUT_UHOST 170 163*4882a593Smuzhiyun #define DOUT_SPI0 171 164*4882a593Smuzhiyun #define DOUT_SPI1 172 165*4882a593Smuzhiyun #define DOUT_AUDIO0 173 166*4882a593Smuzhiyun #define DOUT_AUDIO1 174 167*4882a593Smuzhiyun #define DOUT_UART 175 168*4882a593Smuzhiyun #define DOUT_IRDA 176 169*4882a593Smuzhiyun #define DOUT_FIMC 177 170*4882a593Smuzhiyun #define DOUT_AUDIO2 178 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* Total number of clocks. */ 173*4882a593Smuzhiyun #define NR_CLKS (DOUT_AUDIO2 + 1) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ 176