1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation 4*4882a593Smuzhiyun * Copyright 2013 Ideas On Board SPRL 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ 8*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7794_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* CPG */ 11*4882a593Smuzhiyun #define R8A7794_CLK_MAIN 0 12*4882a593Smuzhiyun #define R8A7794_CLK_PLL0 1 13*4882a593Smuzhiyun #define R8A7794_CLK_PLL1 2 14*4882a593Smuzhiyun #define R8A7794_CLK_PLL3 3 15*4882a593Smuzhiyun #define R8A7794_CLK_LB 4 16*4882a593Smuzhiyun #define R8A7794_CLK_QSPI 5 17*4882a593Smuzhiyun #define R8A7794_CLK_SDH 6 18*4882a593Smuzhiyun #define R8A7794_CLK_SD0 7 19*4882a593Smuzhiyun #define R8A7794_CLK_RCAN 8 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* MSTP0 */ 22*4882a593Smuzhiyun #define R8A7794_CLK_MSIOF0 0 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* MSTP1 */ 25*4882a593Smuzhiyun #define R8A7794_CLK_VCP0 1 26*4882a593Smuzhiyun #define R8A7794_CLK_VPC0 3 27*4882a593Smuzhiyun #define R8A7794_CLK_TMU1 11 28*4882a593Smuzhiyun #define R8A7794_CLK_3DG 12 29*4882a593Smuzhiyun #define R8A7794_CLK_2DDMAC 15 30*4882a593Smuzhiyun #define R8A7794_CLK_FDP1_0 19 31*4882a593Smuzhiyun #define R8A7794_CLK_TMU3 21 32*4882a593Smuzhiyun #define R8A7794_CLK_TMU2 22 33*4882a593Smuzhiyun #define R8A7794_CLK_CMT0 24 34*4882a593Smuzhiyun #define R8A7794_CLK_TMU0 25 35*4882a593Smuzhiyun #define R8A7794_CLK_VSP1_DU0 28 36*4882a593Smuzhiyun #define R8A7794_CLK_VSP1_S 31 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* MSTP2 */ 39*4882a593Smuzhiyun #define R8A7794_CLK_SCIFA2 2 40*4882a593Smuzhiyun #define R8A7794_CLK_SCIFA1 3 41*4882a593Smuzhiyun #define R8A7794_CLK_SCIFA0 4 42*4882a593Smuzhiyun #define R8A7794_CLK_MSIOF2 5 43*4882a593Smuzhiyun #define R8A7794_CLK_SCIFB0 6 44*4882a593Smuzhiyun #define R8A7794_CLK_SCIFB1 7 45*4882a593Smuzhiyun #define R8A7794_CLK_MSIOF1 8 46*4882a593Smuzhiyun #define R8A7794_CLK_SCIFB2 16 47*4882a593Smuzhiyun #define R8A7794_CLK_SYS_DMAC1 18 48*4882a593Smuzhiyun #define R8A7794_CLK_SYS_DMAC0 19 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* MSTP3 */ 51*4882a593Smuzhiyun #define R8A7794_CLK_SDHI2 11 52*4882a593Smuzhiyun #define R8A7794_CLK_SDHI1 12 53*4882a593Smuzhiyun #define R8A7794_CLK_SDHI0 14 54*4882a593Smuzhiyun #define R8A7794_CLK_MMCIF0 15 55*4882a593Smuzhiyun #define R8A7794_CLK_IIC0 18 56*4882a593Smuzhiyun #define R8A7794_CLK_IIC1 23 57*4882a593Smuzhiyun #define R8A7794_CLK_CMT1 29 58*4882a593Smuzhiyun #define R8A7794_CLK_USBDMAC0 30 59*4882a593Smuzhiyun #define R8A7794_CLK_USBDMAC1 31 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* MSTP4 */ 62*4882a593Smuzhiyun #define R8A7794_CLK_IRQC 7 63*4882a593Smuzhiyun #define R8A7794_CLK_INTC_SYS 8 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* MSTP5 */ 66*4882a593Smuzhiyun #define R8A7794_CLK_AUDIO_DMAC0 2 67*4882a593Smuzhiyun #define R8A7794_CLK_PWM 23 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* MSTP7 */ 70*4882a593Smuzhiyun #define R8A7794_CLK_EHCI 3 71*4882a593Smuzhiyun #define R8A7794_CLK_HSUSB 4 72*4882a593Smuzhiyun #define R8A7794_CLK_HSCIF2 13 73*4882a593Smuzhiyun #define R8A7794_CLK_SCIF5 14 74*4882a593Smuzhiyun #define R8A7794_CLK_SCIF4 15 75*4882a593Smuzhiyun #define R8A7794_CLK_HSCIF1 16 76*4882a593Smuzhiyun #define R8A7794_CLK_HSCIF0 17 77*4882a593Smuzhiyun #define R8A7794_CLK_SCIF3 18 78*4882a593Smuzhiyun #define R8A7794_CLK_SCIF2 19 79*4882a593Smuzhiyun #define R8A7794_CLK_SCIF1 20 80*4882a593Smuzhiyun #define R8A7794_CLK_SCIF0 21 81*4882a593Smuzhiyun #define R8A7794_CLK_DU1 23 82*4882a593Smuzhiyun #define R8A7794_CLK_DU0 24 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* MSTP8 */ 85*4882a593Smuzhiyun #define R8A7794_CLK_VIN1 10 86*4882a593Smuzhiyun #define R8A7794_CLK_VIN0 11 87*4882a593Smuzhiyun #define R8A7794_CLK_ETHERAVB 12 88*4882a593Smuzhiyun #define R8A7794_CLK_ETHER 13 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* MSTP9 */ 91*4882a593Smuzhiyun #define R8A7794_CLK_GPIO6 5 92*4882a593Smuzhiyun #define R8A7794_CLK_GPIO5 7 93*4882a593Smuzhiyun #define R8A7794_CLK_GPIO4 8 94*4882a593Smuzhiyun #define R8A7794_CLK_GPIO3 9 95*4882a593Smuzhiyun #define R8A7794_CLK_GPIO2 10 96*4882a593Smuzhiyun #define R8A7794_CLK_GPIO1 11 97*4882a593Smuzhiyun #define R8A7794_CLK_GPIO0 12 98*4882a593Smuzhiyun #define R8A7794_CLK_RCAN1 15 99*4882a593Smuzhiyun #define R8A7794_CLK_RCAN0 16 100*4882a593Smuzhiyun #define R8A7794_CLK_QSPI_MOD 17 101*4882a593Smuzhiyun #define R8A7794_CLK_I2C5 25 102*4882a593Smuzhiyun #define R8A7794_CLK_I2C4 27 103*4882a593Smuzhiyun #define R8A7794_CLK_I2C3 28 104*4882a593Smuzhiyun #define R8A7794_CLK_I2C2 29 105*4882a593Smuzhiyun #define R8A7794_CLK_I2C1 30 106*4882a593Smuzhiyun #define R8A7794_CLK_I2C0 31 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* MSTP10 */ 109*4882a593Smuzhiyun #define R8A7794_CLK_SSI_ALL 5 110*4882a593Smuzhiyun #define R8A7794_CLK_SSI9 6 111*4882a593Smuzhiyun #define R8A7794_CLK_SSI8 7 112*4882a593Smuzhiyun #define R8A7794_CLK_SSI7 8 113*4882a593Smuzhiyun #define R8A7794_CLK_SSI6 9 114*4882a593Smuzhiyun #define R8A7794_CLK_SSI5 10 115*4882a593Smuzhiyun #define R8A7794_CLK_SSI4 11 116*4882a593Smuzhiyun #define R8A7794_CLK_SSI3 12 117*4882a593Smuzhiyun #define R8A7794_CLK_SSI2 13 118*4882a593Smuzhiyun #define R8A7794_CLK_SSI1 14 119*4882a593Smuzhiyun #define R8A7794_CLK_SSI0 15 120*4882a593Smuzhiyun #define R8A7794_CLK_SCU_ALL 17 121*4882a593Smuzhiyun #define R8A7794_CLK_SCU_DVC1 18 122*4882a593Smuzhiyun #define R8A7794_CLK_SCU_DVC0 19 123*4882a593Smuzhiyun #define R8A7794_CLK_SCU_CTU1_MIX1 20 124*4882a593Smuzhiyun #define R8A7794_CLK_SCU_CTU0_MIX0 21 125*4882a593Smuzhiyun #define R8A7794_CLK_SCU_SRC6 25 126*4882a593Smuzhiyun #define R8A7794_CLK_SCU_SRC5 26 127*4882a593Smuzhiyun #define R8A7794_CLK_SCU_SRC4 27 128*4882a593Smuzhiyun #define R8A7794_CLK_SCU_SRC3 28 129*4882a593Smuzhiyun #define R8A7794_CLK_SCU_SRC2 29 130*4882a593Smuzhiyun #define R8A7794_CLK_SCU_SRC1 30 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* MSTP11 */ 133*4882a593Smuzhiyun #define R8A7794_CLK_SCIFA3 6 134*4882a593Smuzhiyun #define R8A7794_CLK_SCIFA4 7 135*4882a593Smuzhiyun #define R8A7794_CLK_SCIFA5 8 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ 138