1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for MPC512x clock specs in DT bindings. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define MPC512x_CLK_DUMMY 0 10*4882a593Smuzhiyun #define MPC512x_CLK_REF 1 11*4882a593Smuzhiyun #define MPC512x_CLK_SYS 2 12*4882a593Smuzhiyun #define MPC512x_CLK_DIU 3 13*4882a593Smuzhiyun #define MPC512x_CLK_VIU 4 14*4882a593Smuzhiyun #define MPC512x_CLK_CSB 5 15*4882a593Smuzhiyun #define MPC512x_CLK_E300 6 16*4882a593Smuzhiyun #define MPC512x_CLK_IPS 7 17*4882a593Smuzhiyun #define MPC512x_CLK_FEC 8 18*4882a593Smuzhiyun #define MPC512x_CLK_SATA 9 19*4882a593Smuzhiyun #define MPC512x_CLK_PATA 10 20*4882a593Smuzhiyun #define MPC512x_CLK_NFC 11 21*4882a593Smuzhiyun #define MPC512x_CLK_LPC 12 22*4882a593Smuzhiyun #define MPC512x_CLK_MBX_BUS 13 23*4882a593Smuzhiyun #define MPC512x_CLK_MBX 14 24*4882a593Smuzhiyun #define MPC512x_CLK_MBX_3D 15 25*4882a593Smuzhiyun #define MPC512x_CLK_AXE 16 26*4882a593Smuzhiyun #define MPC512x_CLK_USB1 17 27*4882a593Smuzhiyun #define MPC512x_CLK_USB2 18 28*4882a593Smuzhiyun #define MPC512x_CLK_I2C 19 29*4882a593Smuzhiyun #define MPC512x_CLK_MSCAN0_MCLK 20 30*4882a593Smuzhiyun #define MPC512x_CLK_MSCAN1_MCLK 21 31*4882a593Smuzhiyun #define MPC512x_CLK_MSCAN2_MCLK 22 32*4882a593Smuzhiyun #define MPC512x_CLK_MSCAN3_MCLK 23 33*4882a593Smuzhiyun #define MPC512x_CLK_BDLC 24 34*4882a593Smuzhiyun #define MPC512x_CLK_SDHC 25 35*4882a593Smuzhiyun #define MPC512x_CLK_PCI 26 36*4882a593Smuzhiyun #define MPC512x_CLK_PSC_MCLK_IN 27 37*4882a593Smuzhiyun #define MPC512x_CLK_SPDIF_TX 28 38*4882a593Smuzhiyun #define MPC512x_CLK_SPDIF_RX 29 39*4882a593Smuzhiyun #define MPC512x_CLK_SPDIF_MCLK 30 40*4882a593Smuzhiyun #define MPC512x_CLK_SPDIF 31 41*4882a593Smuzhiyun #define MPC512x_CLK_AC97 32 42*4882a593Smuzhiyun #define MPC512x_CLK_PSC0_MCLK 33 43*4882a593Smuzhiyun #define MPC512x_CLK_PSC1_MCLK 34 44*4882a593Smuzhiyun #define MPC512x_CLK_PSC2_MCLK 35 45*4882a593Smuzhiyun #define MPC512x_CLK_PSC3_MCLK 36 46*4882a593Smuzhiyun #define MPC512x_CLK_PSC4_MCLK 37 47*4882a593Smuzhiyun #define MPC512x_CLK_PSC5_MCLK 38 48*4882a593Smuzhiyun #define MPC512x_CLK_PSC6_MCLK 39 49*4882a593Smuzhiyun #define MPC512x_CLK_PSC7_MCLK 40 50*4882a593Smuzhiyun #define MPC512x_CLK_PSC8_MCLK 41 51*4882a593Smuzhiyun #define MPC512x_CLK_PSC9_MCLK 42 52*4882a593Smuzhiyun #define MPC512x_CLK_PSC10_MCLK 43 53*4882a593Smuzhiyun #define MPC512x_CLK_PSC11_MCLK 44 54*4882a593Smuzhiyun #define MPC512x_CLK_PSC_FIFO 45 55*4882a593Smuzhiyun #define MPC512x_CLK_PSC0 46 56*4882a593Smuzhiyun #define MPC512x_CLK_PSC1 47 57*4882a593Smuzhiyun #define MPC512x_CLK_PSC2 48 58*4882a593Smuzhiyun #define MPC512x_CLK_PSC3 49 59*4882a593Smuzhiyun #define MPC512x_CLK_PSC4 50 60*4882a593Smuzhiyun #define MPC512x_CLK_PSC5 51 61*4882a593Smuzhiyun #define MPC512x_CLK_PSC6 52 62*4882a593Smuzhiyun #define MPC512x_CLK_PSC7 53 63*4882a593Smuzhiyun #define MPC512x_CLK_PSC8 54 64*4882a593Smuzhiyun #define MPC512x_CLK_PSC9 55 65*4882a593Smuzhiyun #define MPC512x_CLK_PSC10 56 66*4882a593Smuzhiyun #define MPC512x_CLK_PSC11 57 67*4882a593Smuzhiyun #define MPC512x_CLK_SDHC2 58 68*4882a593Smuzhiyun #define MPC512x_CLK_FEC2 59 69*4882a593Smuzhiyun #define MPC512x_CLK_OUT0_CLK 60 70*4882a593Smuzhiyun #define MPC512x_CLK_OUT1_CLK 61 71*4882a593Smuzhiyun #define MPC512x_CLK_OUT2_CLK 62 72*4882a593Smuzhiyun #define MPC512x_CLK_OUT3_CLK 63 73*4882a593Smuzhiyun #define MPC512x_CLK_CAN_CLK_IN 64 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define MPC512x_CLK_LAST_PUBLIC 64 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif 78