1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define JZ4725B_CLK_EXT 0 10*4882a593Smuzhiyun #define JZ4725B_CLK_OSC32K 1 11*4882a593Smuzhiyun #define JZ4725B_CLK_PLL 2 12*4882a593Smuzhiyun #define JZ4725B_CLK_PLL_HALF 3 13*4882a593Smuzhiyun #define JZ4725B_CLK_CCLK 4 14*4882a593Smuzhiyun #define JZ4725B_CLK_HCLK 5 15*4882a593Smuzhiyun #define JZ4725B_CLK_PCLK 6 16*4882a593Smuzhiyun #define JZ4725B_CLK_MCLK 7 17*4882a593Smuzhiyun #define JZ4725B_CLK_IPU 8 18*4882a593Smuzhiyun #define JZ4725B_CLK_LCD 9 19*4882a593Smuzhiyun #define JZ4725B_CLK_I2S 10 20*4882a593Smuzhiyun #define JZ4725B_CLK_SPI 11 21*4882a593Smuzhiyun #define JZ4725B_CLK_MMC_MUX 12 22*4882a593Smuzhiyun #define JZ4725B_CLK_UDC 13 23*4882a593Smuzhiyun #define JZ4725B_CLK_UART 14 24*4882a593Smuzhiyun #define JZ4725B_CLK_DMA 15 25*4882a593Smuzhiyun #define JZ4725B_CLK_ADC 16 26*4882a593Smuzhiyun #define JZ4725B_CLK_I2C 17 27*4882a593Smuzhiyun #define JZ4725B_CLK_AIC 18 28*4882a593Smuzhiyun #define JZ4725B_CLK_MMC0 19 29*4882a593Smuzhiyun #define JZ4725B_CLK_MMC1 20 30*4882a593Smuzhiyun #define JZ4725B_CLK_BCH 21 31*4882a593Smuzhiyun #define JZ4725B_CLK_TCU 22 32*4882a593Smuzhiyun #define JZ4725B_CLK_EXT512 23 33*4882a593Smuzhiyun #define JZ4725B_CLK_RTC 24 34*4882a593Smuzhiyun #define JZ4725B_CLK_UDC_PHY 25 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ 37