1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ARTPEC-6 clock controller indexes 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2016 Axis Comunications AB. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H 9*4882a593Smuzhiyun #define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ARTPEC6_CLK_CPU 0 12*4882a593Smuzhiyun #define ARTPEC6_CLK_CPU_PERIPH 1 13*4882a593Smuzhiyun #define ARTPEC6_CLK_NAND_CLKA 2 14*4882a593Smuzhiyun #define ARTPEC6_CLK_NAND_CLKB 3 15*4882a593Smuzhiyun #define ARTPEC6_CLK_ETH_ACLK 4 16*4882a593Smuzhiyun #define ARTPEC6_CLK_DMA_ACLK 5 17*4882a593Smuzhiyun #define ARTPEC6_CLK_PTP_REF 6 18*4882a593Smuzhiyun #define ARTPEC6_CLK_SD_PCLK 7 19*4882a593Smuzhiyun #define ARTPEC6_CLK_SD_IMCLK 8 20*4882a593Smuzhiyun #define ARTPEC6_CLK_I2S_HST 9 21*4882a593Smuzhiyun #define ARTPEC6_CLK_I2S0_CLK 10 22*4882a593Smuzhiyun #define ARTPEC6_CLK_I2S1_CLK 11 23*4882a593Smuzhiyun #define ARTPEC6_CLK_UART_PCLK 12 24*4882a593Smuzhiyun #define ARTPEC6_CLK_UART_REFCLK 13 25*4882a593Smuzhiyun #define ARTPEC6_CLK_I2C 14 26*4882a593Smuzhiyun #define ARTPEC6_CLK_SPI_PCLK 15 27*4882a593Smuzhiyun #define ARTPEC6_CLK_SPI_SSPCLK 16 28*4882a593Smuzhiyun #define ARTPEC6_CLK_SYS_TIMER 17 29*4882a593Smuzhiyun #define ARTPEC6_CLK_FRACDIV_IN 18 30*4882a593Smuzhiyun #define ARTPEC6_CLK_DBG_PCLK 19 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* This must be the highest clock index plus one. */ 33*4882a593Smuzhiyun #define ARTPEC6_CLK_NUMCLOCKS 20 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36