1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun #address-cells = <1>; 5*4882a593Smuzhiyun #size-cells = <1>; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun cpus { 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <0>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun cpu@0 { 12*4882a593Smuzhiyun device_type = "cpu"; 13*4882a593Smuzhiyun reg = <0>; 14*4882a593Smuzhiyun model = "ti,c64x+"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun cpu@1 { 17*4882a593Smuzhiyun device_type = "cpu"; 18*4882a593Smuzhiyun reg = <1>; 19*4882a593Smuzhiyun model = "ti,c64x+"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun cpu@2 { 22*4882a593Smuzhiyun device_type = "cpu"; 23*4882a593Smuzhiyun reg = <2>; 24*4882a593Smuzhiyun model = "ti,c64x+"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun soc { 29*4882a593Smuzhiyun compatible = "simple-bus"; 30*4882a593Smuzhiyun model = "tms320c6474"; 31*4882a593Smuzhiyun #address-cells = <1>; 32*4882a593Smuzhiyun #size-cells = <1>; 33*4882a593Smuzhiyun ranges; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun core_pic: interrupt-controller { 36*4882a593Smuzhiyun interrupt-controller; 37*4882a593Smuzhiyun #interrupt-cells = <1>; 38*4882a593Smuzhiyun compatible = "ti,c64x+core-pic"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun megamod_pic: interrupt-controller@1800000 { 42*4882a593Smuzhiyun compatible = "ti,c64x+megamod-pic"; 43*4882a593Smuzhiyun interrupt-controller; 44*4882a593Smuzhiyun #interrupt-cells = <1>; 45*4882a593Smuzhiyun reg = <0x1800000 0x1000>; 46*4882a593Smuzhiyun interrupt-parent = <&core_pic>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun cache-controller@1840000 { 50*4882a593Smuzhiyun compatible = "ti,c64x+cache"; 51*4882a593Smuzhiyun reg = <0x01840000 0x8400>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun timer3: timer@2940000 { 55*4882a593Smuzhiyun compatible = "ti,c64x+timer64"; 56*4882a593Smuzhiyun ti,core-mask = < 0x04 >; 57*4882a593Smuzhiyun reg = <0x2940000 0x40>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun timer4: timer@2950000 { 61*4882a593Smuzhiyun compatible = "ti,c64x+timer64"; 62*4882a593Smuzhiyun ti,core-mask = < 0x02 >; 63*4882a593Smuzhiyun reg = <0x2950000 0x40>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun timer5: timer@2960000 { 67*4882a593Smuzhiyun compatible = "ti,c64x+timer64"; 68*4882a593Smuzhiyun ti,core-mask = < 0x01 >; 69*4882a593Smuzhiyun reg = <0x2960000 0x40>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun device-state-controller@2880800 { 73*4882a593Smuzhiyun compatible = "ti,c64x+dscr"; 74*4882a593Smuzhiyun reg = <0x02880800 0x400>; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun ti,dscr-devstat = <0x004>; 77*4882a593Smuzhiyun ti,dscr-silicon-rev = <0x014 28 0xf>; 78*4882a593Smuzhiyun ti,dscr-mac-fuse-regs = <0x34 3 4 5 6 79*4882a593Smuzhiyun 0x38 0 0 1 2>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun clock-controller@29a0000 { 83*4882a593Smuzhiyun compatible = "ti,c6474-pll", "ti,c64x+pll"; 84*4882a593Smuzhiyun reg = <0x029a0000 0x200>; 85*4882a593Smuzhiyun ti,c64x+pll-bypass-delay = <120>; 86*4882a593Smuzhiyun ti,c64x+pll-reset-delay = <30000>; 87*4882a593Smuzhiyun ti,c64x+pll-lock-delay = <60000>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun}; 91