1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "k3-j7200.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun memory@80000000 { 12*4882a593Smuzhiyun device_type = "memory"; 13*4882a593Smuzhiyun /* 4G RAM */ 14*4882a593Smuzhiyun reg = <0x00 0x80000000 0x00 0x80000000>, 15*4882a593Smuzhiyun <0x08 0x80000000 0x00 0x80000000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reserved_memory: reserved-memory { 19*4882a593Smuzhiyun #address-cells = <2>; 20*4882a593Smuzhiyun #size-cells = <2>; 21*4882a593Smuzhiyun ranges; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun secure_ddr: optee@9e800000 { 24*4882a593Smuzhiyun reg = <0x00 0x9e800000 0x00 0x01800000>; 25*4882a593Smuzhiyun alignment = <0x1000>; 26*4882a593Smuzhiyun no-map; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&wkup_pmx0 { 32*4882a593Smuzhiyun mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { 33*4882a593Smuzhiyun pinctrl-single,pins = < 34*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 35*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 36*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 37*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 38*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 39*4882a593Smuzhiyun J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 40*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 41*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 42*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 43*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 44*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 45*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 46*4882a593Smuzhiyun J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 47*4882a593Smuzhiyun >; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&hbmc { 52*4882a593Smuzhiyun /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 53*4882a593Smuzhiyun * appropriate node based on board detection 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun status = "disabled"; 56*4882a593Smuzhiyun pinctrl-names = "default"; 57*4882a593Smuzhiyun pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 58*4882a593Smuzhiyun ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 59*4882a593Smuzhiyun <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun flash@0,0 { 62*4882a593Smuzhiyun compatible = "cypress,hyperflash", "cfi-flash"; 63*4882a593Smuzhiyun reg = <0x00 0x00 0x4000000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun}; 66