1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Spreadtrum Sharkl64 platform DTS file 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014, Spreadtrum Communications Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under a dual GPLv2 or X11 license. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun interrupt-parent = <&gic>; 11*4882a593Smuzhiyun #address-cells = <2>; 12*4882a593Smuzhiyun #size-cells = <2>; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun soc { 15*4882a593Smuzhiyun compatible = "simple-bus"; 16*4882a593Smuzhiyun #address-cells = <2>; 17*4882a593Smuzhiyun #size-cells = <2>; 18*4882a593Smuzhiyun ranges; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun ap-apb { 21*4882a593Smuzhiyun compatible = "simple-bus"; 22*4882a593Smuzhiyun #address-cells = <2>; 23*4882a593Smuzhiyun #size-cells = <2>; 24*4882a593Smuzhiyun ranges; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun uart0: serial@70000000 { 27*4882a593Smuzhiyun compatible = "sprd,sc9836-uart"; 28*4882a593Smuzhiyun reg = <0 0x70000000 0 0x100>; 29*4882a593Smuzhiyun interrupts = <0 2 0xf04>; 30*4882a593Smuzhiyun clocks = <&clk26mhz>; 31*4882a593Smuzhiyun status = "disabled"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun uart1: serial@70100000 { 35*4882a593Smuzhiyun compatible = "sprd,sc9836-uart"; 36*4882a593Smuzhiyun reg = <0 0x70100000 0 0x100>; 37*4882a593Smuzhiyun interrupts = <0 3 0xf04>; 38*4882a593Smuzhiyun clocks = <&clk26mhz>; 39*4882a593Smuzhiyun status = "disabled"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun uart2: serial@70200000 { 43*4882a593Smuzhiyun compatible = "sprd,sc9836-uart"; 44*4882a593Smuzhiyun reg = <0 0x70200000 0 0x100>; 45*4882a593Smuzhiyun interrupts = <0 4 0xf04>; 46*4882a593Smuzhiyun clocks = <&clk26mhz>; 47*4882a593Smuzhiyun status = "disabled"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun uart3: serial@70300000 { 51*4882a593Smuzhiyun compatible = "sprd,sc9836-uart"; 52*4882a593Smuzhiyun reg = <0 0x70300000 0 0x100>; 53*4882a593Smuzhiyun interrupts = <0 5 0xf04>; 54*4882a593Smuzhiyun clocks = <&clk26mhz>; 55*4882a593Smuzhiyun status = "disabled"; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun clk26mhz: clk26mhz { 61*4882a593Smuzhiyun compatible = "fixed-clock"; 62*4882a593Smuzhiyun #clock-cells = <0>; 63*4882a593Smuzhiyun clock-frequency = <26000000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun}; 66