xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20-ref.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ OR MIT
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Device Tree Source for UniPhier LD20 Reference Board
4*4882a593Smuzhiyun//
5*4882a593Smuzhiyun// Copyright (C) 2015-2016 Socionext Inc.
6*4882a593Smuzhiyun//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/dts-v1/;
9*4882a593Smuzhiyun#include "uniphier-ld20.dtsi"
10*4882a593Smuzhiyun#include "uniphier-ref-daughter.dtsi"
11*4882a593Smuzhiyun#include "uniphier-support-card.dtsi"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	model = "UniPhier LD20 Reference Board";
15*4882a593Smuzhiyun	compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	chosen {
18*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	aliases {
22*4882a593Smuzhiyun		serial0 = &serial0;
23*4882a593Smuzhiyun		serial1 = &serialsc;
24*4882a593Smuzhiyun		serial2 = &serial2;
25*4882a593Smuzhiyun		serial3 = &serial3;
26*4882a593Smuzhiyun		i2c0 = &i2c0;
27*4882a593Smuzhiyun		i2c1 = &i2c1;
28*4882a593Smuzhiyun		i2c2 = &i2c2;
29*4882a593Smuzhiyun		i2c3 = &i2c3;
30*4882a593Smuzhiyun		i2c4 = &i2c4;
31*4882a593Smuzhiyun		i2c5 = &i2c5;
32*4882a593Smuzhiyun		ethernet0 = &eth;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	memory@80000000 {
36*4882a593Smuzhiyun		device_type = "memory";
37*4882a593Smuzhiyun		reg = <0 0x80000000 0 0xc0000000>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun&ethsc {
42*4882a593Smuzhiyun	interrupts = <0 8>;
43*4882a593Smuzhiyun};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun&serialsc {
46*4882a593Smuzhiyun	interrupts = <0 8>;
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun&serial0 {
50*4882a593Smuzhiyun	status = "okay";
51*4882a593Smuzhiyun};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun&gpio {
54*4882a593Smuzhiyun	xirq0 {
55*4882a593Smuzhiyun		gpio-hog;
56*4882a593Smuzhiyun		gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
57*4882a593Smuzhiyun		input;
58*4882a593Smuzhiyun	};
59*4882a593Smuzhiyun};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun&i2c0 {
62*4882a593Smuzhiyun	status = "okay";
63*4882a593Smuzhiyun};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun&eth {
66*4882a593Smuzhiyun	status = "okay";
67*4882a593Smuzhiyun	phy-handle = <&ethphy>;
68*4882a593Smuzhiyun};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun&mdio {
71*4882a593Smuzhiyun	ethphy: ethernet-phy@0 {
72*4882a593Smuzhiyun		reg = <0>;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun&pinctrl_ether_rgmii {
77*4882a593Smuzhiyun	tx {
78*4882a593Smuzhiyun		pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
79*4882a593Smuzhiyun		       "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
80*4882a593Smuzhiyun		drive-strength = <9>;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun&usb {
85*4882a593Smuzhiyun	status = "okay";
86*4882a593Smuzhiyun};
87