xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3588s-tablet-single.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/usb/pd.h>
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
11*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
12*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
13*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h>
14*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
15*4882a593Smuzhiyun#include "rk3588s.dtsi"
16*4882a593Smuzhiyun#include "rk3588-android.dtsi"
17*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun/ {
20*4882a593Smuzhiyun	adc_keys: adc-keys {
21*4882a593Smuzhiyun		compatible = "adc-keys";
22*4882a593Smuzhiyun		io-channels = <&saradc 1>;
23*4882a593Smuzhiyun		io-channel-names = "buttons";
24*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
25*4882a593Smuzhiyun		poll-interval = <100>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		vol-up-key {
28*4882a593Smuzhiyun			label = "volume up";
29*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
30*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		vol-down-key {
34*4882a593Smuzhiyun			label = "volume down";
35*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
36*4882a593Smuzhiyun			press-threshold-microvolt = <417000>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	backlight: backlight {
41*4882a593Smuzhiyun		compatible = "pwm-backlight";
42*4882a593Smuzhiyun		pwms = <&pwm14 0 25000 0>;
43*4882a593Smuzhiyun		brightness-levels = <
44*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
45*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
46*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
47*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
48*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
49*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
50*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
51*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
52*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
53*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
54*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
55*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
56*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
57*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
58*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
59*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
60*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
61*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
62*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
63*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
64*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
65*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
66*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
67*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
68*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
69*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
70*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
71*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
72*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
73*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
74*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
75*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
76*4882a593Smuzhiyun		>;
77*4882a593Smuzhiyun		default-brightness-level = <200>;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	charge-animation {
81*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
82*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
83*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
84*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <6800>;
85*4882a593Smuzhiyun		rockchip,screen-on-voltage = <6900>;
86*4882a593Smuzhiyun		rockchip,uboot-exit-charge-level = <2>;
87*4882a593Smuzhiyun		rockchip,uboot-exit-charge-auto = <0>;
88*4882a593Smuzhiyun		rockchip,system-suspend = <1>;
89*4882a593Smuzhiyun		regulator-on-in-mem = <&vdd_log_s0>, <&vcc_2v0_pldo_s3>,
90*4882a593Smuzhiyun			<&vdd2_ddr_s3>, <&vcc_1v8_s3>, <&avcc_1v8_s0>,
91*4882a593Smuzhiyun			<&vcc_1v8_s0>, <&vdd_0v75_s3>, <&pldo6_s3>,
92*4882a593Smuzhiyun			<&vcc_3v3_s3>;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun		regulator-off-in-mem = <&vdd_gpu_s0>, <&vdd_npu_s0>,
95*4882a593Smuzhiyun			<&vdd_vdenc_s0>, <&vdd_gpu_mem_s0>, <&vdd_npu_mem_s0>,
96*4882a593Smuzhiyun			<&vdd_vdenc_mem_s0>, <&vcc_3v3_s0>,
97*4882a593Smuzhiyun			<&vccio_sd_s0>, <&avdd_0v75_s0>, <&vdd_0v85_s0>,
98*4882a593Smuzhiyun			<&vdd_cpu_big1_s0>, <&vdd_cpu_big0_s0>, <&vdd_cpu_lit_s0>,
99*4882a593Smuzhiyun			<&vdd_cpu_big1_mem_s0>, <&vdd_cpu_big0_mem_s0>, <&vdd_cpu_lit_mem_s0>,
100*4882a593Smuzhiyun			<&vddq_ddr_s0>, <&vdd_ddr_s0>, <&vdd_ddr_pll_s0>,
101*4882a593Smuzhiyun			<&avdd_1v2_s0>, <&vdd_0v75_s0>;
102*4882a593Smuzhiyun		status = "okay";
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	es7202_sound_micarray: es7202-sound-micarray {
106*4882a593Smuzhiyun		status = "okay";
107*4882a593Smuzhiyun		compatible = "simple-audio-card";
108*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
109*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,sound-micarray";
110*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
111*4882a593Smuzhiyun		simple-audio-card,dai-link@0 {
112*4882a593Smuzhiyun			format = "pdm";
113*4882a593Smuzhiyun			cpu {
114*4882a593Smuzhiyun				sound-dai = <&pdm0>;
115*4882a593Smuzhiyun			};
116*4882a593Smuzhiyun			codec {
117*4882a593Smuzhiyun				sound-dai = <&es7202>;
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun	};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun	es8388_sound: es8388-sound {
123*4882a593Smuzhiyun		status = "okay";
124*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
125*4882a593Smuzhiyun		rockchip,card-name = "rockchip,es8388-codec";
126*4882a593Smuzhiyun		hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
127*4882a593Smuzhiyun		io-channels = <&saradc 3>;
128*4882a593Smuzhiyun		io-channel-names = "adc-detect";
129*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
130*4882a593Smuzhiyun		poll-interval = <100>;
131*4882a593Smuzhiyun		spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
132*4882a593Smuzhiyun		hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
133*4882a593Smuzhiyun		rockchip,format = "i2s";
134*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
135*4882a593Smuzhiyun		rockchip,cpu = <&i2s0_8ch>;
136*4882a593Smuzhiyun		rockchip,codec = <&es8388>;
137*4882a593Smuzhiyun		rockchip,audio-routing =
138*4882a593Smuzhiyun			"Headphone", "LOUT1",
139*4882a593Smuzhiyun			"Headphone", "ROUT1",
140*4882a593Smuzhiyun			"Speaker", "LOUT2",
141*4882a593Smuzhiyun			"Speaker", "ROUT2",
142*4882a593Smuzhiyun			"Headphone", "Headphone Power",
143*4882a593Smuzhiyun			"Headphone", "Headphone Power",
144*4882a593Smuzhiyun			"Speaker", "Speaker Power",
145*4882a593Smuzhiyun			"Speaker", "Speaker Power",
146*4882a593Smuzhiyun			"LINPUT1", "Main Mic",
147*4882a593Smuzhiyun			"LINPUT2", "Main Mic",
148*4882a593Smuzhiyun			"RINPUT1", "Headset Mic",
149*4882a593Smuzhiyun			"RINPUT2", "Headset Mic";
150*4882a593Smuzhiyun		pinctrl-names = "default";
151*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
152*4882a593Smuzhiyun		play-pause-key {
153*4882a593Smuzhiyun			label = "playpause";
154*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
155*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
156*4882a593Smuzhiyun		};
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun	hall_sensor: hall-mh248 {
160*4882a593Smuzhiyun		compatible = "hall-mh248";
161*4882a593Smuzhiyun		pinctrl-names = "default";
162*4882a593Smuzhiyun		pinctrl-0 = <&mh248_irq_gpio>;
163*4882a593Smuzhiyun		irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_EDGE_BOTH>;
164*4882a593Smuzhiyun		hall-active = <1>;
165*4882a593Smuzhiyun		status = "okay";
166*4882a593Smuzhiyun	};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun	panel-edp {
169*4882a593Smuzhiyun		compatible = "innolux,p120zdg-bf4", "simple-panel";
170*4882a593Smuzhiyun		backlight = <&backlight>;
171*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_edp>;
172*4882a593Smuzhiyun		prepare-delay-ms = <120>;
173*4882a593Smuzhiyun		enable-delay-ms = <120>;
174*4882a593Smuzhiyun		unprepare-delay-ms = <500>;
175*4882a593Smuzhiyun		disable-delay-ms = <120>;
176*4882a593Smuzhiyun		width-mm = <254>;
177*4882a593Smuzhiyun		height-mm = <169>;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun		panel-timing {
180*4882a593Smuzhiyun			clock-frequency = <206000000>;
181*4882a593Smuzhiyun			hactive = <2160>;
182*4882a593Smuzhiyun			vactive = <1440>;
183*4882a593Smuzhiyun			hfront-porch = <48>;
184*4882a593Smuzhiyun			hsync-len = <32>;
185*4882a593Smuzhiyun			hback-porch = <80>;
186*4882a593Smuzhiyun			vfront-porch = <3>;
187*4882a593Smuzhiyun			vsync-len = <10>;
188*4882a593Smuzhiyun			vback-porch = <27>;
189*4882a593Smuzhiyun			hsync-active = <0>;
190*4882a593Smuzhiyun			vsync-active = <0>;
191*4882a593Smuzhiyun			de-active = <0>;
192*4882a593Smuzhiyun			pixelclk-active = <0>;
193*4882a593Smuzhiyun		};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		port {
196*4882a593Smuzhiyun			panel_in_edp: endpoint {
197*4882a593Smuzhiyun				remote-endpoint = <&edp_out_panel>;
198*4882a593Smuzhiyun			};
199*4882a593Smuzhiyun		};
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
203*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
204*4882a593Smuzhiyun		clocks = <&hym8563>;
205*4882a593Smuzhiyun		clock-names = "ext_clock";
206*4882a593Smuzhiyun		pinctrl-names = "default";
207*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
208*4882a593Smuzhiyun		/*
209*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
210*4882a593Smuzhiyun		 * on the actual card populated):
211*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
212*4882a593Smuzhiyun		 * - PDN (power down when low)
213*4882a593Smuzhiyun		 */
214*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
215*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
216*4882a593Smuzhiyun	};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
219*4882a593Smuzhiyun		compatible = "regulator-fixed";
220*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
221*4882a593Smuzhiyun		regulator-always-on;
222*4882a593Smuzhiyun		regulator-boot-on;
223*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
224*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
225*4882a593Smuzhiyun	};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun	vcc5v0_usb: vcc5v0-usb {
228*4882a593Smuzhiyun		compatible = "regulator-fixed";
229*4882a593Smuzhiyun		regulator-name = "vcc5v0_usb";
230*4882a593Smuzhiyun		regulator-always-on;
231*4882a593Smuzhiyun		regulator-boot-on;
232*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
233*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
234*4882a593Smuzhiyun		enable-active-high;
235*4882a593Smuzhiyun		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
236*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
237*4882a593Smuzhiyun		pinctrl-names = "default";
238*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_usb_en>;
239*4882a593Smuzhiyun	};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
242*4882a593Smuzhiyun		compatible = "regulator-fixed";
243*4882a593Smuzhiyun		regulator-name = "vcc_1v1_nldo_s3";
244*4882a593Smuzhiyun		regulator-always-on;
245*4882a593Smuzhiyun		regulator-boot-on;
246*4882a593Smuzhiyun		regulator-min-microvolt = <1100000>;
247*4882a593Smuzhiyun		regulator-max-microvolt = <1100000>;
248*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
249*4882a593Smuzhiyun	};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun	vcc3v3_lcd_edp: vcc3v3-lcd-edp {
252*4882a593Smuzhiyun		compatible = "regulator-fixed";
253*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd_edp";
254*4882a593Smuzhiyun		regulator-boot-on;
255*4882a593Smuzhiyun		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
256*4882a593Smuzhiyun		enable-active-high;
257*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s3>;
258*4882a593Smuzhiyun	};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun	vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
261*4882a593Smuzhiyun		compatible = "regulator-fixed";
262*4882a593Smuzhiyun		enable-active-high;
263*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
264*4882a593Smuzhiyun		pinctrl-names = "default";
265*4882a593Smuzhiyun		pinctrl-0 = <&sd_s0_pwr>;
266*4882a593Smuzhiyun		regulator-always-on;
267*4882a593Smuzhiyun		regulator-max-microvolt = <3000000>;
268*4882a593Smuzhiyun		regulator-min-microvolt = <3000000>;
269*4882a593Smuzhiyun		regulator-name = "vcc_3v3_sd_s0";
270*4882a593Smuzhiyun		vin-supply = <&vcc_3v3_s3>;
271*4882a593Smuzhiyun	};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host {
274*4882a593Smuzhiyun		compatible = "regulator-fixed";
275*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
276*4882a593Smuzhiyun		regulator-boot-on;
277*4882a593Smuzhiyun		regulator-always-on;
278*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
279*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
280*4882a593Smuzhiyun		enable-active-high;
281*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
282*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
283*4882a593Smuzhiyun		pinctrl-names = "default";
284*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
285*4882a593Smuzhiyun	};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun	vcc_mipidcphy: vcc-mipidcphy-regulator {
288*4882a593Smuzhiyun		compatible = "regulator-fixed";
289*4882a593Smuzhiyun		gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
290*4882a593Smuzhiyun		pinctrl-names = "default";
291*4882a593Smuzhiyun		pinctrl-0 = <&mipidcphy_pwr>;
292*4882a593Smuzhiyun		regulator-name = "vcc_mipidcphy";
293*4882a593Smuzhiyun		enable-active-high;
294*4882a593Smuzhiyun		regulator-boot-on;
295*4882a593Smuzhiyun	};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
298*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
299*4882a593Smuzhiyun		clocks = <&hym8563>;
300*4882a593Smuzhiyun		clock-names = "ext_clock";
301*4882a593Smuzhiyun		uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
302*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
303*4882a593Smuzhiyun		pinctrl-0 = <&uart7m1_rtsn>,  <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
304*4882a593Smuzhiyun		pinctrl-1 = <&uart7_gpios>;
305*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
306*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
307*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
308*4882a593Smuzhiyun		status = "okay";
309*4882a593Smuzhiyun	};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
312*4882a593Smuzhiyun		compatible = "wlan-platdata";
313*4882a593Smuzhiyun		wifi_chip_type = "ap6398s";
314*4882a593Smuzhiyun		pinctrl-names = "default";
315*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>;
316*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
317*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
318*4882a593Smuzhiyun		status = "okay";
319*4882a593Smuzhiyun	};
320*4882a593Smuzhiyun};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun&av1d_mmu {
323*4882a593Smuzhiyun	status = "okay";
324*4882a593Smuzhiyun};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun&combphy0_ps {
327*4882a593Smuzhiyun	status = "okay";
328*4882a593Smuzhiyun};
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun&cpu_l0 {
331*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_lit_s0>;
332*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_lit_mem_s0>;
333*4882a593Smuzhiyun};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun&cpu_b0 {
336*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_big0_s0>;
337*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_big0_mem_s0>;
338*4882a593Smuzhiyun};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun&cpu_b2 {
341*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_big1_s0>;
342*4882a593Smuzhiyun	mem-supply = <&vdd_cpu_big1_mem_s0>;
343*4882a593Smuzhiyun};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun&csi2_dcphy0 {
346*4882a593Smuzhiyun	status = "okay";
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun	ports {
349*4882a593Smuzhiyun		#address-cells = <1>;
350*4882a593Smuzhiyun		#size-cells = <0>;
351*4882a593Smuzhiyun		port@0 {
352*4882a593Smuzhiyun			reg = <0>;
353*4882a593Smuzhiyun			#address-cells = <1>;
354*4882a593Smuzhiyun			#size-cells = <0>;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun			mipi_in_ov50c40: endpoint@1 {
357*4882a593Smuzhiyun				reg = <1>;
358*4882a593Smuzhiyun				remote-endpoint = <&ov50c40_out>;
359*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
360*4882a593Smuzhiyun			};
361*4882a593Smuzhiyun		};
362*4882a593Smuzhiyun		port@1 {
363*4882a593Smuzhiyun			reg = <1>;
364*4882a593Smuzhiyun			#address-cells = <1>;
365*4882a593Smuzhiyun			#size-cells = <0>;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun			csidcphy0_out: endpoint@0 {
368*4882a593Smuzhiyun				reg = <0>;
369*4882a593Smuzhiyun				remote-endpoint = <&mipi0_csi2_input>;
370*4882a593Smuzhiyun			};
371*4882a593Smuzhiyun		};
372*4882a593Smuzhiyun	};
373*4882a593Smuzhiyun};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun&csi2_dcphy1 {
376*4882a593Smuzhiyun	status = "okay";
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun	ports {
379*4882a593Smuzhiyun		#address-cells = <1>;
380*4882a593Smuzhiyun		#size-cells = <0>;
381*4882a593Smuzhiyun		port@0 {
382*4882a593Smuzhiyun			reg = <0>;
383*4882a593Smuzhiyun			#address-cells = <1>;
384*4882a593Smuzhiyun			#size-cells = <0>;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
387*4882a593Smuzhiyun				reg = <1>;
388*4882a593Smuzhiyun				remote-endpoint = <&ov13855_out>;
389*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
390*4882a593Smuzhiyun			};
391*4882a593Smuzhiyun		};
392*4882a593Smuzhiyun		port@1 {
393*4882a593Smuzhiyun			reg = <1>;
394*4882a593Smuzhiyun			#address-cells = <1>;
395*4882a593Smuzhiyun			#size-cells = <0>;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun			csidcphy1_out: endpoint@0 {
398*4882a593Smuzhiyun				reg = <0>;
399*4882a593Smuzhiyun				remote-endpoint = <&mipi1_csi2_input>;
400*4882a593Smuzhiyun			};
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun	};
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&dp0 {
406*4882a593Smuzhiyun	status = "okay";
407*4882a593Smuzhiyun};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun&dp0_in_vp1 {
410*4882a593Smuzhiyun	status = "okay";
411*4882a593Smuzhiyun};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun&edp0 {
414*4882a593Smuzhiyun	support-psr;
415*4882a593Smuzhiyun	force-hpd;
416*4882a593Smuzhiyun	status = "okay";
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun	ports {
419*4882a593Smuzhiyun		port@1 {
420*4882a593Smuzhiyun			reg = <1>;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun			edp_out_panel: endpoint {
423*4882a593Smuzhiyun				remote-endpoint = <&panel_in_edp>;
424*4882a593Smuzhiyun			};
425*4882a593Smuzhiyun		};
426*4882a593Smuzhiyun	};
427*4882a593Smuzhiyun};
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun&edp0_in_vp2 {
430*4882a593Smuzhiyun	status = "okay";
431*4882a593Smuzhiyun};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun&gpu {
434*4882a593Smuzhiyun	mali-supply = <&vdd_gpu_s0>;
435*4882a593Smuzhiyun	mem-supply = <&vdd_gpu_mem_s0>;
436*4882a593Smuzhiyun	upthreshold = <60>;
437*4882a593Smuzhiyun	downdifferential = <30>;
438*4882a593Smuzhiyun	status = "okay";
439*4882a593Smuzhiyun};
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun&hdptxphy0 {
442*4882a593Smuzhiyun	/* Single Vdiff Training Table for power reduction (optional) */
443*4882a593Smuzhiyun	training-table = /bits/ 8 <
444*4882a593Smuzhiyun		/* voltage swing 0, pre-emphasis 0->3 */
445*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
446*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
447*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
448*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
449*4882a593Smuzhiyun		/* voltage swing 1, pre-emphasis 0->2 */
450*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
451*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
452*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
453*4882a593Smuzhiyun		/* voltage swing 2, pre-emphasis 0->1 */
454*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
455*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
456*4882a593Smuzhiyun		/* voltage swing 3, pre-emphasis 0 */
457*4882a593Smuzhiyun		0x0d 0x00 0x00 0x00 0x00 0x00
458*4882a593Smuzhiyun	>;
459*4882a593Smuzhiyun	status = "okay";
460*4882a593Smuzhiyun};
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun&i2c0 {
463*4882a593Smuzhiyun	status = "okay";
464*4882a593Smuzhiyun	pinctrl-names = "default";
465*4882a593Smuzhiyun	pinctrl-0 = <&i2c0m2_xfer>;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun	vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
468*4882a593Smuzhiyun		compatible = "rockchip,rk8602";
469*4882a593Smuzhiyun		reg = <0x42>;
470*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
471*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
472*4882a593Smuzhiyun		regulator-name = "vdd_cpu_big0_s0";
473*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
474*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
475*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
476*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
477*4882a593Smuzhiyun		regulator-boot-on;
478*4882a593Smuzhiyun		regulator-always-on;
479*4882a593Smuzhiyun		regulator-state-mem {
480*4882a593Smuzhiyun			regulator-off-in-suspend;
481*4882a593Smuzhiyun		};
482*4882a593Smuzhiyun	};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun	vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
485*4882a593Smuzhiyun		compatible = "rockchip,rk8603";
486*4882a593Smuzhiyun		reg = <0x43>;
487*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
488*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
489*4882a593Smuzhiyun		regulator-name = "vdd_cpu_big1_s0";
490*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
491*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
492*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
493*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
494*4882a593Smuzhiyun		regulator-boot-on;
495*4882a593Smuzhiyun		regulator-always-on;
496*4882a593Smuzhiyun		regulator-state-mem {
497*4882a593Smuzhiyun			regulator-off-in-suspend;
498*4882a593Smuzhiyun		};
499*4882a593Smuzhiyun	};
500*4882a593Smuzhiyun};
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun&i2c2 {
503*4882a593Smuzhiyun	status = "okay";
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun	vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
506*4882a593Smuzhiyun		compatible = "rockchip,rk8602";
507*4882a593Smuzhiyun		reg = <0x42>;
508*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
509*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
510*4882a593Smuzhiyun		regulator-name = "vdd_npu_s0";
511*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
512*4882a593Smuzhiyun		regulator-max-microvolt = <950000>;
513*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
514*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
515*4882a593Smuzhiyun		regulator-boot-on;
516*4882a593Smuzhiyun		regulator-always-on;
517*4882a593Smuzhiyun		regulator-state-mem {
518*4882a593Smuzhiyun			regulator-off-in-suspend;
519*4882a593Smuzhiyun		};
520*4882a593Smuzhiyun	};
521*4882a593Smuzhiyun};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun&i2c3 {
524*4882a593Smuzhiyun	status = "okay";
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun	es8388: es8388@11 {
527*4882a593Smuzhiyun		status = "okay";
528*4882a593Smuzhiyun		#sound-dai-cells = <0>;
529*4882a593Smuzhiyun		compatible = "everest,es8388", "everest,es8323";
530*4882a593Smuzhiyun		reg = <0x11>;
531*4882a593Smuzhiyun		clocks = <&mclkout_i2s0>;
532*4882a593Smuzhiyun		clock-names = "mclk";
533*4882a593Smuzhiyun		assigned-clocks = <&mclkout_i2s0>;
534*4882a593Smuzhiyun		assigned-clock-rates = <12288000>;
535*4882a593Smuzhiyun		pinctrl-names = "default";
536*4882a593Smuzhiyun		pinctrl-0 = <&i2s0_mclk>;
537*4882a593Smuzhiyun	};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun	es7202: es7202@32 {
540*4882a593Smuzhiyun		status = "okay";
541*4882a593Smuzhiyun		#sound-dai-cells = <0>;
542*4882a593Smuzhiyun		compatible = "ES7202_PDM_ADC_1";
543*4882a593Smuzhiyun		power-supply = <&avcc_1v8_s0>;	/* only 1v8 or 3v3, default is 3v3 */
544*4882a593Smuzhiyun		reg = <0x32>;
545*4882a593Smuzhiyun	};
546*4882a593Smuzhiyun};
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun&i2c4 {
549*4882a593Smuzhiyun	status = "okay";
550*4882a593Smuzhiyun	pinctrl-names = "default";
551*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m3_xfer>;
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun	elan_touch: elan_ktf@10 {
554*4882a593Smuzhiyun		status = "okay";
555*4882a593Smuzhiyun		compatible = "elan,ektf";
556*4882a593Smuzhiyun		reg = <0x10>;
557*4882a593Smuzhiyun		pinctrl-names = "default";
558*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
559*4882a593Smuzhiyun		elan,rst-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
560*4882a593Smuzhiyun		elan,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
561*4882a593Smuzhiyun		chip_type = <0x01>;	/* 1:HID IIC, 0: NORMAL IIC */
562*4882a593Smuzhiyun		report_type = <0x01>;	/* 1:B protocol, 0:A protocol */
563*4882a593Smuzhiyun	};
564*4882a593Smuzhiyun};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun&i2c5 {
567*4882a593Smuzhiyun	status = "okay";
568*4882a593Smuzhiyun	pinctrl-names = "default";
569*4882a593Smuzhiyun	pinctrl-0 = <&i2c5m2_xfer>;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun	mpu6500_acc: mpu_acc@68 {
572*4882a593Smuzhiyun		status = "okay";
573*4882a593Smuzhiyun		compatible = "mpu6500_acc";
574*4882a593Smuzhiyun		reg = <0x68>;
575*4882a593Smuzhiyun		irq-gpio = <&gpio1 RK_PD3 IRQ_TYPE_EDGE_RISING>;
576*4882a593Smuzhiyun		irq_enable = <0>;
577*4882a593Smuzhiyun		poll_delay_ms = <30>;
578*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
579*4882a593Smuzhiyun		layout = <5>;
580*4882a593Smuzhiyun	};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun	mpu6500_gyro: mpu_gyro@68 {
583*4882a593Smuzhiyun		status = "okay";
584*4882a593Smuzhiyun		compatible = "mpu6500_gyro";
585*4882a593Smuzhiyun		reg = <0x68>;
586*4882a593Smuzhiyun		poll_delay_ms = <30>;
587*4882a593Smuzhiyun		type = <SENSOR_TYPE_GYROSCOPE>;
588*4882a593Smuzhiyun		layout = <5>;
589*4882a593Smuzhiyun	};
590*4882a593Smuzhiyun};
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun&i2c6 {
593*4882a593Smuzhiyun	status = "okay";
594*4882a593Smuzhiyun	pinctrl-names = "default";
595*4882a593Smuzhiyun	pinctrl-0 = <&i2c6m3_xfer>;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun	hym8563: hym8563@51 {
598*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
599*4882a593Smuzhiyun		reg = <0x51>;
600*4882a593Smuzhiyun		#clock-cells = <0>;
601*4882a593Smuzhiyun		clock-frequency = <32768>;
602*4882a593Smuzhiyun		clock-output-names = "hym8563";
603*4882a593Smuzhiyun		pinctrl-names = "default";
604*4882a593Smuzhiyun		pinctrl-0 = <&rtc_int>;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
607*4882a593Smuzhiyun		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
608*4882a593Smuzhiyun		wakeup-source;
609*4882a593Smuzhiyun	};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun	cw2015@62 {
612*4882a593Smuzhiyun		status = "okay";
613*4882a593Smuzhiyun		compatible = "cellwise,cw2015";
614*4882a593Smuzhiyun		reg = <0x62>;
615*4882a593Smuzhiyun		cellwise,battery-profile = /bits/ 8
616*4882a593Smuzhiyun			<0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B
617*4882a593Smuzhiyun			 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D
618*4882a593Smuzhiyun			 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49
619*4882a593Smuzhiyun			 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49
620*4882a593Smuzhiyun			 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35
621*4882a593Smuzhiyun			 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17
622*4882a593Smuzhiyun			 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB
623*4882a593Smuzhiyun			 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>;
624*4882a593Smuzhiyun		cellwise,dual-cell = <1>;
625*4882a593Smuzhiyun		cellwise,monitor-interval-ms = <5000>;
626*4882a593Smuzhiyun		power-supplies = <&bq25703>;
627*4882a593Smuzhiyun	};
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun	bq25703: bq25703@6b {
630*4882a593Smuzhiyun		status = "okay";
631*4882a593Smuzhiyun		compatible = "ti,bq25703";
632*4882a593Smuzhiyun		reg = <0x6b>;
633*4882a593Smuzhiyun		ti,usb-charger-detection = <&usbc0>;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
636*4882a593Smuzhiyun		interrupts = <RK_PD5 IRQ_TYPE_LEVEL_LOW>;
637*4882a593Smuzhiyun		otg-mode-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
638*4882a593Smuzhiyun		pinctrl-names = "default";
639*4882a593Smuzhiyun		pinctrl-0 = <&charger_ok>;
640*4882a593Smuzhiyun		extcon = <&u2phy0>;
641*4882a593Smuzhiyun		ti,charge-current = <2500000>;
642*4882a593Smuzhiyun		ti,max-input-voltage = <20000000>;
643*4882a593Smuzhiyun		ti,max-input-current = <6000000>;
644*4882a593Smuzhiyun		ti,max-charge-voltage = <8750000>;
645*4882a593Smuzhiyun		ti,input-current = <500000>;
646*4882a593Smuzhiyun		ti,input-current-sdp = <500000>;
647*4882a593Smuzhiyun		ti,input-current-dcp = <2000000>;
648*4882a593Smuzhiyun		ti,input-current-cdp = <2000000>;
649*4882a593Smuzhiyun		ti,minimum-sys-voltage = <7400000>;
650*4882a593Smuzhiyun		ti,otg-voltage = <5000000>;
651*4882a593Smuzhiyun		ti,otg-current = <1500000>;
652*4882a593Smuzhiyun		pd-charge-only = <0>;
653*4882a593Smuzhiyun		regulators {
654*4882a593Smuzhiyun			vbus5v0_typec: vbus5v0-typec {
655*4882a593Smuzhiyun				regulator-compatible = "otg-vbus";
656*4882a593Smuzhiyun				regulator-name = "vbus5v0_typec";
657*4882a593Smuzhiyun			};
658*4882a593Smuzhiyun		};
659*4882a593Smuzhiyun	};
660*4882a593Smuzhiyun};
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun&i2c7 {
663*4882a593Smuzhiyun	status = "okay";
664*4882a593Smuzhiyun	pinctrl-names = "default";
665*4882a593Smuzhiyun	pinctrl-0 = <&i2c7m2_xfer>;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun	aw8601: aw8601@c {
668*4882a593Smuzhiyun		compatible = "awinic,aw8601";
669*4882a593Smuzhiyun		status = "okay";
670*4882a593Smuzhiyun		reg = <0x0c>;
671*4882a593Smuzhiyun		rockchip,vcm-start-current = <56>;
672*4882a593Smuzhiyun		rockchip,vcm-rated-current = <96>;
673*4882a593Smuzhiyun		rockchip,vcm-step-mode = <4>;
674*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
675*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
676*4882a593Smuzhiyun	};
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun	ov13855: ov13855@10 {
679*4882a593Smuzhiyun		compatible = "ovti,ov13855";
680*4882a593Smuzhiyun		status = "okay";
681*4882a593Smuzhiyun		reg = <0x10>;
682*4882a593Smuzhiyun		clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
683*4882a593Smuzhiyun		clock-names = "xvclk";
684*4882a593Smuzhiyun		power-domains = <&power RK3588_PD_VI>;
685*4882a593Smuzhiyun		pinctrl-names = "default";
686*4882a593Smuzhiyun		pinctrl-0 = <&mipim1_camera4_clk>;
687*4882a593Smuzhiyun		rockchip,grf = <&sys_grf>;
688*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
689*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
690*4882a593Smuzhiyun		avdd-supply = <&vcc_mipidcphy>;
691*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
692*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
693*4882a593Smuzhiyun		rockchip,camera-module-name = "CMK-OT2016-FV1";
694*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
695*4882a593Smuzhiyun		port {
696*4882a593Smuzhiyun			ov13855_out: endpoint {
697*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
698*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
699*4882a593Smuzhiyun			};
700*4882a593Smuzhiyun		};
701*4882a593Smuzhiyun	};
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun	ov50c40: ov50c40@36 {
704*4882a593Smuzhiyun		compatible = "ovti,ov50c40";
705*4882a593Smuzhiyun		status = "okay";
706*4882a593Smuzhiyun		reg = <0x36>;
707*4882a593Smuzhiyun		clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
708*4882a593Smuzhiyun		clock-names = "xvclk";
709*4882a593Smuzhiyun		power-domains = <&power RK3588_PD_VI>;
710*4882a593Smuzhiyun		pinctrl-names = "default";
711*4882a593Smuzhiyun		pinctrl-0 = <&mipim1_camera1_clk>;
712*4882a593Smuzhiyun		rockchip,grf = <&sys_grf>;
713*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
714*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
715*4882a593Smuzhiyun		avdd-supply = <&vcc_mipidcphy>;
716*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
717*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
718*4882a593Smuzhiyun		rockchip,camera-module-name = "HZGA06";
719*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "ZE0082C1";
720*4882a593Smuzhiyun		eeprom-ctrl = <&otp_eeprom>;
721*4882a593Smuzhiyun		lens-focus = <&aw8601>;
722*4882a593Smuzhiyun		port {
723*4882a593Smuzhiyun			ov50c40_out: endpoint {
724*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ov50c40>;
725*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
726*4882a593Smuzhiyun			};
727*4882a593Smuzhiyun		};
728*4882a593Smuzhiyun	};
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun	otp_eeprom: otp_eeprom@50 {
731*4882a593Smuzhiyun		compatible = "rk,otp_eeprom";
732*4882a593Smuzhiyun		status = "okay";
733*4882a593Smuzhiyun		reg = <0x50>;
734*4882a593Smuzhiyun	};
735*4882a593Smuzhiyun};
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun&i2c8 {
738*4882a593Smuzhiyun	status = "okay";
739*4882a593Smuzhiyun	pinctrl-names = "default";
740*4882a593Smuzhiyun	pinctrl-0 = <&i2c8m2_xfer>;
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun	usbc0: fusb302@22 {
743*4882a593Smuzhiyun		compatible = "fcs,fusb302";
744*4882a593Smuzhiyun		reg = <0x22>;
745*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
746*4882a593Smuzhiyun		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
747*4882a593Smuzhiyun		int-n-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
748*4882a593Smuzhiyun		pinctrl-names = "default";
749*4882a593Smuzhiyun		pinctrl-0 = <&usbc0_int>;
750*4882a593Smuzhiyun		vbus-supply = <&vbus5v0_typec>;
751*4882a593Smuzhiyun		status = "okay";
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun		ports {
754*4882a593Smuzhiyun			#address-cells = <1>;
755*4882a593Smuzhiyun			#size-cells = <0>;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun			port@0 {
758*4882a593Smuzhiyun				reg = <0>;
759*4882a593Smuzhiyun				usbc0_role_sw: endpoint@0 {
760*4882a593Smuzhiyun					remote-endpoint = <&dwc3_0_role_switch>;
761*4882a593Smuzhiyun				};
762*4882a593Smuzhiyun			};
763*4882a593Smuzhiyun		};
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun		usb_con: connector {
766*4882a593Smuzhiyun			compatible = "usb-c-connector";
767*4882a593Smuzhiyun			label = "USB-C";
768*4882a593Smuzhiyun			data-role = "dual";
769*4882a593Smuzhiyun			power-role = "dual";
770*4882a593Smuzhiyun			try-power-role = "sink";
771*4882a593Smuzhiyun			op-sink-microwatt = <1000000>;
772*4882a593Smuzhiyun			sink-pdos =
773*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
774*4882a593Smuzhiyun				 PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
775*4882a593Smuzhiyun				 PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
776*4882a593Smuzhiyun			source-pdos =
777*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun			altmodes {
780*4882a593Smuzhiyun				#address-cells = <1>;
781*4882a593Smuzhiyun				#size-cells = <0>;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun				altmode@0 {
784*4882a593Smuzhiyun					reg = <0>;
785*4882a593Smuzhiyun					svid = <0xff01>;
786*4882a593Smuzhiyun					vdo = <0xffffffff>;
787*4882a593Smuzhiyun				};
788*4882a593Smuzhiyun			};
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun			ports {
791*4882a593Smuzhiyun				#address-cells = <1>;
792*4882a593Smuzhiyun				#size-cells = <0>;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun				port@0 {
795*4882a593Smuzhiyun					reg = <0>;
796*4882a593Smuzhiyun					usbc0_orien_sw: endpoint {
797*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_orientation_switch>;
798*4882a593Smuzhiyun					};
799*4882a593Smuzhiyun				};
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun				port@1 {
802*4882a593Smuzhiyun					reg = <1>;
803*4882a593Smuzhiyun					dp_altmode_mux: endpoint {
804*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
805*4882a593Smuzhiyun					};
806*4882a593Smuzhiyun				};
807*4882a593Smuzhiyun			};
808*4882a593Smuzhiyun		};
809*4882a593Smuzhiyun	};
810*4882a593Smuzhiyun};
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun&i2s0_8ch {
813*4882a593Smuzhiyun	status = "okay";
814*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
815*4882a593Smuzhiyun	pinctrl-0 = <&i2s0_lrck
816*4882a593Smuzhiyun		     &i2s0_sclk
817*4882a593Smuzhiyun		     &i2s0_sdi0
818*4882a593Smuzhiyun		     &i2s0_sdo0>;
819*4882a593Smuzhiyun};
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun&iep {
822*4882a593Smuzhiyun	status = "okay";
823*4882a593Smuzhiyun};
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun&iep_mmu {
826*4882a593Smuzhiyun	status = "okay";
827*4882a593Smuzhiyun};
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun&jpegd {
830*4882a593Smuzhiyun	status = "okay";
831*4882a593Smuzhiyun};
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun&jpegd_mmu {
834*4882a593Smuzhiyun	status = "okay";
835*4882a593Smuzhiyun};
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun&jpege_ccu {
838*4882a593Smuzhiyun	status = "okay";
839*4882a593Smuzhiyun};
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun&jpege0 {
842*4882a593Smuzhiyun	status = "okay";
843*4882a593Smuzhiyun};
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun&jpege0_mmu {
846*4882a593Smuzhiyun	status = "okay";
847*4882a593Smuzhiyun};
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun&jpege1 {
850*4882a593Smuzhiyun	status = "okay";
851*4882a593Smuzhiyun};
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun&jpege1_mmu {
854*4882a593Smuzhiyun	status = "okay";
855*4882a593Smuzhiyun};
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun&jpege2 {
858*4882a593Smuzhiyun	status = "okay";
859*4882a593Smuzhiyun};
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun&jpege2_mmu {
862*4882a593Smuzhiyun	status = "okay";
863*4882a593Smuzhiyun};
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun&jpege3 {
866*4882a593Smuzhiyun	status = "okay";
867*4882a593Smuzhiyun};
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun&jpege3_mmu {
870*4882a593Smuzhiyun	status = "okay";
871*4882a593Smuzhiyun};
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun&mipi_dcphy0 {
874*4882a593Smuzhiyun	status = "okay";
875*4882a593Smuzhiyun};
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun&mipi_dcphy1 {
878*4882a593Smuzhiyun	status = "okay";
879*4882a593Smuzhiyun};
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun&mipi0_csi2 {
882*4882a593Smuzhiyun	status = "okay";
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun	ports {
885*4882a593Smuzhiyun		#address-cells = <1>;
886*4882a593Smuzhiyun		#size-cells = <0>;
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun		port@0 {
889*4882a593Smuzhiyun			reg = <0>;
890*4882a593Smuzhiyun			#address-cells = <1>;
891*4882a593Smuzhiyun			#size-cells = <0>;
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun			mipi0_csi2_input: endpoint@1 {
894*4882a593Smuzhiyun				reg = <1>;
895*4882a593Smuzhiyun				remote-endpoint = <&csidcphy0_out>;
896*4882a593Smuzhiyun			};
897*4882a593Smuzhiyun		};
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun		port@1 {
900*4882a593Smuzhiyun			reg = <1>;
901*4882a593Smuzhiyun			#address-cells = <1>;
902*4882a593Smuzhiyun			#size-cells = <0>;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun			mipi0_csi2_output: endpoint@0 {
905*4882a593Smuzhiyun				reg = <0>;
906*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in0>;
907*4882a593Smuzhiyun			};
908*4882a593Smuzhiyun		};
909*4882a593Smuzhiyun	};
910*4882a593Smuzhiyun};
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun&mipi1_csi2 {
913*4882a593Smuzhiyun	status = "okay";
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun	ports {
916*4882a593Smuzhiyun		#address-cells = <1>;
917*4882a593Smuzhiyun		#size-cells = <0>;
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun		port@0 {
920*4882a593Smuzhiyun			reg = <0>;
921*4882a593Smuzhiyun			#address-cells = <1>;
922*4882a593Smuzhiyun			#size-cells = <0>;
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun			mipi1_csi2_input: endpoint@1 {
925*4882a593Smuzhiyun				reg = <1>;
926*4882a593Smuzhiyun				remote-endpoint = <&csidcphy1_out>;
927*4882a593Smuzhiyun			};
928*4882a593Smuzhiyun		};
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun		port@1 {
931*4882a593Smuzhiyun			reg = <1>;
932*4882a593Smuzhiyun			#address-cells = <1>;
933*4882a593Smuzhiyun			#size-cells = <0>;
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun			mipi1_csi2_output: endpoint@0 {
936*4882a593Smuzhiyun				reg = <0>;
937*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in1>;
938*4882a593Smuzhiyun			};
939*4882a593Smuzhiyun		};
940*4882a593Smuzhiyun	};
941*4882a593Smuzhiyun};
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun&mpp_srv {
944*4882a593Smuzhiyun	status = "okay";
945*4882a593Smuzhiyun};
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun&pdm0 {
948*4882a593Smuzhiyun	rockchip,path-map = <2 0 1 3>;
949*4882a593Smuzhiyun	status = "okay";
950*4882a593Smuzhiyun};
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun&pinctrl {
953*4882a593Smuzhiyun	cam {
954*4882a593Smuzhiyun		mipidcphy_pwr: mipidcphy-pwr {
955*4882a593Smuzhiyun			rockchip,pins =
956*4882a593Smuzhiyun				/* camera power en */
957*4882a593Smuzhiyun				<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
958*4882a593Smuzhiyun		};
959*4882a593Smuzhiyun	};
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun	charger {
962*4882a593Smuzhiyun		charger_ok: charger_ok {
963*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
964*4882a593Smuzhiyun		};
965*4882a593Smuzhiyun	};
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun	headphone {
968*4882a593Smuzhiyun		hp_det: hp-det {
969*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
970*4882a593Smuzhiyun		};
971*4882a593Smuzhiyun	};
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun	hym8563 {
974*4882a593Smuzhiyun		rtc_int: rtc-int {
975*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
976*4882a593Smuzhiyun		};
977*4882a593Smuzhiyun	};
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun	sdio-pwrseq {
980*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
981*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
982*4882a593Smuzhiyun		};
983*4882a593Smuzhiyun	};
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun	sdmmc {
986*4882a593Smuzhiyun		sd_s0_pwr: sd-s0-pwr {
987*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
988*4882a593Smuzhiyun		};
989*4882a593Smuzhiyun	};
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun	sensor {
992*4882a593Smuzhiyun		mpu6500_irq_gpio: mpu6500-irq-gpio {
993*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
994*4882a593Smuzhiyun		};
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun		mh248_irq_gpio: mh248-irq-gpio {
997*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
998*4882a593Smuzhiyun		};
999*4882a593Smuzhiyun	};
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun	touch {
1002*4882a593Smuzhiyun		touch_gpio: touch-gpio {
1003*4882a593Smuzhiyun			rockchip,pins =
1004*4882a593Smuzhiyun				<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
1005*4882a593Smuzhiyun				<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1006*4882a593Smuzhiyun		};
1007*4882a593Smuzhiyun	};
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun	usb {
1010*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
1011*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1012*4882a593Smuzhiyun		};
1013*4882a593Smuzhiyun		vcc5v0_usb_en: vcc5v0-usb-en {
1014*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1015*4882a593Smuzhiyun		};
1016*4882a593Smuzhiyun	};
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun	usb-typec {
1019*4882a593Smuzhiyun		usbc0_int: usbc0-int {
1020*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
1021*4882a593Smuzhiyun		};
1022*4882a593Smuzhiyun	};
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun	wireless-bluetooth {
1025*4882a593Smuzhiyun		uart7_gpios: uart7-gpios {
1026*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
1027*4882a593Smuzhiyun		};
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun		bt_reset_gpio: bt-reset-gpio {
1030*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
1031*4882a593Smuzhiyun		};
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun		bt_wake_gpio: bt-wake-gpio {
1034*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
1035*4882a593Smuzhiyun		};
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun		bt_irq_gpio: bt-irq-gpio {
1038*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
1039*4882a593Smuzhiyun		};
1040*4882a593Smuzhiyun	};
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun	wireless-wlan {
1043*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
1044*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
1045*4882a593Smuzhiyun		};
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun		wifi_poweren_gpio: wifi-poweren-gpio {
1048*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
1049*4882a593Smuzhiyun		};
1050*4882a593Smuzhiyun	};
1051*4882a593Smuzhiyun};
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun&pwm14 {
1054*4882a593Smuzhiyun	pinctrl-0 = <&pwm14m1_pins>;
1055*4882a593Smuzhiyun	status = "okay";
1056*4882a593Smuzhiyun};
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun&rga3_core0 {
1059*4882a593Smuzhiyun	status = "okay";
1060*4882a593Smuzhiyun};
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun&rga3_0_mmu {
1063*4882a593Smuzhiyun	status = "okay";
1064*4882a593Smuzhiyun};
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun&rga3_core1 {
1067*4882a593Smuzhiyun	status = "okay";
1068*4882a593Smuzhiyun};
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun&rga3_1_mmu {
1071*4882a593Smuzhiyun	status = "okay";
1072*4882a593Smuzhiyun};
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun&rga2 {
1075*4882a593Smuzhiyun	status = "okay";
1076*4882a593Smuzhiyun};
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun&rkcif {
1079*4882a593Smuzhiyun	status = "okay";
1080*4882a593Smuzhiyun};
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun&rkcif_mipi_lvds {
1083*4882a593Smuzhiyun	status = "okay";
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun	port {
1086*4882a593Smuzhiyun		cif_mipi_in0: endpoint {
1087*4882a593Smuzhiyun			remote-endpoint = <&mipi0_csi2_output>;
1088*4882a593Smuzhiyun		};
1089*4882a593Smuzhiyun	};
1090*4882a593Smuzhiyun};
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
1093*4882a593Smuzhiyun	status = "okay";
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun	port {
1096*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
1097*4882a593Smuzhiyun			remote-endpoint = <&isp1_in1>;
1098*4882a593Smuzhiyun		};
1099*4882a593Smuzhiyun	};
1100*4882a593Smuzhiyun};
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun&rkcif_mipi_lvds1 {
1103*4882a593Smuzhiyun	status = "okay";
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun	port {
1106*4882a593Smuzhiyun		cif_mipi_in1: endpoint {
1107*4882a593Smuzhiyun			remote-endpoint = <&mipi1_csi2_output>;
1108*4882a593Smuzhiyun		};
1109*4882a593Smuzhiyun	};
1110*4882a593Smuzhiyun};
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun&rkcif_mipi_lvds1_sditf {
1113*4882a593Smuzhiyun	status = "okay";
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun	port {
1116*4882a593Smuzhiyun		mipi1_lvds_sditf: endpoint {
1117*4882a593Smuzhiyun			remote-endpoint = <&isp1_in2>;
1118*4882a593Smuzhiyun		};
1119*4882a593Smuzhiyun	};
1120*4882a593Smuzhiyun};
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun&rkcif_mmu {
1123*4882a593Smuzhiyun	status = "okay";
1124*4882a593Smuzhiyun};
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun&rkisp_unite {
1127*4882a593Smuzhiyun	status = "okay";
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun};
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun&rkisp_unite_mmu {
1132*4882a593Smuzhiyun	status = "okay";
1133*4882a593Smuzhiyun};
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun&rkisp0_vir0 {
1136*4882a593Smuzhiyun	status = "okay";
1137*4882a593Smuzhiyun	/*
1138*4882a593Smuzhiyun	 * dual isp process image case
1139*4882a593Smuzhiyun	 * other rkisp hw and virtual nodes should disabled
1140*4882a593Smuzhiyun	 */
1141*4882a593Smuzhiyun	rockchip,hw = <&rkisp_unite>;
1142*4882a593Smuzhiyun	port {
1143*4882a593Smuzhiyun		#address-cells = <1>;
1144*4882a593Smuzhiyun		#size-cells = <0>;
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun		isp1_in1: endpoint@0 {
1147*4882a593Smuzhiyun			reg = <0>;
1148*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds_sditf>;
1149*4882a593Smuzhiyun		};
1150*4882a593Smuzhiyun		isp1_in2: endpoint@1 {
1151*4882a593Smuzhiyun			reg = <1>;
1152*4882a593Smuzhiyun			remote-endpoint = <&mipi1_lvds_sditf>;
1153*4882a593Smuzhiyun		};
1154*4882a593Smuzhiyun	};
1155*4882a593Smuzhiyun};
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun&rknpu {
1158*4882a593Smuzhiyun	rknpu-supply = <&vdd_npu_s0>;
1159*4882a593Smuzhiyun	mem-supply = <&vdd_npu_mem_s0>;
1160*4882a593Smuzhiyun	status = "okay";
1161*4882a593Smuzhiyun};
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun&rknpu_mmu {
1164*4882a593Smuzhiyun	status = "okay";
1165*4882a593Smuzhiyun};
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun&rkvdec_ccu {
1168*4882a593Smuzhiyun	status = "okay";
1169*4882a593Smuzhiyun};
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun&rkvdec0 {
1172*4882a593Smuzhiyun	status = "okay";
1173*4882a593Smuzhiyun};
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun&rkvdec0_mmu {
1176*4882a593Smuzhiyun	status = "okay";
1177*4882a593Smuzhiyun};
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun&rkvdec1 {
1180*4882a593Smuzhiyun	status = "okay";
1181*4882a593Smuzhiyun};
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun&rkvdec1_mmu {
1184*4882a593Smuzhiyun	status = "okay";
1185*4882a593Smuzhiyun};
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun&vepu {
1188*4882a593Smuzhiyun	status = "okay";
1189*4882a593Smuzhiyun};
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun&rkvenc_ccu {
1192*4882a593Smuzhiyun	status = "okay";
1193*4882a593Smuzhiyun};
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun&rkvenc0 {
1196*4882a593Smuzhiyun	venc-supply = <&vdd_vdenc_s0>;
1197*4882a593Smuzhiyun	mem-supply = <&vdd_vdenc_mem_s0>;
1198*4882a593Smuzhiyun	status = "okay";
1199*4882a593Smuzhiyun};
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun&rkvenc0_mmu {
1202*4882a593Smuzhiyun	status = "okay";
1203*4882a593Smuzhiyun};
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun&rkvenc1 {
1206*4882a593Smuzhiyun	venc-supply = <&vdd_vdenc_s0>;
1207*4882a593Smuzhiyun	mem-supply = <&vdd_vdenc_mem_s0>;
1208*4882a593Smuzhiyun	status = "okay";
1209*4882a593Smuzhiyun};
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun&rkvenc1_mmu {
1212*4882a593Smuzhiyun	status = "okay";
1213*4882a593Smuzhiyun};
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun&rockchip_suspend {
1216*4882a593Smuzhiyun	status = "okay";
1217*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
1218*4882a593Smuzhiyun};
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun&route_edp0 {
1221*4882a593Smuzhiyun	connect = <&vp2_out_edp0>;
1222*4882a593Smuzhiyun	status = "okay";
1223*4882a593Smuzhiyun};
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun&saradc {
1226*4882a593Smuzhiyun	status = "okay";
1227*4882a593Smuzhiyun	vref-supply = <&vcc_1v8_s0>;
1228*4882a593Smuzhiyun};
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun&sdhci {
1231*4882a593Smuzhiyun	bus-width = <8>;
1232*4882a593Smuzhiyun	no-sdio;
1233*4882a593Smuzhiyun	no-sd;
1234*4882a593Smuzhiyun	non-removable;
1235*4882a593Smuzhiyun	max-frequency = <200000000>;
1236*4882a593Smuzhiyun	mmc-hs400-1_8v;
1237*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
1238*4882a593Smuzhiyun	status = "okay";
1239*4882a593Smuzhiyun};
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun&sdio {
1242*4882a593Smuzhiyun	max-frequency = <150000000>;
1243*4882a593Smuzhiyun	no-sd;
1244*4882a593Smuzhiyun	no-mmc;
1245*4882a593Smuzhiyun	bus-width = <4>;
1246*4882a593Smuzhiyun	disable-wp;
1247*4882a593Smuzhiyun	cap-sd-highspeed;
1248*4882a593Smuzhiyun	cap-sdio-irq;
1249*4882a593Smuzhiyun	keep-power-in-suspend;
1250*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
1251*4882a593Smuzhiyun	non-removable;
1252*4882a593Smuzhiyun	pinctrl-names = "default";
1253*4882a593Smuzhiyun	pinctrl-0 = <&sdiom1_pins>;
1254*4882a593Smuzhiyun	sd-uhs-sdr104;
1255*4882a593Smuzhiyun	status = "okay";
1256*4882a593Smuzhiyun};
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun&sdmmc {
1259*4882a593Smuzhiyun	max-frequency = <150000000>;
1260*4882a593Smuzhiyun	no-sdio;
1261*4882a593Smuzhiyun	no-mmc;
1262*4882a593Smuzhiyun	bus-width = <4>;
1263*4882a593Smuzhiyun	cap-mmc-highspeed;
1264*4882a593Smuzhiyun	cap-sd-highspeed;
1265*4882a593Smuzhiyun	disable-wp;
1266*4882a593Smuzhiyun	sd-uhs-sdr104;
1267*4882a593Smuzhiyun	vmmc-supply = <&vcc_3v3_sd_s0>;
1268*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd_s0>;
1269*4882a593Smuzhiyun	pinctrl-names = "default";
1270*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
1271*4882a593Smuzhiyun	status = "okay";
1272*4882a593Smuzhiyun};
1273*4882a593Smuzhiyun
1274*4882a593Smuzhiyun&tsadc {
1275*4882a593Smuzhiyun	status = "okay";
1276*4882a593Smuzhiyun};
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun&uart7 {
1279*4882a593Smuzhiyun	pinctrl-names = "default";
1280*4882a593Smuzhiyun	pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn>;
1281*4882a593Smuzhiyun	status = "okay";
1282*4882a593Smuzhiyun};
1283*4882a593Smuzhiyun
1284*4882a593Smuzhiyun&u2phy0 {
1285*4882a593Smuzhiyun	status = "okay";
1286*4882a593Smuzhiyun};
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun&u2phy2 {
1289*4882a593Smuzhiyun	status = "okay";
1290*4882a593Smuzhiyun};
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun&u2phy0_otg {
1293*4882a593Smuzhiyun	rockchip,typec-vbus-det;
1294*4882a593Smuzhiyun	status = "okay";
1295*4882a593Smuzhiyun};
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun&u2phy2_host {
1298*4882a593Smuzhiyun	status = "okay";
1299*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
1300*4882a593Smuzhiyun};
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun&usb_host0_ehci {
1303*4882a593Smuzhiyun	status = "okay";
1304*4882a593Smuzhiyun};
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun&usb_host0_ohci {
1307*4882a593Smuzhiyun	status = "okay";
1308*4882a593Smuzhiyun};
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun&usbdp_phy0 {
1311*4882a593Smuzhiyun	orientation-switch;
1312*4882a593Smuzhiyun	svid = <0xff01>;
1313*4882a593Smuzhiyun	sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
1314*4882a593Smuzhiyun	sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>;
1315*4882a593Smuzhiyun	status = "okay";
1316*4882a593Smuzhiyun
1317*4882a593Smuzhiyun	port {
1318*4882a593Smuzhiyun		#address-cells = <1>;
1319*4882a593Smuzhiyun		#size-cells = <0>;
1320*4882a593Smuzhiyun		usbdp_phy0_orientation_switch: endpoint@0 {
1321*4882a593Smuzhiyun			reg = <0>;
1322*4882a593Smuzhiyun			remote-endpoint = <&usbc0_orien_sw>;
1323*4882a593Smuzhiyun		};
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun		usbdp_phy0_dp_altmode_mux: endpoint@1 {
1326*4882a593Smuzhiyun			reg = <1>;
1327*4882a593Smuzhiyun			remote-endpoint = <&dp_altmode_mux>;
1328*4882a593Smuzhiyun		};
1329*4882a593Smuzhiyun	};
1330*4882a593Smuzhiyun};
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun&usbdp_phy0_dp {
1333*4882a593Smuzhiyun	status = "okay";
1334*4882a593Smuzhiyun};
1335*4882a593Smuzhiyun
1336*4882a593Smuzhiyun&usbdp_phy0_u3 {
1337*4882a593Smuzhiyun	status = "okay";
1338*4882a593Smuzhiyun};
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun&usbdrd3_0 {
1341*4882a593Smuzhiyun	status = "okay";
1342*4882a593Smuzhiyun};
1343*4882a593Smuzhiyun
1344*4882a593Smuzhiyun&usbdrd_dwc3_0 {
1345*4882a593Smuzhiyun	dr_mode = "otg";
1346*4882a593Smuzhiyun	status = "okay";
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun	usb-role-switch;
1349*4882a593Smuzhiyun	port {
1350*4882a593Smuzhiyun		#address-cells = <1>;
1351*4882a593Smuzhiyun		#size-cells = <0>;
1352*4882a593Smuzhiyun		dwc3_0_role_switch: endpoint@0 {
1353*4882a593Smuzhiyun			reg = <0>;
1354*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
1355*4882a593Smuzhiyun		};
1356*4882a593Smuzhiyun	};
1357*4882a593Smuzhiyun};
1358*4882a593Smuzhiyun
1359*4882a593Smuzhiyun&usbhost3_0 {
1360*4882a593Smuzhiyun	status = "disabled";
1361*4882a593Smuzhiyun};
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun&usbhost_dwc3_0 {
1364*4882a593Smuzhiyun	status = "disabled";
1365*4882a593Smuzhiyun};
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun&vdpu {
1368*4882a593Smuzhiyun	status = "okay";
1369*4882a593Smuzhiyun};
1370*4882a593Smuzhiyun
1371*4882a593Smuzhiyun&vdpu_mmu {
1372*4882a593Smuzhiyun	status = "okay";
1373*4882a593Smuzhiyun};
1374*4882a593Smuzhiyun
1375*4882a593Smuzhiyun&vop {
1376*4882a593Smuzhiyun	status = "okay";
1377*4882a593Smuzhiyun};
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun&vop_mmu {
1380*4882a593Smuzhiyun	status = "okay";
1381*4882a593Smuzhiyun};
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun&vp1 {
1384*4882a593Smuzhiyun	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 |
1385*4882a593Smuzhiyun				1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
1386*4882a593Smuzhiyun	rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
1387*4882a593Smuzhiyun};
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun&vp2 {
1390*4882a593Smuzhiyun	rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 |
1391*4882a593Smuzhiyun				1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
1392*4882a593Smuzhiyun	rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
1393*4882a593Smuzhiyun};
1394